timer.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <time.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/spr_gpt.h>
  12. #include <asm/arch/spr_misc.h>
  13. #define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
  14. #define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
  15. static struct gpt_regs *const gpt_regs_p =
  16. (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
  17. static struct misc_regs *const misc_regs_p =
  18. (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static ulong get_timer_masked(void);
  21. #define timestamp gd->arch.tbl
  22. #define lastdec gd->arch.lastinc
  23. int timer_init(void)
  24. {
  25. u32 synth;
  26. /* Prescaler setting */
  27. #if defined(CONFIG_SPEAR3XX)
  28. writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
  29. synth = MISC_GPT4SYNTH;
  30. #elif defined(CONFIG_SPEAR600)
  31. writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
  32. synth = MISC_GPT3SYNTH;
  33. #else
  34. # error Incorrect config. Can only be SPEAR{600|300|310|320}
  35. #endif
  36. writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
  37. &misc_regs_p->periph_clk_cfg);
  38. /* disable timers */
  39. writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
  40. /* load value for free running */
  41. writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
  42. /* auto reload, start timer */
  43. writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
  44. /* Reset the timer */
  45. lastdec = READ_TIMER();
  46. timestamp = 0;
  47. return 0;
  48. }
  49. /*
  50. * timer without interrupts
  51. */
  52. ulong get_timer(ulong base)
  53. {
  54. return (get_timer_masked() / GPT_RESOLUTION) - base;
  55. }
  56. void __udelay(unsigned long usec)
  57. {
  58. ulong tmo;
  59. ulong start = get_timer_masked();
  60. ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
  61. ulong rndoff;
  62. rndoff = (usec % 10) ? 1 : 0;
  63. /* tenudelcnt timer tick gives 10 microsecconds delay */
  64. tmo = ((usec / 10) + rndoff) * tenudelcnt;
  65. while ((ulong) (get_timer_masked() - start) < tmo)
  66. ;
  67. }
  68. static ulong get_timer_masked(void)
  69. {
  70. ulong now = READ_TIMER();
  71. if (now >= lastdec) {
  72. /* normal mode */
  73. timestamp += now - lastdec;
  74. } else {
  75. /* we have an overflow ... */
  76. timestamp += now + GPT_FREE_RUNNING - lastdec;
  77. }
  78. lastdec = now;
  79. return timestamp;
  80. }
  81. /*
  82. * This function is derived from PowerPC code (read timebase as long long).
  83. * On ARM it just returns the timer value.
  84. */
  85. unsigned long long get_ticks(void)
  86. {
  87. return get_timer(0);
  88. }
  89. /*
  90. * This function is derived from PowerPC code (timebase clock frequency).
  91. * On ARM it returns the number of timer ticks per second.
  92. */
  93. ulong get_tbclk(void)
  94. {
  95. return CONFIG_SPEAR_HZ;
  96. }