timer.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <time.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/armada100.h>
  14. /*
  15. * Timer registers
  16. * Refer Section A.6 in Datasheet
  17. */
  18. struct armd1tmr_registers {
  19. u32 clk_ctrl; /* Timer clk control reg */
  20. u32 match[9]; /* Timer match registers */
  21. u32 count[3]; /* Timer count registers */
  22. u32 status[3];
  23. u32 ie[3];
  24. u32 preload[3]; /* Timer preload value */
  25. u32 preload_ctrl[3];
  26. u32 wdt_match_en;
  27. u32 wdt_match_r;
  28. u32 wdt_val;
  29. u32 wdt_sts;
  30. u32 icr[3];
  31. u32 wdt_icr;
  32. u32 cer; /* Timer count enable reg */
  33. u32 cmr;
  34. u32 ilr[3];
  35. u32 wcr;
  36. u32 wfar;
  37. u32 wsar;
  38. u32 cvwr;
  39. };
  40. #define TIMER 0 /* Use TIMER 0 */
  41. /* Each timer has 3 match registers */
  42. #define MATCH_CMP(x) ((3 * TIMER) + x)
  43. #define TIMER_LOAD_VAL 0xffffffff
  44. #define COUNT_RD_REQ 0x1
  45. DECLARE_GLOBAL_DATA_PTR;
  46. /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
  47. /* For preventing risk of instability in reading counter value,
  48. * first set read request to register cvwr and then read same
  49. * register after it captures counter value.
  50. */
  51. ulong read_timer(void)
  52. {
  53. struct armd1tmr_registers *armd1timers =
  54. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  55. volatile int loop=100;
  56. writel(COUNT_RD_REQ, &armd1timers->cvwr);
  57. while (loop--);
  58. return(readl(&armd1timers->cvwr));
  59. }
  60. static ulong get_timer_masked(void)
  61. {
  62. ulong now = read_timer();
  63. if (now >= gd->arch.tbl) {
  64. /* normal mode */
  65. gd->arch.tbu += now - gd->arch.tbl;
  66. } else {
  67. /* we have an overflow ... */
  68. gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
  69. }
  70. gd->arch.tbl = now;
  71. return gd->arch.tbu;
  72. }
  73. ulong get_timer(ulong base)
  74. {
  75. return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
  76. base);
  77. }
  78. void __udelay(unsigned long usec)
  79. {
  80. ulong delayticks;
  81. ulong endtime;
  82. delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
  83. endtime = get_timer_masked() + delayticks;
  84. while (get_timer_masked() < endtime);
  85. }
  86. /*
  87. * init the Timer
  88. */
  89. int timer_init(void)
  90. {
  91. struct armd1apb1_registers *apb1clkres =
  92. (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  93. struct armd1tmr_registers *armd1timers =
  94. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  95. /* Enable Timer clock at 3.25 MHZ */
  96. writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
  97. /* load value into timer */
  98. writel(0x0, &armd1timers->clk_ctrl);
  99. /* Use Timer 0 Match Resiger 0 */
  100. writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
  101. /* Preload value is 0 */
  102. writel(0x0, &armd1timers->preload[TIMER]);
  103. /* Enable match comparator 0 for Timer 0 */
  104. writel(0x1, &armd1timers->preload_ctrl[TIMER]);
  105. /* Enable timer 0 */
  106. writel(0x1, &armd1timers->cer);
  107. /* init the gd->arch.tbu and gd->arch.tbl value */
  108. gd->arch.tbl = read_timer();
  109. gd->arch.tbu = 0;
  110. return 0;
  111. }
  112. #define MPMU_APRR_WDTR (1<<4)
  113. #define TMR_WFAR 0xbaba /* WDT Register First key */
  114. #define TMP_WSAR 0xeb10 /* WDT Register Second key */
  115. /*
  116. * This function uses internal Watchdog Timer
  117. * based reset mechanism.
  118. * Steps to write watchdog registers (protected access)
  119. * 1. Write key value to TMR_WFAR reg.
  120. * 2. Write key value to TMP_WSAR reg.
  121. * 3. Perform write operation.
  122. */
  123. void reset_cpu(unsigned long ignored)
  124. {
  125. struct armd1mpmu_registers *mpmu =
  126. (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  127. struct armd1tmr_registers *armd1timers =
  128. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  129. u32 val;
  130. /* negate hardware reset to the WDT after system reset */
  131. val = readl(&mpmu->aprr);
  132. val = val | MPMU_APRR_WDTR;
  133. writel(val, &mpmu->aprr);
  134. /* reset/enable WDT clock */
  135. writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
  136. readl(&mpmu->wdtpcr);
  137. writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
  138. readl(&mpmu->wdtpcr);
  139. /* clear previous WDT status */
  140. writel(TMR_WFAR, &armd1timers->wfar);
  141. writel(TMP_WSAR, &armd1timers->wsar);
  142. writel(0, &armd1timers->wdt_sts);
  143. /* set match counter */
  144. writel(TMR_WFAR, &armd1timers->wfar);
  145. writel(TMP_WSAR, &armd1timers->wsar);
  146. writel(0xf, &armd1timers->wdt_match_r);
  147. /* enable WDT reset */
  148. writel(TMR_WFAR, &armd1timers->wfar);
  149. writel(TMP_WSAR, &armd1timers->wsar);
  150. writel(0x3, &armd1timers->wdt_match_en);
  151. while(1);
  152. }
  153. /*
  154. * This function is derived from PowerPC code (read timebase as long long).
  155. * On ARM it just returns the timer value.
  156. */
  157. unsigned long long get_ticks(void)
  158. {
  159. return get_timer(0);
  160. }
  161. /*
  162. * This function is derived from PowerPC code (timebase clock frequency).
  163. * On ARM it returns the number of timer ticks per second.
  164. */
  165. ulong get_tbclk(void)
  166. {
  167. return (ulong)CONFIG_SYS_HZ;
  168. }