generic.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <div64.h>
  11. #include <init.h>
  12. #include <net.h>
  13. #include <asm/io.h>
  14. #include <linux/errno.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #ifdef CONFIG_FSL_ESDHC_IMX
  20. #include <fsl_esdhc_imx.h>
  21. #endif
  22. #include <netdev.h>
  23. #include <spl.h>
  24. #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  25. #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
  26. #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
  27. #define CLK_CODE_PATH(c) ((c) & 0xFF)
  28. #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  29. #ifdef CONFIG_FSL_ESDHC_IMX
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #endif
  32. static int g_clk_mux_auto[8] = {
  33. CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  34. CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  35. };
  36. static int g_clk_mux_consumer[16] = {
  37. CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  38. -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  39. CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  40. -1, -1, CLK_CODE(4, 2, 0), -1,
  41. };
  42. static int hsp_div_table[3][16] = {
  43. {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  44. {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  45. {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  46. };
  47. u32 get_cpu_rev(void)
  48. {
  49. int reg;
  50. struct iim_regs *iim =
  51. (struct iim_regs *)IIM_BASE_ADDR;
  52. reg = readl(&iim->iim_srev);
  53. if (!reg) {
  54. reg = readw(ROMPATCH_REV);
  55. reg <<= 4;
  56. } else {
  57. reg += CHIP_REV_1_0;
  58. }
  59. return 0x35000 + (reg & 0xFF);
  60. }
  61. static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  62. {
  63. int *pclk_mux;
  64. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  65. pclk_mux = g_clk_mux_consumer +
  66. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  67. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  68. } else {
  69. pclk_mux = g_clk_mux_auto +
  70. ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  71. MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  72. }
  73. if ((*pclk_mux) == -1)
  74. return -1;
  75. if (fi && fd) {
  76. if (!CLK_CODE_PATH(*pclk_mux)) {
  77. *fi = *fd = 1;
  78. return CLK_CODE_ARM(*pclk_mux);
  79. }
  80. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  81. *fi = 3;
  82. *fd = 4;
  83. } else {
  84. *fi = 2;
  85. *fd = 3;
  86. }
  87. }
  88. return CLK_CODE_ARM(*pclk_mux);
  89. }
  90. static int get_ahb_div(u32 pdr0)
  91. {
  92. int *pclk_mux;
  93. pclk_mux = g_clk_mux_consumer +
  94. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  95. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  96. if ((*pclk_mux) == -1)
  97. return -1;
  98. return CLK_CODE_AHB(*pclk_mux);
  99. }
  100. static u32 decode_pll(u32 reg, u32 infreq)
  101. {
  102. u32 mfi = (reg >> 10) & 0xf;
  103. s32 mfn = reg & 0x3ff;
  104. u32 mfd = (reg >> 16) & 0x3ff;
  105. u32 pd = (reg >> 26) & 0xf;
  106. mfi = mfi <= 5 ? 5 : mfi;
  107. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  108. mfd += 1;
  109. pd += 1;
  110. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  111. mfd * pd);
  112. }
  113. static u32 get_mcu_main_clk(void)
  114. {
  115. u32 arm_div = 0, fi = 0, fd = 0;
  116. struct ccm_regs *ccm =
  117. (struct ccm_regs *)IMX_CCM_BASE;
  118. arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
  119. fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
  120. return fi / (arm_div * fd);
  121. }
  122. static u32 get_ipg_clk(void)
  123. {
  124. u32 freq = get_mcu_main_clk();
  125. struct ccm_regs *ccm =
  126. (struct ccm_regs *)IMX_CCM_BASE;
  127. u32 pdr0 = readl(&ccm->pdr0);
  128. return freq / (get_ahb_div(pdr0) * 2);
  129. }
  130. static u32 get_ipg_per_clk(void)
  131. {
  132. u32 freq = get_mcu_main_clk();
  133. struct ccm_regs *ccm =
  134. (struct ccm_regs *)IMX_CCM_BASE;
  135. u32 pdr0 = readl(&ccm->pdr0);
  136. u32 pdr4 = readl(&ccm->pdr4);
  137. u32 div;
  138. if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
  139. div = CCM_GET_DIVIDER(pdr4,
  140. MXC_CCM_PDR4_PER0_PODF_MASK,
  141. MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
  142. } else {
  143. div = CCM_GET_DIVIDER(pdr0,
  144. MXC_CCM_PDR0_PER_PODF_MASK,
  145. MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
  146. div *= get_ahb_div(pdr0);
  147. }
  148. return freq / div;
  149. }
  150. u32 imx_get_uartclk(void)
  151. {
  152. u32 freq;
  153. struct ccm_regs *ccm =
  154. (struct ccm_regs *)IMX_CCM_BASE;
  155. u32 pdr4 = readl(&ccm->pdr4);
  156. if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
  157. freq = get_mcu_main_clk();
  158. else
  159. freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  160. freq /= CCM_GET_DIVIDER(pdr4,
  161. MXC_CCM_PDR4_UART_PODF_MASK,
  162. MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
  163. return freq;
  164. }
  165. unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
  166. {
  167. u32 nfc_pdf, hsp_podf;
  168. u32 pll, ret_val = 0, usb_podf;
  169. struct ccm_regs *ccm =
  170. (struct ccm_regs *)IMX_CCM_BASE;
  171. u32 reg = readl(&ccm->pdr0);
  172. u32 reg4 = readl(&ccm->pdr4);
  173. reg |= 0x1;
  174. switch (clk) {
  175. case CPU_CLK:
  176. ret_val = get_mcu_main_clk();
  177. break;
  178. case AHB_CLK:
  179. ret_val = get_mcu_main_clk();
  180. break;
  181. case HSP_CLK:
  182. if (reg & CLKMODE_CONSUMER) {
  183. hsp_podf = (reg >> 20) & 0x3;
  184. pll = get_mcu_main_clk();
  185. hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
  186. if (hsp_podf > 0) {
  187. ret_val = pll / hsp_podf;
  188. } else {
  189. puts("mismatch HSP with ARM clock setting\n");
  190. ret_val = 0;
  191. }
  192. } else {
  193. ret_val = get_mcu_main_clk();
  194. }
  195. break;
  196. case IPG_CLK:
  197. ret_val = get_ipg_clk();
  198. break;
  199. case IPG_PER_CLK:
  200. ret_val = get_ipg_per_clk();
  201. break;
  202. case NFC_CLK:
  203. nfc_pdf = (reg4 >> 28) & 0xF;
  204. pll = get_mcu_main_clk();
  205. /* AHB/nfc_pdf */
  206. ret_val = pll / (nfc_pdf + 1);
  207. break;
  208. case USB_CLK:
  209. usb_podf = (reg4 >> 22) & 0x3F;
  210. if (reg4 & 0x200)
  211. pll = get_mcu_main_clk();
  212. else
  213. pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  214. ret_val = pll / (usb_podf + 1);
  215. break;
  216. default:
  217. printf("Unknown clock: %d\n", clk);
  218. break;
  219. }
  220. return ret_val;
  221. }
  222. unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
  223. {
  224. u32 ret_val = 0, pdf, pre_pdf, clk_sel;
  225. struct ccm_regs *ccm =
  226. (struct ccm_regs *)IMX_CCM_BASE;
  227. u32 mpdr2 = readl(&ccm->pdr2);
  228. u32 mpdr3 = readl(&ccm->pdr3);
  229. u32 mpdr4 = readl(&ccm->pdr4);
  230. switch (clk) {
  231. case UART1_BAUD:
  232. case UART2_BAUD:
  233. case UART3_BAUD:
  234. clk_sel = mpdr3 & (1 << 14);
  235. pdf = (mpdr4 >> 10) & 0x3F;
  236. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  237. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  238. break;
  239. case SSI1_BAUD:
  240. pre_pdf = (mpdr2 >> 24) & 0x7;
  241. pdf = mpdr2 & 0x3F;
  242. clk_sel = mpdr2 & (1 << 6);
  243. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  244. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  245. ((pre_pdf + 1) * (pdf + 1));
  246. break;
  247. case SSI2_BAUD:
  248. pre_pdf = (mpdr2 >> 27) & 0x7;
  249. pdf = (mpdr2 >> 8) & 0x3F;
  250. clk_sel = mpdr2 & (1 << 6);
  251. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  252. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  253. ((pre_pdf + 1) * (pdf + 1));
  254. break;
  255. case CSI_BAUD:
  256. clk_sel = mpdr2 & (1 << 7);
  257. pdf = (mpdr2 >> 16) & 0x3F;
  258. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  259. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  260. break;
  261. case MSHC_CLK:
  262. pre_pdf = readl(&ccm->pdr1);
  263. clk_sel = (pre_pdf & 0x80);
  264. pdf = (pre_pdf >> 22) & 0x3F;
  265. pre_pdf = (pre_pdf >> 28) & 0x7;
  266. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  267. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  268. ((pre_pdf + 1) * (pdf + 1));
  269. break;
  270. case ESDHC1_CLK:
  271. clk_sel = mpdr3 & 0x40;
  272. pdf = mpdr3 & 0x3F;
  273. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  274. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  275. break;
  276. case ESDHC2_CLK:
  277. clk_sel = mpdr3 & 0x40;
  278. pdf = (mpdr3 >> 8) & 0x3F;
  279. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  280. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  281. break;
  282. case ESDHC3_CLK:
  283. clk_sel = mpdr3 & 0x40;
  284. pdf = (mpdr3 >> 16) & 0x3F;
  285. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  286. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  287. break;
  288. case SPDIF_CLK:
  289. clk_sel = mpdr3 & 0x400000;
  290. pre_pdf = (mpdr3 >> 29) & 0x7;
  291. pdf = (mpdr3 >> 23) & 0x3F;
  292. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  293. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  294. ((pre_pdf + 1) * (pdf + 1));
  295. break;
  296. default:
  297. printf("%s(): This clock: %d not supported yet\n",
  298. __func__, clk);
  299. break;
  300. }
  301. return ret_val;
  302. }
  303. unsigned int mxc_get_clock(enum mxc_clock clk)
  304. {
  305. switch (clk) {
  306. case MXC_ARM_CLK:
  307. return get_mcu_main_clk();
  308. case MXC_AHB_CLK:
  309. break;
  310. case MXC_IPG_CLK:
  311. return get_ipg_clk();
  312. case MXC_IPG_PERCLK:
  313. case MXC_I2C_CLK:
  314. return get_ipg_per_clk();
  315. case MXC_UART_CLK:
  316. return imx_get_uartclk();
  317. case MXC_ESDHC1_CLK:
  318. return mxc_get_peri_clock(ESDHC1_CLK);
  319. case MXC_ESDHC2_CLK:
  320. return mxc_get_peri_clock(ESDHC2_CLK);
  321. case MXC_ESDHC3_CLK:
  322. return mxc_get_peri_clock(ESDHC3_CLK);
  323. case MXC_USB_CLK:
  324. return mxc_get_main_clock(USB_CLK);
  325. case MXC_FEC_CLK:
  326. return get_ipg_clk();
  327. case MXC_CSPI_CLK:
  328. return get_ipg_clk();
  329. }
  330. return -1;
  331. }
  332. #ifdef CONFIG_FEC_MXC
  333. /*
  334. * The MX35 has no fuse for MAC, return a NULL MAC
  335. */
  336. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  337. {
  338. memset(mac, 0, 6);
  339. }
  340. u32 imx_get_fecclk(void)
  341. {
  342. return mxc_get_clock(MXC_IPG_CLK);
  343. }
  344. #endif
  345. int do_mx35_showclocks(cmd_tbl_t *cmdtp,
  346. int flag, int argc, char * const argv[])
  347. {
  348. u32 cpufreq = get_mcu_main_clk();
  349. printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
  350. printf("ipg clock : %dHz\n", get_ipg_clk());
  351. printf("ipg per clock : %dHz\n", get_ipg_per_clk());
  352. printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
  353. return 0;
  354. }
  355. U_BOOT_CMD(
  356. clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
  357. "display clocks",
  358. ""
  359. );
  360. #if defined(CONFIG_DISPLAY_CPUINFO)
  361. static char *get_reset_cause(void)
  362. {
  363. /* read RCSR register from CCM module */
  364. struct ccm_regs *ccm =
  365. (struct ccm_regs *)IMX_CCM_BASE;
  366. u32 cause = readl(&ccm->rcsr) & 0x0F;
  367. switch (cause) {
  368. case 0x0000:
  369. return "POR";
  370. case 0x0002:
  371. return "JTAG";
  372. case 0x0004:
  373. return "RST";
  374. case 0x0008:
  375. return "WDOG";
  376. default:
  377. return "unknown reset";
  378. }
  379. }
  380. int print_cpuinfo(void)
  381. {
  382. u32 srev = get_cpu_rev();
  383. printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
  384. (srev & 0xF0) >> 4, (srev & 0x0F),
  385. get_mcu_main_clk() / 1000000);
  386. printf("Reset cause: %s\n", get_reset_cause());
  387. return 0;
  388. }
  389. #endif
  390. /*
  391. * Initializes on-chip ethernet controllers.
  392. * to override, implement board_eth_init()
  393. */
  394. int cpu_eth_init(bd_t *bis)
  395. {
  396. int rc = -ENODEV;
  397. #if defined(CONFIG_FEC_MXC)
  398. rc = fecmxc_initialize(bis);
  399. #endif
  400. return rc;
  401. }
  402. #ifdef CONFIG_FSL_ESDHC_IMX
  403. /*
  404. * Initializes on-chip MMC controllers.
  405. * to override, implement board_mmc_init()
  406. */
  407. int cpu_mmc_init(bd_t *bis)
  408. {
  409. return fsl_esdhc_mmc_init(bis);
  410. }
  411. #endif
  412. int get_clocks(void)
  413. {
  414. #ifdef CONFIG_FSL_ESDHC_IMX
  415. #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
  416. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  417. #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
  418. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  419. #else
  420. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  421. #endif
  422. #endif
  423. return 0;
  424. }
  425. #define RCSR_MEM_CTL_WEIM 0
  426. #define RCSR_MEM_CTL_NAND 1
  427. #define RCSR_MEM_CTL_ATA 2
  428. #define RCSR_MEM_CTL_EXPANSION 3
  429. #define RCSR_MEM_TYPE_NOR 0
  430. #define RCSR_MEM_TYPE_ONENAND 2
  431. #define RCSR_MEM_TYPE_SD 0
  432. #define RCSR_MEM_TYPE_I2C 2
  433. #define RCSR_MEM_TYPE_SPI 3
  434. u32 spl_boot_device(void)
  435. {
  436. struct ccm_regs *ccm =
  437. (struct ccm_regs *)IMX_CCM_BASE;
  438. u32 rcsr = readl(&ccm->rcsr);
  439. u32 mem_type, mem_ctl;
  440. /* In external mode, no boot device is returned */
  441. if ((rcsr >> 10) & 0x03)
  442. return BOOT_DEVICE_NONE;
  443. mem_ctl = (rcsr >> 25) & 0x03;
  444. mem_type = (rcsr >> 23) & 0x03;
  445. switch (mem_ctl) {
  446. case RCSR_MEM_CTL_WEIM:
  447. switch (mem_type) {
  448. case RCSR_MEM_TYPE_NOR:
  449. return BOOT_DEVICE_NOR;
  450. case RCSR_MEM_TYPE_ONENAND:
  451. return BOOT_DEVICE_ONENAND;
  452. default:
  453. return BOOT_DEVICE_NONE;
  454. }
  455. case RCSR_MEM_CTL_NAND:
  456. return BOOT_DEVICE_NAND;
  457. case RCSR_MEM_CTL_EXPANSION:
  458. switch (mem_type) {
  459. case RCSR_MEM_TYPE_SD:
  460. return BOOT_DEVICE_MMC1;
  461. case RCSR_MEM_TYPE_I2C:
  462. return BOOT_DEVICE_I2C;
  463. case RCSR_MEM_TYPE_SPI:
  464. return BOOT_DEVICE_SPI;
  465. default:
  466. return BOOT_DEVICE_NONE;
  467. }
  468. }
  469. return BOOT_DEVICE_NONE;
  470. }