omap_wdt.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * omap_wdt.c
  4. *
  5. * (C) Copyright 2013
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. *
  10. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  11. *
  12. * commit 2d991a164a61858012651e13c59521975504e260
  13. * Author: Bill Pemberton <wfp5p@virginia.edu>
  14. * Date: Mon Nov 19 13:21:41 2012 -0500
  15. *
  16. * watchdog: remove use of __devinit
  17. *
  18. * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
  19. * needed.
  20. *
  21. * Author: MontaVista Software, Inc.
  22. * <gdavis@mvista.com> or <source@mvista.com>
  23. *
  24. * History:
  25. *
  26. * 20030527: George G. Davis <gdavis@mvista.com>
  27. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  28. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  29. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  30. *
  31. * Copyright (c) 2004 Texas Instruments.
  32. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  33. * 2. Ported to 2.6 kernel
  34. *
  35. * Copyright (c) 2005 David Brownell
  36. * Use the driver model and standard identifiers; handle bigger timeouts.
  37. */
  38. #include <common.h>
  39. #include <watchdog.h>
  40. #include <asm/arch/hardware.h>
  41. #include <asm/io.h>
  42. #include <asm/processor.h>
  43. #include <asm/arch/cpu.h>
  44. #include <wdt.h>
  45. #include <dm.h>
  46. #include <errno.h>
  47. /* Hardware timeout in seconds */
  48. #define WDT_HW_TIMEOUT 60
  49. #if !CONFIG_IS_ENABLED(WDT)
  50. static unsigned int wdt_trgr_pattern = 0x1234;
  51. void hw_watchdog_reset(void)
  52. {
  53. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  54. /*
  55. * Somebody just triggered watchdog reset and write to WTGR register
  56. * is in progress. It is resetting right now, no need to trigger it
  57. * again
  58. */
  59. if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
  60. return;
  61. wdt_trgr_pattern = ~wdt_trgr_pattern;
  62. writel(wdt_trgr_pattern, &wdt->wdtwtgr);
  63. /*
  64. * Don't wait for posted write to complete, i.e. don't check
  65. * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
  66. * WTGR register outside of this func, and if entering it
  67. * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
  68. * was just triggered. This prevents us from wasting time in busy
  69. * polling of WDT_WWPS_PEND_WTGR bit.
  70. */
  71. }
  72. static int omap_wdt_set_timeout(unsigned int timeout)
  73. {
  74. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  75. u32 pre_margin = GET_WLDR_VAL(timeout);
  76. /* just count up at 32 KHz */
  77. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
  78. ;
  79. writel(pre_margin, &wdt->wdtwldr);
  80. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
  81. ;
  82. return 0;
  83. }
  84. void hw_watchdog_disable(void)
  85. {
  86. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  87. /*
  88. * Disable watchdog
  89. */
  90. writel(0xAAAA, &wdt->wdtwspr);
  91. while (readl(&wdt->wdtwwps) != 0x0)
  92. ;
  93. writel(0x5555, &wdt->wdtwspr);
  94. while (readl(&wdt->wdtwwps) != 0x0)
  95. ;
  96. }
  97. void hw_watchdog_init(void)
  98. {
  99. struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
  100. /*
  101. * Make sure the watchdog is disabled. This is unfortunately required
  102. * because writing to various registers with the watchdog running has no
  103. * effect.
  104. */
  105. hw_watchdog_disable();
  106. /* initialize prescaler */
  107. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
  108. ;
  109. writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
  110. while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
  111. ;
  112. omap_wdt_set_timeout(WDT_HW_TIMEOUT);
  113. /* Sequence to enable the watchdog */
  114. writel(0xBBBB, &wdt->wdtwspr);
  115. while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  116. ;
  117. writel(0x4444, &wdt->wdtwspr);
  118. while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  119. ;
  120. }
  121. void watchdog_reset(void)
  122. {
  123. hw_watchdog_reset();
  124. }
  125. #else
  126. static int omap3_wdt_reset(struct udevice *dev)
  127. {
  128. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  129. priv->wdt_trgr_pattern = 0x1234;
  130. /*
  131. * Somebody just triggered watchdog reset and write to WTGR register
  132. * is in progress. It is resetting right now, no need to trigger it
  133. * again
  134. */
  135. if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
  136. return 0;
  137. priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
  138. writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
  139. /*
  140. * Don't wait for posted write to complete, i.e. don't check
  141. * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
  142. * WTGR register outside of this func, and if entering it
  143. * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
  144. * was just triggered. This prevents us from wasting time in busy
  145. * polling of WDT_WWPS_PEND_WTGR bit.
  146. */
  147. return 0;
  148. }
  149. static int omap3_wdt_stop(struct udevice *dev)
  150. {
  151. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  152. /* disable watchdog */
  153. writel(0xAAAA, &priv->regs->wdtwspr);
  154. while (readl(&priv->regs->wdtwwps) != 0x0)
  155. ;
  156. writel(0x5555, &priv->regs->wdtwspr);
  157. while (readl(&priv->regs->wdtwwps) != 0x0)
  158. ;
  159. return 0;
  160. }
  161. static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
  162. {
  163. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  164. u32 pre_margin = GET_WLDR_VAL(timeout_ms);
  165. /*
  166. * Make sure the watchdog is disabled. This is unfortunately required
  167. * because writing to various registers with the watchdog running has no
  168. * effect.
  169. */
  170. omap3_wdt_stop(dev);
  171. /* initialize prescaler */
  172. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
  173. ;
  174. writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
  175. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
  176. ;
  177. /* just count up at 32 KHz */
  178. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
  179. ;
  180. writel(pre_margin, &priv->regs->wdtwldr);
  181. while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
  182. ;
  183. /* Sequence to enable the watchdog */
  184. writel(0xBBBB, &priv->regs->wdtwspr);
  185. while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  186. ;
  187. writel(0x4444, &priv->regs->wdtwspr);
  188. while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
  189. ;
  190. return 0;
  191. }
  192. static int omap3_wdt_probe(struct udevice *dev)
  193. {
  194. struct omap3_wdt_priv *priv = dev_get_priv(dev);
  195. priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
  196. if (!priv->regs)
  197. return -EINVAL;
  198. debug("%s: Probing wdt%u\n", __func__, dev->seq);
  199. return 0;
  200. }
  201. static const struct wdt_ops omap3_wdt_ops = {
  202. .start = omap3_wdt_start,
  203. .stop = omap3_wdt_stop,
  204. .reset = omap3_wdt_reset,
  205. };
  206. static const struct udevice_id omap3_wdt_ids[] = {
  207. { .compatible = "ti,omap3-wdt" },
  208. { }
  209. };
  210. U_BOOT_DRIVER(omap3_wdt) = {
  211. .name = "omap3_wdt",
  212. .id = UCLASS_WDT,
  213. .of_match = omap3_wdt_ids,
  214. .ops = &omap3_wdt_ops,
  215. .probe = omap3_wdt_probe,
  216. .priv_auto_alloc_size = sizeof(struct omap3_wdt_priv),
  217. };
  218. #endif /* !CONFIG_IS_ENABLED(WDT) */