mcffec.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2004
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2007 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <malloc.h>
  12. #include <command.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <miiphy.h>
  16. #include <asm/fec.h>
  17. #include <asm/immap.h>
  18. #include <linux/mii.h>
  19. #undef ET_DEBUG
  20. #undef MII_DEBUG
  21. /* Ethernet Transmit and Receive Buffers */
  22. #define DBUF_LENGTH 1520
  23. #define TX_BUF_CNT 2
  24. #define PKT_MAXBUF_SIZE 1518
  25. #define PKT_MINBUF_SIZE 64
  26. #define PKT_MAXBLR_SIZE 1520
  27. #define LAST_PKTBUFSRX PKTBUFSRX - 1
  28. #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
  29. #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
  30. struct fec_info_s fec_info[] = {
  31. #ifdef CONFIG_SYS_FEC0_IOBASE
  32. {
  33. 0, /* index */
  34. CONFIG_SYS_FEC0_IOBASE, /* io base */
  35. CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
  36. CONFIG_SYS_FEC0_MIIBASE, /* mii base */
  37. -1, /* phy_addr */
  38. 0, /* duplex and speed */
  39. 0, /* phy name */
  40. 0, /* phyname init */
  41. 0, /* RX BD */
  42. 0, /* TX BD */
  43. 0, /* rx Index */
  44. 0, /* tx Index */
  45. 0, /* tx buffer */
  46. 0, /* initialized flag */
  47. (struct fec_info_s *)-1,
  48. },
  49. #endif
  50. #ifdef CONFIG_SYS_FEC1_IOBASE
  51. {
  52. 1, /* index */
  53. CONFIG_SYS_FEC1_IOBASE, /* io base */
  54. CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
  55. CONFIG_SYS_FEC1_MIIBASE, /* mii base */
  56. -1, /* phy_addr */
  57. 0, /* duplex and speed */
  58. 0, /* phy name */
  59. 0, /* phy name init */
  60. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  61. (cbd_t *)DBUF_LENGTH, /* RX BD */
  62. #else
  63. 0, /* RX BD */
  64. #endif
  65. 0, /* TX BD */
  66. 0, /* rx Index */
  67. 0, /* tx Index */
  68. 0, /* tx buffer */
  69. 0, /* initialized flag */
  70. (struct fec_info_s *)-1,
  71. }
  72. #endif
  73. };
  74. int fec_recv(struct eth_device *dev);
  75. int fec_init(struct eth_device *dev, bd_t * bd);
  76. void fec_halt(struct eth_device *dev);
  77. void fec_reset(struct eth_device *dev);
  78. void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
  79. {
  80. if ((dup_spd >> 16) == FULL) {
  81. /* Set maximum frame length */
  82. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
  83. FEC_RCR_PROM | 0x100;
  84. fecp->tcr = FEC_TCR_FDEN;
  85. } else {
  86. /* Half duplex mode */
  87. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
  88. FEC_RCR_MII_MODE | FEC_RCR_DRT;
  89. fecp->tcr &= ~FEC_TCR_FDEN;
  90. }
  91. if ((dup_spd & 0xFFFF) == _100BASET) {
  92. #ifdef CONFIG_MCF5445x
  93. fecp->rcr &= ~0x200; /* disabled 10T base */
  94. #endif
  95. #ifdef MII_DEBUG
  96. printf("100Mbps\n");
  97. #endif
  98. bd->bi_ethspeed = 100;
  99. } else {
  100. #ifdef CONFIG_MCF5445x
  101. fecp->rcr |= 0x200; /* enabled 10T base */
  102. #endif
  103. #ifdef MII_DEBUG
  104. printf("10Mbps\n");
  105. #endif
  106. bd->bi_ethspeed = 10;
  107. }
  108. }
  109. static int fec_send(struct eth_device *dev, void *packet, int length)
  110. {
  111. struct fec_info_s *info = dev->priv;
  112. volatile fec_t *fecp = (fec_t *) (info->iobase);
  113. int j, rc;
  114. u16 phyStatus;
  115. miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
  116. /* section 16.9.23.3
  117. * Wait for ready
  118. */
  119. j = 0;
  120. while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
  121. (j < MCFFEC_TOUT_LOOP)) {
  122. udelay(1);
  123. j++;
  124. }
  125. if (j >= MCFFEC_TOUT_LOOP) {
  126. printf("TX not ready\n");
  127. }
  128. info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
  129. info->txbd[info->txIdx].cbd_datlen = length;
  130. info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
  131. /* Activate transmit Buffer Descriptor polling */
  132. fecp->tdar = 0x01000000; /* Descriptor polling active */
  133. #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
  134. /*
  135. * FEC unable to initial transmit data packet.
  136. * A nop will ensure the descriptor polling active completed.
  137. * CF Internal RAM has shorter cycle access than DRAM. If use
  138. * DRAM as Buffer descriptor and data, a nop is a must.
  139. * Affect only V2 and V3.
  140. */
  141. __asm__ ("nop");
  142. #endif
  143. #ifdef CONFIG_SYS_UNIFY_CACHE
  144. icache_invalid();
  145. #endif
  146. j = 0;
  147. while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
  148. (j < MCFFEC_TOUT_LOOP)) {
  149. udelay(1);
  150. j++;
  151. }
  152. if (j >= MCFFEC_TOUT_LOOP) {
  153. printf("TX timeout\n");
  154. }
  155. #ifdef ET_DEBUG
  156. printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
  157. __FILE__, __LINE__, __FUNCTION__, j,
  158. info->txbd[info->txIdx].cbd_sc,
  159. (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
  160. #endif
  161. /* return only status bits */
  162. rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
  163. info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
  164. return rc;
  165. }
  166. int fec_recv(struct eth_device *dev)
  167. {
  168. struct fec_info_s *info = dev->priv;
  169. volatile fec_t *fecp = (fec_t *) (info->iobase);
  170. int length;
  171. for (;;) {
  172. #ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
  173. #endif
  174. #ifdef CONFIG_SYS_UNIFY_CACHE
  175. icache_invalid();
  176. #endif
  177. /* section 16.9.23.2 */
  178. if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  179. length = -1;
  180. break; /* nothing received - leave for() loop */
  181. }
  182. length = info->rxbd[info->rxIdx].cbd_datlen;
  183. if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
  184. printf("%s[%d] err: %x\n",
  185. __FUNCTION__, __LINE__,
  186. info->rxbd[info->rxIdx].cbd_sc);
  187. #ifdef ET_DEBUG
  188. printf("%s[%d] err: %x\n",
  189. __FUNCTION__, __LINE__,
  190. info->rxbd[info->rxIdx].cbd_sc);
  191. #endif
  192. } else {
  193. length -= 4;
  194. /* Pass the packet up to the protocol layers. */
  195. net_process_received_packet(net_rx_packets[info->rxIdx],
  196. length);
  197. fecp->eir |= FEC_EIR_RXF;
  198. }
  199. /* Give the buffer back to the FEC. */
  200. info->rxbd[info->rxIdx].cbd_datlen = 0;
  201. /* wrap around buffer index when necessary */
  202. if (info->rxIdx == LAST_PKTBUFSRX) {
  203. info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
  204. info->rxIdx = 0;
  205. } else {
  206. info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  207. info->rxIdx++;
  208. }
  209. /* Try to fill Buffer Descriptors */
  210. fecp->rdar = 0x01000000; /* Descriptor polling active */
  211. }
  212. return length;
  213. }
  214. #ifdef ET_DEBUG
  215. void dbgFecRegs(struct eth_device *dev)
  216. {
  217. struct fec_info_s *info = dev->priv;
  218. volatile fec_t *fecp = (fec_t *) (info->iobase);
  219. printf("=====\n");
  220. printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
  221. printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
  222. printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
  223. printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
  224. printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
  225. printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
  226. printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
  227. printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
  228. printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
  229. printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
  230. printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
  231. printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
  232. printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
  233. printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
  234. printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
  235. printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
  236. printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
  237. printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
  238. printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
  239. printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
  240. printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
  241. printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
  242. printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
  243. printf("\n");
  244. printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
  245. fecp->rmon_t_drop);
  246. printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
  247. fecp->rmon_t_packets);
  248. printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
  249. fecp->rmon_t_bc_pkt);
  250. printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
  251. fecp->rmon_t_mc_pkt);
  252. printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
  253. fecp->rmon_t_crc_align);
  254. printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
  255. fecp->rmon_t_undersize);
  256. printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
  257. fecp->rmon_t_oversize);
  258. printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
  259. fecp->rmon_t_frag);
  260. printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
  261. fecp->rmon_t_jab);
  262. printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
  263. fecp->rmon_t_col);
  264. printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
  265. fecp->rmon_t_p64);
  266. printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
  267. fecp->rmon_t_p65to127);
  268. printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
  269. fecp->rmon_t_p128to255);
  270. printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
  271. fecp->rmon_t_p256to511);
  272. printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
  273. fecp->rmon_t_p512to1023);
  274. printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
  275. fecp->rmon_t_p1024to2047);
  276. printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
  277. fecp->rmon_t_p_gte2048);
  278. printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
  279. fecp->rmon_t_octets);
  280. printf("\n");
  281. printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
  282. fecp->ieee_t_drop);
  283. printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
  284. fecp->ieee_t_frame_ok);
  285. printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
  286. fecp->ieee_t_1col);
  287. printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
  288. fecp->ieee_t_mcol);
  289. printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
  290. fecp->ieee_t_def);
  291. printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
  292. fecp->ieee_t_lcol);
  293. printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
  294. fecp->ieee_t_excol);
  295. printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
  296. fecp->ieee_t_macerr);
  297. printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
  298. fecp->ieee_t_cserr);
  299. printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
  300. fecp->ieee_t_sqe);
  301. printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
  302. fecp->ieee_t_fdxfc);
  303. printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
  304. fecp->ieee_t_octets_ok);
  305. printf("\n");
  306. printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
  307. fecp->rmon_r_drop);
  308. printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
  309. fecp->rmon_r_packets);
  310. printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
  311. fecp->rmon_r_bc_pkt);
  312. printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
  313. fecp->rmon_r_mc_pkt);
  314. printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
  315. fecp->rmon_r_crc_align);
  316. printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
  317. fecp->rmon_r_undersize);
  318. printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
  319. fecp->rmon_r_oversize);
  320. printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
  321. fecp->rmon_r_frag);
  322. printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
  323. fecp->rmon_r_jab);
  324. printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
  325. fecp->rmon_r_p64);
  326. printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
  327. fecp->rmon_r_p65to127);
  328. printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
  329. fecp->rmon_r_p128to255);
  330. printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
  331. fecp->rmon_r_p256to511);
  332. printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
  333. fecp->rmon_r_p512to1023);
  334. printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
  335. fecp->rmon_r_p1024to2047);
  336. printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
  337. fecp->rmon_r_p_gte2048);
  338. printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
  339. fecp->rmon_r_octets);
  340. printf("\n");
  341. printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
  342. fecp->ieee_r_drop);
  343. printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
  344. fecp->ieee_r_frame_ok);
  345. printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
  346. fecp->ieee_r_crc);
  347. printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
  348. fecp->ieee_r_align);
  349. printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
  350. fecp->ieee_r_macerr);
  351. printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
  352. fecp->ieee_r_fdxfc);
  353. printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
  354. fecp->ieee_r_octets_ok);
  355. printf("\n\n\n");
  356. }
  357. #endif
  358. int fec_init(struct eth_device *dev, bd_t * bd)
  359. {
  360. struct fec_info_s *info = dev->priv;
  361. volatile fec_t *fecp = (fec_t *) (info->iobase);
  362. int i;
  363. uchar ea[6];
  364. fecpin_setclear(dev, 1);
  365. fec_reset(dev);
  366. #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
  367. defined (CONFIG_SYS_DISCOVER_PHY)
  368. mii_init();
  369. setFecDuplexSpeed(fecp, bd, info->dup_spd);
  370. #else
  371. #ifndef CONFIG_SYS_DISCOVER_PHY
  372. setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
  373. #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
  374. #endif /* CONFIG_CMD_MII || CONFIG_MII */
  375. /* We use strictly polling mode only */
  376. fecp->eimr = 0;
  377. /* Clear any pending interrupt */
  378. fecp->eir = 0xffffffff;
  379. /* Set station address */
  380. if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
  381. #ifdef CONFIG_SYS_FEC1_IOBASE
  382. volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
  383. eth_env_get_enetaddr("eth1addr", ea);
  384. fecp1->palr =
  385. (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  386. fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
  387. #endif
  388. eth_env_get_enetaddr("ethaddr", ea);
  389. fecp->palr =
  390. (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  391. fecp->paur = (ea[4] << 24) | (ea[5] << 16);
  392. } else {
  393. #ifdef CONFIG_SYS_FEC0_IOBASE
  394. volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
  395. eth_env_get_enetaddr("ethaddr", ea);
  396. fecp0->palr =
  397. (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  398. fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
  399. #endif
  400. #ifdef CONFIG_SYS_FEC1_IOBASE
  401. eth_env_get_enetaddr("eth1addr", ea);
  402. fecp->palr =
  403. (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  404. fecp->paur = (ea[4] << 24) | (ea[5] << 16);
  405. #endif
  406. }
  407. /* Clear unicast address hash table */
  408. fecp->iaur = 0;
  409. fecp->ialr = 0;
  410. /* Clear multicast address hash table */
  411. fecp->gaur = 0;
  412. fecp->galr = 0;
  413. /* Set maximum receive buffer size. */
  414. fecp->emrbr = PKT_MAXBLR_SIZE;
  415. /*
  416. * Setup Buffers and Buffer Descriptors
  417. */
  418. info->rxIdx = 0;
  419. info->txIdx = 0;
  420. /*
  421. * Setup Receiver Buffer Descriptors (13.14.24.18)
  422. * Settings:
  423. * Empty, Wrap
  424. */
  425. for (i = 0; i < PKTBUFSRX; i++) {
  426. info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  427. info->rxbd[i].cbd_datlen = 0; /* Reset */
  428. info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  429. }
  430. info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  431. /*
  432. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  433. * Settings:
  434. * Last, Tx CRC
  435. */
  436. for (i = 0; i < TX_BUF_CNT; i++) {
  437. info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
  438. info->txbd[i].cbd_datlen = 0; /* Reset */
  439. info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
  440. }
  441. info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  442. /* Set receive and transmit descriptor base */
  443. fecp->erdsr = (unsigned int)(&info->rxbd[0]);
  444. fecp->etdsr = (unsigned int)(&info->txbd[0]);
  445. /* Now enable the transmit and receive processing */
  446. fecp->ecr |= FEC_ECR_ETHER_EN;
  447. /* And last, try to fill Rx Buffer Descriptors */
  448. fecp->rdar = 0x01000000; /* Descriptor polling active */
  449. return 1;
  450. }
  451. void fec_reset(struct eth_device *dev)
  452. {
  453. struct fec_info_s *info = dev->priv;
  454. volatile fec_t *fecp = (fec_t *) (info->iobase);
  455. int i;
  456. fecp->ecr = FEC_ECR_RESET;
  457. for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  458. udelay(1);
  459. }
  460. if (i == FEC_RESET_DELAY) {
  461. printf("FEC_RESET_DELAY timeout\n");
  462. }
  463. }
  464. void fec_halt(struct eth_device *dev)
  465. {
  466. struct fec_info_s *info = dev->priv;
  467. fec_reset(dev);
  468. fecpin_setclear(dev, 0);
  469. info->rxIdx = info->txIdx = 0;
  470. memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
  471. memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
  472. memset(info->txbuf, 0, DBUF_LENGTH);
  473. }
  474. int mcffec_initialize(bd_t * bis)
  475. {
  476. struct eth_device *dev;
  477. int i;
  478. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  479. u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
  480. #endif
  481. for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
  482. dev =
  483. (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
  484. sizeof *dev);
  485. if (dev == NULL)
  486. hang();
  487. memset(dev, 0, sizeof(*dev));
  488. sprintf(dev->name, "FEC%d", fec_info[i].index);
  489. dev->priv = &fec_info[i];
  490. dev->init = fec_init;
  491. dev->halt = fec_halt;
  492. dev->send = fec_send;
  493. dev->recv = fec_recv;
  494. /* setup Receive and Transmit buffer descriptor */
  495. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  496. fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
  497. tmp = (u32)fec_info[i].rxbd;
  498. fec_info[i].txbd =
  499. (cbd_t *)((u32)fec_info[i].txbd + tmp +
  500. (PKTBUFSRX * sizeof(cbd_t)));
  501. tmp = (u32)fec_info[i].txbd;
  502. fec_info[i].txbuf =
  503. (char *)((u32)fec_info[i].txbuf + tmp +
  504. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  505. tmp = (u32)fec_info[i].txbuf;
  506. #else
  507. fec_info[i].rxbd =
  508. (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
  509. (PKTBUFSRX * sizeof(cbd_t)));
  510. fec_info[i].txbd =
  511. (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
  512. (TX_BUF_CNT * sizeof(cbd_t)));
  513. fec_info[i].txbuf =
  514. (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
  515. #endif
  516. #ifdef ET_DEBUG
  517. printf("rxbd %x txbd %x\n",
  518. (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
  519. #endif
  520. fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
  521. eth_register(dev);
  522. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  523. int retval;
  524. struct mii_dev *mdiodev = mdio_alloc();
  525. if (!mdiodev)
  526. return -ENOMEM;
  527. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  528. mdiodev->read = mcffec_miiphy_read;
  529. mdiodev->write = mcffec_miiphy_write;
  530. retval = mdio_register(mdiodev);
  531. if (retval < 0)
  532. return retval;
  533. #endif
  534. if (i > 0)
  535. fec_info[i - 1].next = &fec_info[i];
  536. }
  537. fec_info[i - 1].next = &fec_info[0];
  538. /* default speed */
  539. bis->bi_ethspeed = 10;
  540. return 0;
  541. }