lx2160a.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <phy.h>
  7. #include <fsl-mc/ldpaa_wriop.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/arch/soc.h>
  11. #include <linux/mii.h>
  12. u32 dpmac_to_devdisr[] = {
  13. [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
  14. [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
  15. [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
  16. [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
  17. [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
  18. [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
  19. [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
  20. [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
  21. [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
  22. [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
  23. [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
  24. [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
  25. [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
  26. [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
  27. [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
  28. [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
  29. [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
  30. [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
  31. };
  32. static int is_device_disabled(int dpmac_id)
  33. {
  34. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  35. u32 devdisr2 = in_le32(&gur->devdisr2);
  36. return dpmac_to_devdisr[dpmac_id] & devdisr2;
  37. }
  38. void wriop_dpmac_disable(int dpmac_id)
  39. {
  40. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  41. setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  42. }
  43. void wriop_dpmac_enable(int dpmac_id)
  44. {
  45. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  46. clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  47. }
  48. phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
  49. {
  50. enum srds_prtcl;
  51. if (is_device_disabled(dpmac_id + 1))
  52. return PHY_INTERFACE_MODE_NONE;
  53. if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
  54. return PHY_INTERFACE_MODE_SGMII;
  55. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
  56. return PHY_INTERFACE_MODE_XGMII;
  57. if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
  58. return PHY_INTERFACE_MODE_25G_AUI;
  59. if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
  60. return PHY_INTERFACE_MODE_XLAUI;
  61. if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
  62. return PHY_INTERFACE_MODE_CAUI2;
  63. if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
  64. return PHY_INTERFACE_MODE_CAUI4;
  65. return PHY_INTERFACE_MODE_NONE;
  66. }
  67. #ifdef CONFIG_SYS_FSL_HAS_RGMII
  68. void fsl_rgmii_init(void)
  69. {
  70. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  71. u32 ec;
  72. #ifdef CONFIG_SYS_FSL_EC1
  73. ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
  74. & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
  75. ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
  76. if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
  77. wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
  78. #endif
  79. #ifdef CONFIG_SYS_FSL_EC2
  80. ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
  81. & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
  82. ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
  83. if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
  84. wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
  85. #endif
  86. }
  87. #endif