ls1088a.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #include <common.h>
  6. #include <phy.h>
  7. #include <fsl-mc/ldpaa_wriop.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/arch/soc.h>
  11. #include <linux/mii.h>
  12. u32 dpmac_to_devdisr[] = {
  13. [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
  14. [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
  15. [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
  16. [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
  17. [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
  18. [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
  19. [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
  20. [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
  21. [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
  22. [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
  23. };
  24. static int is_device_disabled(int dpmac_id)
  25. {
  26. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  27. u32 devdisr2 = in_le32(&gur->devdisr2);
  28. return dpmac_to_devdisr[dpmac_id] & devdisr2;
  29. }
  30. void wriop_dpmac_disable(int dpmac_id)
  31. {
  32. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  33. setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  34. }
  35. void wriop_dpmac_enable(int dpmac_id)
  36. {
  37. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  38. clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
  39. }
  40. phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
  41. {
  42. enum srds_prtcl;
  43. if (is_device_disabled(dpmac_id + 1))
  44. return PHY_INTERFACE_MODE_NONE;
  45. switch (lane_prtcl) {
  46. case SGMII1:
  47. case SGMII2:
  48. case SGMII3:
  49. case SGMII7:
  50. return PHY_INTERFACE_MODE_SGMII;
  51. }
  52. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
  53. return PHY_INTERFACE_MODE_XGMII;
  54. if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
  55. return PHY_INTERFACE_MODE_QSGMII;
  56. return PHY_INTERFACE_MODE_NONE;
  57. }
  58. void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  59. {
  60. switch (lane_prtcl) {
  61. case QSGMII_A:
  62. wriop_init_dpmac(sd, 3, (int)lane_prtcl);
  63. wriop_init_dpmac(sd, 4, (int)lane_prtcl);
  64. wriop_init_dpmac(sd, 5, (int)lane_prtcl);
  65. wriop_init_dpmac(sd, 6, (int)lane_prtcl);
  66. break;
  67. case QSGMII_B:
  68. wriop_init_dpmac(sd, 7, (int)lane_prtcl);
  69. wriop_init_dpmac(sd, 8, (int)lane_prtcl);
  70. wriop_init_dpmac(sd, 9, (int)lane_prtcl);
  71. wriop_init_dpmac(sd, 10, (int)lane_prtcl);
  72. break;
  73. }
  74. }
  75. #ifdef CONFIG_SYS_FSL_HAS_RGMII
  76. void fsl_rgmii_init(void)
  77. {
  78. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  79. u32 ec;
  80. #ifdef CONFIG_SYS_FSL_EC1
  81. ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
  82. & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
  83. ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
  84. if (!ec)
  85. wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
  86. #endif
  87. #ifdef CONFIG_SYS_FSL_EC2
  88. ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
  89. & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
  90. ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
  91. if (!ec)
  92. wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
  93. #endif
  94. }
  95. #endif