zynq_nand.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq NAND Flash Controller Driver
  6. * This driver is based on plat_nand.c and mxc_nand.c drivers
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <asm/io.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #include <nand.h>
  15. #include <linux/ioport.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/rawnand.h>
  18. #include <linux/mtd/partitions.h>
  19. #include <linux/mtd/nand_ecc.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <dm.h>
  23. /* The NAND flash driver defines */
  24. #define ZYNQ_NAND_CMD_PHASE 1
  25. #define ZYNQ_NAND_DATA_PHASE 2
  26. #define ZYNQ_NAND_ECC_SIZE 512
  27. #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
  28. #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
  29. #define ZYNQ_NAND_ECC_STATUS (1 << 6)
  30. #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
  31. #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
  32. #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
  33. #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
  34. /* Flash memory controller operating parameters */
  35. #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
  36. (0x1 << 4) | /* Clear interrupt */ \
  37. (0x1 << 6)) /* Disable ECC interrupt */
  38. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  39. /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  40. #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
  41. (0x2 << 17) | /* t_ar from nand_cycles */ \
  42. (0x1 << 14) | /* t_clr from nand_cycles */ \
  43. (0x3 << 11) | /* t_wp from nand_cycles */ \
  44. (0x2 << 8) | /* t_rea from nand_cycles */ \
  45. (0x5 << 4) | /* t_wc from nand_cycles */ \
  46. (0x5 << 0)) /* t_rc from nand_cycles */
  47. #endif
  48. #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
  49. (0x2 << 21)) /* UpdateRegs operation */
  50. #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
  51. (0x1 << 4) | /* ECC read at end of page */ \
  52. (0x0 << 5)) /* No Jumping */
  53. #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
  54. (0x00 << 8) | /* Read command */ \
  55. (0x30 << 16) | /* Read End command */ \
  56. (0x1 << 24)) /* Read End command calid */
  57. #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
  58. (0x05 << 8) | /* Read col change cmd */ \
  59. (0xE0 << 16) | /* Read col change end cmd */ \
  60. (0x1 << 24)) /* Read col change
  61. end cmd valid */
  62. /* AXI Address definitions */
  63. #define START_CMD_SHIFT 3
  64. #define END_CMD_SHIFT 11
  65. #define END_CMD_VALID_SHIFT 20
  66. #define ADDR_CYCLES_SHIFT 21
  67. #define CLEAR_CS_SHIFT 21
  68. #define ECC_LAST_SHIFT 10
  69. #define COMMAND_PHASE (0 << 19)
  70. #define DATA_PHASE (1 << 19)
  71. #define ONDIE_ECC_FEATURE_ADDR 0x90
  72. #define ONDIE_ECC_FEATURE_ENABLE 0x08
  73. #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
  74. #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
  75. /* ECC block registers bit position and bit mask */
  76. #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
  77. #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
  78. #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F
  79. #define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0
  80. #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13
  81. #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8
  82. enum zynq_nand_bus_width {
  83. NAND_BW_UNKNOWN = -1,
  84. NAND_BW_8BIT,
  85. NAND_BW_16BIT,
  86. };
  87. #ifndef NAND_CMD_LOCK_TIGHT
  88. #define NAND_CMD_LOCK_TIGHT 0x2c
  89. #endif
  90. #ifndef NAND_CMD_LOCK_STATUS
  91. #define NAND_CMD_LOCK_STATUS 0x7a
  92. #endif
  93. /* SMC register set */
  94. struct zynq_nand_smc_regs {
  95. u32 csr; /* 0x00 */
  96. u32 reserved0[2];
  97. u32 cfr; /* 0x0C */
  98. u32 dcr; /* 0x10 */
  99. u32 scr; /* 0x14 */
  100. u32 sor; /* 0x18 */
  101. u32 reserved1[249];
  102. u32 esr; /* 0x400 */
  103. u32 emcr; /* 0x404 */
  104. u32 emcmd1r; /* 0x408 */
  105. u32 emcmd2r; /* 0x40C */
  106. u32 reserved2[2];
  107. u32 eval0r; /* 0x418 */
  108. };
  109. /*
  110. * struct nand_config - Defines the NAND flash driver instance
  111. * @parts: Pointer to the mtd_partition structure
  112. * @nand_base: Virtual address of the NAND flash device
  113. * @end_cmd_pending: End command is pending
  114. * @end_cmd: End command
  115. */
  116. struct nand_config {
  117. void __iomem *nand_base;
  118. u8 end_cmd_pending;
  119. u8 end_cmd;
  120. };
  121. struct nand_drv {
  122. struct zynq_nand_smc_regs *reg;
  123. struct nand_config config;
  124. };
  125. struct zynq_nand_info {
  126. struct udevice *dev;
  127. struct nand_drv nand_ctrl;
  128. struct nand_chip nand_chip;
  129. };
  130. /*
  131. * struct zynq_nand_command_format - Defines NAND flash command format
  132. * @start_cmd: First cycle command (Start command)
  133. * @end_cmd: Second cycle command (Last command)
  134. * @addr_cycles: Number of address cycles required to send the address
  135. * @end_cmd_valid: The second cycle command is valid for cmd or data phase
  136. */
  137. struct zynq_nand_command_format {
  138. u8 start_cmd;
  139. u8 end_cmd;
  140. u8 addr_cycles;
  141. u8 end_cmd_valid;
  142. };
  143. /* The NAND flash operations command format */
  144. static const struct zynq_nand_command_format zynq_nand_commands[] = {
  145. {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
  146. {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
  147. {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
  148. {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
  149. {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
  150. {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
  151. {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
  152. {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
  153. {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
  154. {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
  155. {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
  156. {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
  157. {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
  158. {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
  159. {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
  160. {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
  161. {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
  162. /* Add all the flash commands supported by the flash device */
  163. };
  164. /* Define default oob placement schemes for large and small page devices */
  165. static struct nand_ecclayout nand_oob_16 = {
  166. .eccbytes = 3,
  167. .eccpos = {0, 1, 2},
  168. .oobfree = {
  169. { .offset = 8, .length = 8 }
  170. }
  171. };
  172. static struct nand_ecclayout nand_oob_64 = {
  173. .eccbytes = 12,
  174. .eccpos = {
  175. 52, 53, 54, 55, 56, 57,
  176. 58, 59, 60, 61, 62, 63},
  177. .oobfree = {
  178. { .offset = 2, .length = 50 }
  179. }
  180. };
  181. static struct nand_ecclayout ondie_nand_oob_64 = {
  182. .eccbytes = 32,
  183. .eccpos = {
  184. 8, 9, 10, 11, 12, 13, 14, 15,
  185. 24, 25, 26, 27, 28, 29, 30, 31,
  186. 40, 41, 42, 43, 44, 45, 46, 47,
  187. 56, 57, 58, 59, 60, 61, 62, 63
  188. },
  189. .oobfree = {
  190. { .offset = 4, .length = 4 },
  191. { .offset = 20, .length = 4 },
  192. { .offset = 36, .length = 4 },
  193. { .offset = 52, .length = 4 }
  194. }
  195. };
  196. /* bbt decriptors for chips with on-die ECC and
  197. chips with 64-byte OOB */
  198. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  199. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  200. static struct nand_bbt_descr bbt_main_descr = {
  201. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  202. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  203. .offs = 4,
  204. .len = 4,
  205. .veroffs = 20,
  206. .maxblocks = 4,
  207. .pattern = bbt_pattern
  208. };
  209. static struct nand_bbt_descr bbt_mirror_descr = {
  210. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  211. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  212. .offs = 4,
  213. .len = 4,
  214. .veroffs = 20,
  215. .maxblocks = 4,
  216. .pattern = mirror_pattern
  217. };
  218. /*
  219. * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
  220. *
  221. * returns: status for command completion, -1 for Timeout
  222. */
  223. static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd)
  224. {
  225. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  226. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  227. unsigned long timeout;
  228. u32 status;
  229. /* Wait max 10us */
  230. timeout = 10;
  231. status = readl(&smc->reg->esr);
  232. while (status & ZYNQ_NAND_ECC_BUSY) {
  233. status = readl(&smc->reg->esr);
  234. if (timeout == 0)
  235. return -1;
  236. timeout--;
  237. udelay(1);
  238. }
  239. return status;
  240. }
  241. /*
  242. * zynq_nand_init_nand_flash - Initialize NAND controller
  243. * @option: Device property flags
  244. *
  245. * This function initializes the NAND flash interface on the NAND controller.
  246. *
  247. * returns: 0 on success or error value on failure
  248. */
  249. static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
  250. {
  251. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  252. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  253. u32 status;
  254. /* disable interrupts */
  255. writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
  256. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  257. /* Initialize the NAND interface by setting cycles and operation mode */
  258. writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr);
  259. #endif
  260. if (option & NAND_BUSWIDTH_16)
  261. writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor);
  262. else
  263. writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor);
  264. writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr);
  265. /* Wait till the ECC operation is complete */
  266. status = zynq_nand_waitfor_ecc_completion(mtd);
  267. if (status < 0) {
  268. printf("%s: Timeout\n", __func__);
  269. return status;
  270. }
  271. /* Set the command1 and command2 register */
  272. writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r);
  273. writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r);
  274. return 0;
  275. }
  276. /*
  277. * zynq_nand_calculate_hwecc - Calculate Hardware ECC
  278. * @mtd: Pointer to the mtd_info structure
  279. * @data: Pointer to the page data
  280. * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
  281. *
  282. * This function retrieves the Hardware ECC data from the controller and returns
  283. * ECC data back to the MTD subsystem.
  284. *
  285. * returns: 0 on success or error value on failure
  286. */
  287. static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
  288. u8 *ecc_code)
  289. {
  290. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  291. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  292. u32 ecc_value = 0;
  293. u8 ecc_reg, ecc_byte;
  294. u32 ecc_status;
  295. /* Wait till the ECC operation is complete */
  296. ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
  297. if (ecc_status < 0) {
  298. printf("%s: Timeout\n", __func__);
  299. return ecc_status;
  300. }
  301. for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
  302. /* Read ECC value for each block */
  303. ecc_value = readl(&smc->reg->eval0r + ecc_reg);
  304. /* Get the ecc status from ecc read value */
  305. ecc_status = (ecc_value >> 24) & 0xFF;
  306. /* ECC value valid */
  307. if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
  308. for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
  309. /* Copy ECC bytes to MTD buffer */
  310. *ecc_code = ecc_value & 0xFF;
  311. ecc_value = ecc_value >> 8;
  312. ecc_code++;
  313. }
  314. } else {
  315. debug("%s: ecc status failed\n", __func__);
  316. }
  317. }
  318. return 0;
  319. }
  320. /*
  321. * onehot - onehot function
  322. * @value: value to check for onehot
  323. *
  324. * This function checks whether a value is onehot or not.
  325. * onehot is if and only if one bit is set.
  326. *
  327. * FIXME: Try to move this in common.h
  328. */
  329. static bool onehot(unsigned short value)
  330. {
  331. bool onehot;
  332. onehot = value && !(value & (value - 1));
  333. return onehot;
  334. }
  335. /*
  336. * zynq_nand_correct_data - ECC correction function
  337. * @mtd: Pointer to the mtd_info structure
  338. * @buf: Pointer to the page data
  339. * @read_ecc: Pointer to the ECC value read from spare data area
  340. * @calc_ecc: Pointer to the calculated ECC value
  341. *
  342. * This function corrects the ECC single bit errors & detects 2-bit errors.
  343. *
  344. * returns: 0 if no ECC errors found
  345. * 1 if single bit error found and corrected.
  346. * -1 if multiple ECC errors found.
  347. */
  348. static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
  349. unsigned char *read_ecc, unsigned char *calc_ecc)
  350. {
  351. unsigned char bit_addr;
  352. unsigned int byte_addr;
  353. unsigned short ecc_odd, ecc_even;
  354. unsigned short read_ecc_lower, read_ecc_upper;
  355. unsigned short calc_ecc_lower, calc_ecc_upper;
  356. read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
  357. read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
  358. calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
  359. calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
  360. ecc_odd = read_ecc_lower ^ calc_ecc_lower;
  361. ecc_even = read_ecc_upper ^ calc_ecc_upper;
  362. if ((ecc_odd == 0) && (ecc_even == 0))
  363. return 0; /* no error */
  364. if (ecc_odd == (~ecc_even & 0xfff)) {
  365. /* bits [11:3] of error code is byte offset */
  366. byte_addr = (ecc_odd >> 3) & 0x1ff;
  367. /* bits [2:0] of error code is bit offset */
  368. bit_addr = ecc_odd & 0x7;
  369. /* Toggling error bit */
  370. buf[byte_addr] ^= (1 << bit_addr);
  371. return 1;
  372. }
  373. if (onehot(ecc_odd | ecc_even))
  374. return 1; /* one error in parity */
  375. return -1; /* Uncorrectable error */
  376. }
  377. /*
  378. * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
  379. * @mtd: mtd info structure
  380. * @chip: nand chip info structure
  381. * @page: page number to read
  382. * @sndcmd: flag whether to issue read command or not
  383. */
  384. static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  385. int page)
  386. {
  387. unsigned long data_phase_addr = 0;
  388. int data_width = 4;
  389. u8 *p;
  390. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  391. p = chip->oob_poi;
  392. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  393. p += mtd->oobsize - data_width;
  394. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  395. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  396. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  397. chip->read_buf(mtd, p, data_width);
  398. return 0;
  399. }
  400. /*
  401. * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
  402. * @mtd: mtd info structure
  403. * @chip: nand chip info structure
  404. * @page: page number to write
  405. */
  406. static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  407. int page)
  408. {
  409. int status = 0, data_width = 4;
  410. const u8 *buf = chip->oob_poi;
  411. unsigned long data_phase_addr = 0;
  412. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  413. chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
  414. buf += mtd->oobsize - data_width;
  415. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  416. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  417. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  418. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  419. chip->write_buf(mtd, buf, data_width);
  420. /* Send command to program the OOB data */
  421. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  422. status = chip->waitfunc(mtd, chip);
  423. return status & NAND_STATUS_FAIL ? -EIO : 0;
  424. }
  425. /*
  426. * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
  427. * @mtd: mtd info structure
  428. * @chip: nand chip info structure
  429. * @buf: buffer to store read data
  430. * @oob_required: must write chip->oob_poi to OOB
  431. * @page: page number to read
  432. */
  433. static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  434. u8 *buf, int oob_required, int page)
  435. {
  436. unsigned long data_width = 4;
  437. unsigned long data_phase_addr = 0;
  438. u8 *p;
  439. chip->read_buf(mtd, buf, mtd->writesize);
  440. p = chip->oob_poi;
  441. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  442. p += (mtd->oobsize - data_width);
  443. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  444. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  445. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  446. chip->read_buf(mtd, p, data_width);
  447. return 0;
  448. }
  449. static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
  450. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  451. {
  452. chip->read_buf(mtd, buf, mtd->writesize);
  453. return 0;
  454. }
  455. static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
  456. struct nand_chip *chip, u32 data_offs,
  457. u32 readlen, u8 *buf, int page)
  458. {
  459. if (data_offs != 0) {
  460. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
  461. buf += data_offs;
  462. }
  463. chip->read_buf(mtd, buf, readlen);
  464. return 0;
  465. }
  466. /*
  467. * zynq_nand_write_page_raw - [Intern] raw page write function
  468. * @mtd: mtd info structure
  469. * @chip: nand chip info structure
  470. * @buf: data buffer
  471. * @oob_required: must write chip->oob_poi to OOB
  472. */
  473. static int zynq_nand_write_page_raw(struct mtd_info *mtd,
  474. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  475. {
  476. unsigned long data_width = 4;
  477. unsigned long data_phase_addr = 0;
  478. u8 *p;
  479. chip->write_buf(mtd, buf, mtd->writesize);
  480. p = chip->oob_poi;
  481. chip->write_buf(mtd, p, (mtd->oobsize - data_width));
  482. p += (mtd->oobsize - data_width);
  483. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  484. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  485. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  486. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  487. chip->write_buf(mtd, p, data_width);
  488. return 0;
  489. }
  490. /*
  491. * nand_write_page_hwecc - Hardware ECC based page write function
  492. * @mtd: Pointer to the mtd info structure
  493. * @chip: Pointer to the NAND chip info structure
  494. * @buf: Pointer to the data buffer
  495. * @oob_required: must write chip->oob_poi to OOB
  496. *
  497. * This functions writes data and hardware generated ECC values in to the page.
  498. */
  499. static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
  500. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  501. {
  502. int i, eccsteps, eccsize = chip->ecc.size;
  503. u8 *ecc_calc = chip->buffers->ecccalc;
  504. const u8 *p = buf;
  505. u32 *eccpos = chip->ecc.layout->eccpos;
  506. unsigned long data_phase_addr = 0;
  507. unsigned long data_width = 4;
  508. u8 *oob_ptr;
  509. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  510. chip->write_buf(mtd, p, eccsize);
  511. p += eccsize;
  512. }
  513. chip->write_buf(mtd, p, (eccsize - data_width));
  514. p += eccsize - data_width;
  515. /* Set ECC Last bit to 1 */
  516. data_phase_addr = (unsigned long) chip->IO_ADDR_W;
  517. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  518. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  519. chip->write_buf(mtd, p, data_width);
  520. /* Wait for ECC to be calculated and read the error values */
  521. p = buf;
  522. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  523. for (i = 0; i < chip->ecc.total; i++)
  524. chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
  525. /* Clear ECC last bit */
  526. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  527. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  528. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  529. /* Write the spare area with ECC bytes */
  530. oob_ptr = chip->oob_poi;
  531. chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  532. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  533. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  534. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  535. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  536. oob_ptr += (mtd->oobsize - data_width);
  537. chip->write_buf(mtd, oob_ptr, data_width);
  538. return 0;
  539. }
  540. /*
  541. * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
  542. * write function
  543. * @mtd: mtd info structure
  544. * @chip: nand chip info structure
  545. * @buf: data buffer
  546. * @oob_required: must write chip->oob_poi to OOB
  547. */
  548. static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
  549. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  550. {
  551. int i, eccsize = chip->ecc.size;
  552. int eccbytes = chip->ecc.bytes;
  553. int eccsteps = chip->ecc.steps;
  554. u8 *ecc_calc = chip->buffers->ecccalc;
  555. const u8 *p = buf;
  556. u32 *eccpos = chip->ecc.layout->eccpos;
  557. /* Software ecc calculation */
  558. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  559. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  560. for (i = 0; i < chip->ecc.total; i++)
  561. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  562. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  563. }
  564. /*
  565. * nand_read_page_hwecc - Hardware ECC based page read function
  566. * @mtd: Pointer to the mtd info structure
  567. * @chip: Pointer to the NAND chip info structure
  568. * @buf: Pointer to the buffer to store read data
  569. * @oob_required: must write chip->oob_poi to OOB
  570. * @page: page number to read
  571. *
  572. * This functions reads data and checks the data integrity by comparing hardware
  573. * generated ECC values and read ECC values from spare area.
  574. *
  575. * returns: 0 always and updates ECC operation status in to MTD structure
  576. */
  577. static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
  578. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  579. {
  580. int i, stat, eccsteps, eccsize = chip->ecc.size;
  581. int eccbytes = chip->ecc.bytes;
  582. u8 *p = buf;
  583. u8 *ecc_calc = chip->buffers->ecccalc;
  584. u8 *ecc_code = chip->buffers->ecccode;
  585. u32 *eccpos = chip->ecc.layout->eccpos;
  586. unsigned long data_phase_addr = 0;
  587. unsigned long data_width = 4;
  588. u8 *oob_ptr;
  589. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  590. chip->read_buf(mtd, p, eccsize);
  591. p += eccsize;
  592. }
  593. chip->read_buf(mtd, p, (eccsize - data_width));
  594. p += eccsize - data_width;
  595. /* Set ECC Last bit to 1 */
  596. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  597. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  598. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  599. chip->read_buf(mtd, p, data_width);
  600. /* Read the calculated ECC value */
  601. p = buf;
  602. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  603. /* Clear ECC last bit */
  604. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  605. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  606. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  607. /* Read the stored ECC value */
  608. oob_ptr = chip->oob_poi;
  609. chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  610. /* de-assert chip select */
  611. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  612. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  613. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  614. oob_ptr += (mtd->oobsize - data_width);
  615. chip->read_buf(mtd, oob_ptr, data_width);
  616. for (i = 0; i < chip->ecc.total; i++)
  617. ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
  618. eccsteps = chip->ecc.steps;
  619. p = buf;
  620. /* Check ECC error for all blocks and correct if it is correctable */
  621. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  622. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  623. if (stat < 0)
  624. mtd->ecc_stats.failed++;
  625. else
  626. mtd->ecc_stats.corrected += stat;
  627. }
  628. return 0;
  629. }
  630. /*
  631. * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
  632. * read function
  633. * @mtd: mtd info structure
  634. * @chip: nand chip info structure
  635. * @buf: buffer to store read data
  636. * @page: page number to read
  637. */
  638. static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
  639. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  640. {
  641. int i, eccsize = chip->ecc.size;
  642. int eccbytes = chip->ecc.bytes;
  643. int eccsteps = chip->ecc.steps;
  644. u8 *p = buf;
  645. u8 *ecc_calc = chip->buffers->ecccalc;
  646. u8 *ecc_code = chip->buffers->ecccode;
  647. u32 *eccpos = chip->ecc.layout->eccpos;
  648. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  649. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  650. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  651. for (i = 0; i < chip->ecc.total; i++)
  652. ecc_code[i] = chip->oob_poi[eccpos[i]];
  653. eccsteps = chip->ecc.steps;
  654. p = buf;
  655. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  656. int stat;
  657. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  658. if (stat < 0)
  659. mtd->ecc_stats.failed++;
  660. else
  661. mtd->ecc_stats.corrected += stat;
  662. }
  663. return 0;
  664. }
  665. /*
  666. * zynq_nand_select_chip - Select the flash device
  667. * @mtd: Pointer to the mtd_info structure
  668. * @chip: Chip number to be selected
  669. *
  670. * This function is empty as the NAND controller handles chip select line
  671. * internally based on the chip address passed in command and data phase.
  672. */
  673. static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
  674. {
  675. /* Not support multiple chips yet */
  676. }
  677. /*
  678. * zynq_nand_cmd_function - Send command to NAND device
  679. * @mtd: Pointer to the mtd_info structure
  680. * @command: The command to be sent to the flash device
  681. * @column: The column address for this command, -1 if none
  682. * @page_addr: The page address for this command, -1 if none
  683. */
  684. static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  685. int column, int page_addr)
  686. {
  687. struct nand_chip *chip = mtd_to_nand(mtd);
  688. struct nand_drv *smc = nand_get_controller_data(chip);
  689. const struct zynq_nand_command_format *curr_cmd = NULL;
  690. u8 addr_cycles = 0;
  691. struct nand_config *xnand = &smc->config;
  692. void *cmd_addr;
  693. unsigned long cmd_data = 0;
  694. unsigned long cmd_phase_addr = 0;
  695. unsigned long data_phase_addr = 0;
  696. u8 end_cmd = 0;
  697. u8 end_cmd_valid = 0;
  698. u32 index;
  699. if (xnand->end_cmd_pending) {
  700. /* Check for end command if this command request is same as the
  701. * pending command then return
  702. */
  703. if (xnand->end_cmd == command) {
  704. xnand->end_cmd = 0;
  705. xnand->end_cmd_pending = 0;
  706. return;
  707. }
  708. }
  709. /* Emulate NAND_CMD_READOOB for large page device */
  710. if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
  711. (command == NAND_CMD_READOOB)) {
  712. column += mtd->writesize;
  713. command = NAND_CMD_READ0;
  714. }
  715. /* Get the command format */
  716. for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
  717. if (command == zynq_nand_commands[index].start_cmd)
  718. break;
  719. if (index == ARRAY_SIZE(zynq_nand_commands)) {
  720. printf("%s: Unsupported start cmd %02x\n", __func__, command);
  721. return;
  722. }
  723. curr_cmd = &zynq_nand_commands[index];
  724. /* Clear interrupt */
  725. writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr);
  726. /* Get the command phase address */
  727. if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
  728. end_cmd_valid = 1;
  729. if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE)
  730. end_cmd = 0x0;
  731. else
  732. end_cmd = curr_cmd->end_cmd;
  733. if (command == NAND_CMD_READ0 ||
  734. command == NAND_CMD_SEQIN) {
  735. addr_cycles = chip->onfi_params.addr_cycles &
  736. ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
  737. addr_cycles += ((chip->onfi_params.addr_cycles &
  738. ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
  739. } else {
  740. addr_cycles = curr_cmd->addr_cycles;
  741. }
  742. cmd_phase_addr = (unsigned long)xnand->nand_base |
  743. (addr_cycles << ADDR_CYCLES_SHIFT) |
  744. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  745. (COMMAND_PHASE) |
  746. (end_cmd << END_CMD_SHIFT) |
  747. (curr_cmd->start_cmd << START_CMD_SHIFT);
  748. cmd_addr = (void __iomem *)cmd_phase_addr;
  749. /* Get the data phase address */
  750. end_cmd_valid = 0;
  751. data_phase_addr = (unsigned long)xnand->nand_base |
  752. (0x0 << CLEAR_CS_SHIFT) |
  753. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  754. (DATA_PHASE) |
  755. (end_cmd << END_CMD_SHIFT) |
  756. (0x0 << ECC_LAST_SHIFT);
  757. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  758. chip->IO_ADDR_W = chip->IO_ADDR_R;
  759. /* Command phase AXI Read & Write */
  760. if (column != -1 && page_addr != -1) {
  761. /* Adjust columns for 16 bit bus width */
  762. if (chip->options & NAND_BUSWIDTH_16)
  763. column >>= 1;
  764. cmd_data = column;
  765. if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
  766. cmd_data |= page_addr << 16;
  767. /* Another address cycle for devices > 128MiB */
  768. if (chip->chipsize > (128 << 20)) {
  769. writel(cmd_data, cmd_addr);
  770. cmd_data = (page_addr >> 16);
  771. }
  772. } else {
  773. cmd_data |= page_addr << 8;
  774. }
  775. } else if (page_addr != -1) { /* Erase */
  776. cmd_data = page_addr;
  777. } else if (column != -1) { /* Change read/write column, read id etc */
  778. /* Adjust columns for 16 bit bus width */
  779. if ((chip->options & NAND_BUSWIDTH_16) &&
  780. ((command == NAND_CMD_READ0) ||
  781. (command == NAND_CMD_SEQIN) ||
  782. (command == NAND_CMD_RNDOUT) ||
  783. (command == NAND_CMD_RNDIN)))
  784. column >>= 1;
  785. cmd_data = column;
  786. }
  787. writel(cmd_data, cmd_addr);
  788. if (curr_cmd->end_cmd_valid) {
  789. xnand->end_cmd = curr_cmd->end_cmd;
  790. xnand->end_cmd_pending = 1;
  791. }
  792. ndelay(100);
  793. if ((command == NAND_CMD_READ0) ||
  794. (command == NAND_CMD_RESET) ||
  795. (command == NAND_CMD_PARAM) ||
  796. (command == NAND_CMD_GET_FEATURES))
  797. /* wait until command is processed */
  798. nand_wait_ready(mtd);
  799. }
  800. /*
  801. * zynq_nand_read_buf - read chip data into buffer
  802. * @mtd: MTD device structure
  803. * @buf: buffer to store date
  804. * @len: number of bytes to read
  805. */
  806. static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  807. {
  808. struct nand_chip *chip = mtd_to_nand(mtd);
  809. /* Make sure that buf is 32 bit aligned */
  810. if (((unsigned long)buf & 0x3) != 0) {
  811. if (((unsigned long)buf & 0x1) != 0) {
  812. if (len) {
  813. *buf = readb(chip->IO_ADDR_R);
  814. buf += 1;
  815. len--;
  816. }
  817. }
  818. if (((unsigned long)buf & 0x3) != 0) {
  819. if (len >= 2) {
  820. *(u16 *)buf = readw(chip->IO_ADDR_R);
  821. buf += 2;
  822. len -= 2;
  823. }
  824. }
  825. }
  826. /* copy aligned data */
  827. while (len >= 4) {
  828. *(u32 *)buf = readl(chip->IO_ADDR_R);
  829. buf += 4;
  830. len -= 4;
  831. }
  832. /* mop up any remaining bytes */
  833. if (len) {
  834. if (len >= 2) {
  835. *(u16 *)buf = readw(chip->IO_ADDR_R);
  836. buf += 2;
  837. len -= 2;
  838. }
  839. if (len)
  840. *buf = readb(chip->IO_ADDR_R);
  841. }
  842. }
  843. /*
  844. * zynq_nand_write_buf - write buffer to chip
  845. * @mtd: MTD device structure
  846. * @buf: data buffer
  847. * @len: number of bytes to write
  848. */
  849. static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  850. {
  851. struct nand_chip *chip = mtd_to_nand(mtd);
  852. const u32 *nand = chip->IO_ADDR_W;
  853. /* Make sure that buf is 32 bit aligned */
  854. if (((unsigned long)buf & 0x3) != 0) {
  855. if (((unsigned long)buf & 0x1) != 0) {
  856. if (len) {
  857. writeb(*buf, nand);
  858. buf += 1;
  859. len--;
  860. }
  861. }
  862. if (((unsigned long)buf & 0x3) != 0) {
  863. if (len >= 2) {
  864. writew(*(u16 *)buf, nand);
  865. buf += 2;
  866. len -= 2;
  867. }
  868. }
  869. }
  870. /* copy aligned data */
  871. while (len >= 4) {
  872. writel(*(u32 *)buf, nand);
  873. buf += 4;
  874. len -= 4;
  875. }
  876. /* mop up any remaining bytes */
  877. if (len) {
  878. if (len >= 2) {
  879. writew(*(u16 *)buf, nand);
  880. buf += 2;
  881. len -= 2;
  882. }
  883. if (len)
  884. writeb(*buf, nand);
  885. }
  886. }
  887. /*
  888. * zynq_nand_device_ready - Check device ready/busy line
  889. * @mtd: Pointer to the mtd_info structure
  890. *
  891. * returns: 0 on busy or 1 on ready state
  892. */
  893. static int zynq_nand_device_ready(struct mtd_info *mtd)
  894. {
  895. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  896. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  897. u32 csr_val;
  898. csr_val = readl(&smc->reg->csr);
  899. /* Check the raw_int_status1 bit */
  900. if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
  901. /* Clear the interrupt condition */
  902. writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr);
  903. return 1;
  904. }
  905. return 0;
  906. }
  907. static int zynq_nand_check_is_16bit_bw_flash(void)
  908. {
  909. int is_16bit_bw = NAND_BW_UNKNOWN;
  910. int mio_num_8bit = 0, mio_num_16bit = 0;
  911. mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
  912. if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
  913. is_16bit_bw = NAND_BW_8BIT;
  914. mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
  915. if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
  916. mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
  917. is_16bit_bw = NAND_BW_16BIT;
  918. return is_16bit_bw;
  919. }
  920. static int zynq_nand_probe(struct udevice *dev)
  921. {
  922. struct zynq_nand_info *zynq = dev_get_priv(dev);
  923. struct nand_chip *nand_chip = &zynq->nand_chip;
  924. struct nand_drv *smc = &zynq->nand_ctrl;
  925. struct nand_config *xnand = &smc->config;
  926. struct mtd_info *mtd;
  927. struct resource res;
  928. ofnode of_nand;
  929. unsigned long ecc_page_size;
  930. u8 maf_id, dev_id, i;
  931. u8 get_feature[4];
  932. u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
  933. unsigned long ecc_cfg;
  934. int ondie_ecc_enabled = 0;
  935. int is_16bit_bw;
  936. smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
  937. of_nand = dev_read_subnode(dev, "flash@e1000000");
  938. if (!ofnode_valid(of_nand)) {
  939. printf("Failed to find nand node in dt\n");
  940. return -ENODEV;
  941. }
  942. if (!ofnode_is_available(of_nand)) {
  943. debug("Nand node in dt disabled\n");
  944. return dm_scan_fdt_dev(dev);
  945. }
  946. if (ofnode_read_resource(of_nand, 0, &res)) {
  947. printf("Failed to get nand resource\n");
  948. return -ENODEV;
  949. }
  950. xnand->nand_base = (void __iomem *)res.start;
  951. mtd = nand_to_mtd(nand_chip);
  952. nand_set_controller_data(nand_chip, &zynq->nand_ctrl);
  953. /* Set address of NAND IO lines */
  954. nand_chip->IO_ADDR_R = xnand->nand_base;
  955. nand_chip->IO_ADDR_W = xnand->nand_base;
  956. /* Set the driver entry points for MTD */
  957. nand_chip->cmdfunc = zynq_nand_cmd_function;
  958. nand_chip->dev_ready = zynq_nand_device_ready;
  959. nand_chip->select_chip = zynq_nand_select_chip;
  960. /* If we don't set this delay driver sets 20us by default */
  961. nand_chip->chip_delay = 30;
  962. /* Buffer read/write routines */
  963. nand_chip->read_buf = zynq_nand_read_buf;
  964. nand_chip->write_buf = zynq_nand_write_buf;
  965. is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
  966. if (is_16bit_bw == NAND_BW_UNKNOWN) {
  967. printf("%s: Unable detect NAND based on MIO settings\n",
  968. __func__);
  969. return -EINVAL;
  970. }
  971. if (is_16bit_bw == NAND_BW_16BIT)
  972. nand_chip->options = NAND_BUSWIDTH_16;
  973. nand_chip->bbt_options = NAND_BBT_USE_FLASH;
  974. /* Initialize the NAND flash interface on NAND controller */
  975. if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) {
  976. printf("%s: nand flash init failed\n", __func__);
  977. return -EINVAL;
  978. }
  979. /* first scan to find the device and get the page size */
  980. if (nand_scan_ident(mtd, 1, NULL)) {
  981. printf("%s: nand_scan_ident failed\n", __func__);
  982. return -EINVAL;
  983. }
  984. /* Send the command for reading device ID */
  985. nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  986. nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  987. /* Read manufacturer and device IDs */
  988. maf_id = nand_chip->read_byte(mtd);
  989. dev_id = nand_chip->read_byte(mtd);
  990. if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
  991. (dev_id == 0xa1) || (dev_id == 0xb1) ||
  992. (dev_id == 0xaa) || (dev_id == 0xba) ||
  993. (dev_id == 0xda) || (dev_id == 0xca) ||
  994. (dev_id == 0xac) || (dev_id == 0xbc) ||
  995. (dev_id == 0xdc) || (dev_id == 0xcc) ||
  996. (dev_id == 0xa3) || (dev_id == 0xb3) ||
  997. (dev_id == 0xd3) || (dev_id == 0xc3))) {
  998. nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
  999. ONDIE_ECC_FEATURE_ADDR, -1);
  1000. for (i = 0; i < 4; i++)
  1001. writeb(set_feature[i], nand_chip->IO_ADDR_W);
  1002. /* Wait for 1us after writing data with SET_FEATURES command */
  1003. ndelay(1000);
  1004. nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
  1005. ONDIE_ECC_FEATURE_ADDR, -1);
  1006. nand_chip->read_buf(mtd, get_feature, 4);
  1007. if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
  1008. debug("%s: OnDie ECC flash\n", __func__);
  1009. ondie_ecc_enabled = 1;
  1010. } else {
  1011. printf("%s: Unable to detect OnDie ECC\n", __func__);
  1012. }
  1013. }
  1014. if (ondie_ecc_enabled) {
  1015. /* Bypass the controller ECC block */
  1016. ecc_cfg = readl(&smc->reg->emcr);
  1017. ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
  1018. writel(ecc_cfg, &smc->reg->emcr);
  1019. /* The software ECC routines won't work
  1020. * with the SMC controller
  1021. */
  1022. nand_chip->ecc.mode = NAND_ECC_HW;
  1023. nand_chip->ecc.strength = 1;
  1024. nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
  1025. nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
  1026. nand_chip->ecc.write_page = zynq_nand_write_page_raw;
  1027. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  1028. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  1029. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  1030. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  1031. nand_chip->ecc.size = mtd->writesize;
  1032. nand_chip->ecc.bytes = 0;
  1033. /* NAND with on-die ECC supports subpage reads */
  1034. nand_chip->options |= NAND_SUBPAGE_READ;
  1035. /* On-Die ECC spare bytes offset 8 is used for ECC codes */
  1036. if (ondie_ecc_enabled) {
  1037. nand_chip->ecc.layout = &ondie_nand_oob_64;
  1038. /* Use the BBT pattern descriptors */
  1039. nand_chip->bbt_td = &bbt_main_descr;
  1040. nand_chip->bbt_md = &bbt_mirror_descr;
  1041. }
  1042. } else {
  1043. /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
  1044. nand_chip->ecc.mode = NAND_ECC_HW;
  1045. nand_chip->ecc.strength = 1;
  1046. nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
  1047. nand_chip->ecc.bytes = 3;
  1048. nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
  1049. nand_chip->ecc.correct = zynq_nand_correct_data;
  1050. nand_chip->ecc.hwctl = NULL;
  1051. nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
  1052. nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
  1053. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  1054. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  1055. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  1056. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  1057. switch (mtd->writesize) {
  1058. case 512:
  1059. ecc_page_size = 0x1;
  1060. /* Set the ECC memory config register */
  1061. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1062. &smc->reg->emcr);
  1063. break;
  1064. case 1024:
  1065. ecc_page_size = 0x2;
  1066. /* Set the ECC memory config register */
  1067. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1068. &smc->reg->emcr);
  1069. break;
  1070. case 2048:
  1071. ecc_page_size = 0x3;
  1072. /* Set the ECC memory config register */
  1073. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1074. &smc->reg->emcr);
  1075. break;
  1076. default:
  1077. nand_chip->ecc.mode = NAND_ECC_SOFT;
  1078. nand_chip->ecc.calculate = nand_calculate_ecc;
  1079. nand_chip->ecc.correct = nand_correct_data;
  1080. nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
  1081. nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
  1082. nand_chip->ecc.size = 256;
  1083. break;
  1084. }
  1085. if (mtd->oobsize == 16)
  1086. nand_chip->ecc.layout = &nand_oob_16;
  1087. else if (mtd->oobsize == 64)
  1088. nand_chip->ecc.layout = &nand_oob_64;
  1089. else
  1090. printf("%s: No oob layout found\n", __func__);
  1091. }
  1092. /* Second phase scan */
  1093. if (nand_scan_tail(mtd)) {
  1094. printf("%s: nand_scan_tail failed\n", __func__);
  1095. return -EINVAL;
  1096. }
  1097. if (nand_register(0, mtd))
  1098. return -EINVAL;
  1099. return 0;
  1100. }
  1101. static const struct udevice_id zynq_nand_dt_ids[] = {
  1102. {.compatible = "arm,pl353-smc-r2p1",},
  1103. { /* sentinel */ }
  1104. };
  1105. U_BOOT_DRIVER(zynq_nand) = {
  1106. .name = "zynq_nand",
  1107. .id = UCLASS_MTD,
  1108. .of_match = zynq_nand_dt_ids,
  1109. .probe = zynq_nand_probe,
  1110. .priv_auto_alloc_size = sizeof(struct zynq_nand_info),
  1111. };
  1112. void board_nand_init(void)
  1113. {
  1114. struct udevice *dev;
  1115. int ret;
  1116. ret = uclass_get_device_by_driver(UCLASS_MTD,
  1117. DM_GET_DRIVER(zynq_nand), &dev);
  1118. if (ret && ret != -ENODEV)
  1119. pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
  1120. }