arasan_nfc.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Arasan NAND Flash Controller Driver
  4. *
  5. * Copyright (C) 2014 - 2015 Xilinx, Inc.
  6. */
  7. #include <common.h>
  8. #include <malloc.h>
  9. #include <asm/io.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/rawnand.h>
  14. #include <linux/mtd/partitions.h>
  15. #include <linux/mtd/nand_ecc.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <dm.h>
  19. #include <nand.h>
  20. struct nand_config {
  21. u32 page;
  22. bool on_die_ecc_enabled;
  23. };
  24. struct nand_drv {
  25. struct nand_regs *reg;
  26. struct nand_config config;
  27. };
  28. struct arasan_nand_info {
  29. struct udevice *dev;
  30. struct nand_drv nand_ctrl;
  31. struct nand_chip nand_chip;
  32. };
  33. struct nand_regs {
  34. u32 pkt_reg;
  35. u32 memadr_reg1;
  36. u32 memadr_reg2;
  37. u32 cmd_reg;
  38. u32 pgm_reg;
  39. u32 intsts_enr;
  40. u32 intsig_enr;
  41. u32 intsts_reg;
  42. u32 rdy_busy;
  43. u32 cms_sysadr_reg;
  44. u32 flash_sts_reg;
  45. u32 tmg_reg;
  46. u32 buf_dataport;
  47. u32 ecc_reg;
  48. u32 ecc_errcnt_reg;
  49. u32 ecc_sprcmd_reg;
  50. u32 errcnt_1bitreg;
  51. u32 errcnt_2bitreg;
  52. u32 errcnt_3bitreg;
  53. u32 errcnt_4bitreg;
  54. u32 dma_sysadr0_reg;
  55. u32 dma_bufbdry_reg;
  56. u32 cpu_rls_reg;
  57. u32 errcnt_5bitreg;
  58. u32 errcnt_6bitreg;
  59. u32 errcnt_7bitreg;
  60. u32 errcnt_8bitreg;
  61. u32 data_if_reg;
  62. };
  63. struct arasan_nand_command_format {
  64. u8 cmd1;
  65. u8 cmd2;
  66. u8 addr_cycles;
  67. u32 pgm;
  68. };
  69. #define ONDIE_ECC_FEATURE_ADDR 0x90
  70. #define ENABLE_ONDIE_ECC 0x08
  71. #define ARASAN_PROG_RD_MASK 0x00000001
  72. #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
  73. #define ARASAN_PROG_RD_ID_MASK 0x00000040
  74. #define ARASAN_PROG_RD_STS_MASK 0x00000008
  75. #define ARASAN_PROG_PG_PROG_MASK 0x00000010
  76. #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
  77. #define ARASAN_PROG_RST_MASK 0x00000100
  78. #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
  79. #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
  80. #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
  81. #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
  82. #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
  83. #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
  84. #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
  85. #define ARASAN_NAND_CMD_CMD2_SHIFT 8
  86. #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
  87. #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
  88. #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
  89. #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
  90. #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
  91. #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
  92. #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
  93. #define ARASAN_NAND_MEM_ADDR2_CS0_MASK (0x3 << 30)
  94. #define ARASAN_NAND_MEM_ADDR2_CS1_MASK (0x1 << 30)
  95. #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
  96. #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
  97. #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
  98. #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
  99. #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
  100. #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
  101. #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
  102. #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
  103. #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
  104. #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
  105. #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
  106. #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
  107. #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
  108. #define ARASAN_NAND_ECC_SIZE_SHIFT 16
  109. #define ARASAN_NAND_ECC_BCH_SHIFT 27
  110. #define ARASAN_NAND_PKTSIZE_1K 1024
  111. #define ARASAN_NAND_PKTSIZE_512 512
  112. #define ARASAN_NAND_POLL_TIMEOUT 1000000
  113. #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
  114. #define ERR_ADDR_CYCLE -1
  115. #define READ_BUFF_SIZE 0x4000
  116. static struct arasan_nand_command_format *curr_cmd;
  117. enum addr_cycles {
  118. NAND_ADDR_CYCL_NONE,
  119. NAND_ADDR_CYCL_ONE,
  120. NAND_ADDR_CYCL_ROW,
  121. NAND_ADDR_CYCL_COL,
  122. NAND_ADDR_CYCL_BOTH,
  123. };
  124. static struct arasan_nand_command_format arasan_nand_commands[] = {
  125. {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH,
  126. ARASAN_PROG_RD_MASK},
  127. {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL,
  128. ARASAN_PROG_RD_MASK},
  129. {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  130. ARASAN_PROG_RD_ID_MASK},
  131. {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
  132. ARASAN_PROG_RD_STS_MASK},
  133. {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH,
  134. ARASAN_PROG_PG_PROG_MASK},
  135. {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL,
  136. ARASAN_PROG_CHNG_ROWADR_END_MASK},
  137. {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW,
  138. ARASAN_PROG_BLK_ERS_MASK},
  139. {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
  140. ARASAN_PROG_RST_MASK},
  141. {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  142. ARASAN_PROG_RD_PARAM_PG_MASK},
  143. {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  144. ARASAN_PROG_GET_FTRS_MASK},
  145. {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
  146. ARASAN_PROG_SET_FTRS_MASK},
  147. {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0},
  148. };
  149. struct arasan_ecc_matrix {
  150. u32 pagesize;
  151. u32 ecc_codeword_size;
  152. u8 eccbits;
  153. u8 bch;
  154. u8 bchval;
  155. u16 eccaddr;
  156. u16 eccsize;
  157. };
  158. static const struct arasan_ecc_matrix ecc_matrix[] = {
  159. {512, 512, 1, 0, 0, 0x20D, 0x3},
  160. {512, 512, 4, 1, 3, 0x209, 0x7},
  161. {512, 512, 8, 1, 2, 0x203, 0xD},
  162. /*
  163. * 2K byte page
  164. */
  165. {2048, 512, 1, 0, 0, 0x834, 0xC},
  166. {2048, 512, 4, 1, 3, 0x826, 0x1A},
  167. {2048, 512, 8, 1, 2, 0x80c, 0x34},
  168. {2048, 512, 12, 1, 1, 0x822, 0x4E},
  169. {2048, 512, 16, 1, 0, 0x808, 0x68},
  170. {2048, 1024, 24, 1, 4, 0x81c, 0x54},
  171. /*
  172. * 4K byte page
  173. */
  174. {4096, 512, 1, 0, 0, 0x1068, 0x18},
  175. {4096, 512, 4, 1, 3, 0x104c, 0x34},
  176. {4096, 512, 8, 1, 2, 0x1018, 0x68},
  177. {4096, 512, 12, 1, 1, 0x1044, 0x9C},
  178. {4096, 512, 16, 1, 0, 0x1010, 0xD0},
  179. {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
  180. /*
  181. * 8K byte page
  182. */
  183. {8192, 512, 1, 0, 0, 0x20d0, 0x30},
  184. {8192, 512, 4, 1, 3, 0x2098, 0x68},
  185. {8192, 512, 8, 1, 2, 0x2030, 0xD0},
  186. {8192, 512, 12, 1, 1, 0x2088, 0x138},
  187. {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
  188. {8192, 1024, 24, 1, 4, 0x2070, 0x150},
  189. /*
  190. * 16K byte page
  191. */
  192. {16384, 512, 1, 0, 0, 0x4460, 0x60},
  193. {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
  194. {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
  195. {16384, 512, 12, 1, 1, 0x4250, 0x270},
  196. {16384, 512, 16, 1, 0, 0x4180, 0x340},
  197. {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
  198. };
  199. static struct nand_ecclayout ondie_nand_oob_64 = {
  200. .eccbytes = 32,
  201. .eccpos = {
  202. 8, 9, 10, 11, 12, 13, 14, 15,
  203. 24, 25, 26, 27, 28, 29, 30, 31,
  204. 40, 41, 42, 43, 44, 45, 46, 47,
  205. 56, 57, 58, 59, 60, 61, 62, 63
  206. },
  207. .oobfree = {
  208. { .offset = 4, .length = 4 },
  209. { .offset = 20, .length = 4 },
  210. { .offset = 36, .length = 4 },
  211. { .offset = 52, .length = 4 }
  212. }
  213. };
  214. /*
  215. * bbt decriptors for chips with on-die ECC and
  216. * chips with 64-byte OOB
  217. */
  218. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  219. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  220. static struct nand_bbt_descr bbt_main_descr = {
  221. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  222. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  223. .offs = 4,
  224. .len = 4,
  225. .veroffs = 20,
  226. .maxblocks = 4,
  227. .pattern = bbt_pattern
  228. };
  229. static struct nand_bbt_descr bbt_mirror_descr = {
  230. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  231. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  232. .offs = 4,
  233. .len = 4,
  234. .veroffs = 20,
  235. .maxblocks = 4,
  236. .pattern = mirror_pattern
  237. };
  238. static u8 buf_data[READ_BUFF_SIZE];
  239. static u32 buf_index;
  240. static struct nand_ecclayout nand_oob;
  241. static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
  242. {
  243. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  244. struct nand_drv *info = nand_get_controller_data(nand_chip);
  245. u32 reg_val;
  246. reg_val = readl(&info->reg->memadr_reg2);
  247. if (chip == 0) {
  248. reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK;
  249. writel(reg_val, &info->reg->memadr_reg2);
  250. } else if (chip == 1) {
  251. reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK;
  252. writel(reg_val, &info->reg->memadr_reg2);
  253. }
  254. }
  255. static void arasan_nand_enable_ecc(struct mtd_info *mtd)
  256. {
  257. struct nand_chip *chip = mtd_to_nand(mtd);
  258. struct nand_drv *info = nand_get_controller_data(chip);
  259. u32 reg_val;
  260. reg_val = readl(&info->reg->cmd_reg);
  261. reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
  262. writel(reg_val, &info->reg->cmd_reg);
  263. }
  264. static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
  265. {
  266. u8 addrcycles;
  267. struct nand_chip *chip = mtd_to_nand(mtd);
  268. switch (curr_cmd->addr_cycles) {
  269. case NAND_ADDR_CYCL_NONE:
  270. addrcycles = 0;
  271. break;
  272. case NAND_ADDR_CYCL_ONE:
  273. addrcycles = 1;
  274. break;
  275. case NAND_ADDR_CYCL_ROW:
  276. addrcycles = chip->onfi_params.addr_cycles &
  277. ARASAN_NAND_ROW_ADDR_CYCL_MASK;
  278. break;
  279. case NAND_ADDR_CYCL_COL:
  280. addrcycles = (chip->onfi_params.addr_cycles &
  281. ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
  282. ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
  283. break;
  284. case NAND_ADDR_CYCL_BOTH:
  285. addrcycles = chip->onfi_params.addr_cycles &
  286. ARASAN_NAND_ROW_ADDR_CYCL_MASK;
  287. addrcycles += (chip->onfi_params.addr_cycles &
  288. ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
  289. ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
  290. break;
  291. default:
  292. addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL;
  293. break;
  294. }
  295. return addrcycles;
  296. }
  297. static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
  298. {
  299. struct nand_chip *chip = mtd_to_nand(mtd);
  300. struct nand_drv *info = nand_get_controller_data(chip);
  301. struct nand_config *nand = &info->config;
  302. u32 reg_val, i, pktsize, pktnum;
  303. u32 *bufptr = (u32 *)buf;
  304. u32 timeout;
  305. u32 rdcount = 0;
  306. u8 addr_cycles;
  307. if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
  308. pktsize = ARASAN_NAND_PKTSIZE_1K;
  309. else
  310. pktsize = ARASAN_NAND_PKTSIZE_512;
  311. if (size % pktsize)
  312. pktnum = size/pktsize + 1;
  313. else
  314. pktnum = size/pktsize;
  315. reg_val = readl(&info->reg->intsts_enr);
  316. reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
  317. ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
  318. writel(reg_val, &info->reg->intsts_enr);
  319. reg_val = readl(&info->reg->pkt_reg);
  320. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  321. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  322. reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
  323. pktsize;
  324. writel(reg_val, &info->reg->pkt_reg);
  325. if (!nand->on_die_ecc_enabled) {
  326. arasan_nand_enable_ecc(mtd);
  327. addr_cycles = arasan_nand_get_addrcycle(mtd);
  328. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  329. return ERR_ADDR_CYCLE;
  330. writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
  331. NAND_CMD_RNDOUT | (addr_cycles <<
  332. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
  333. &info->reg->ecc_sprcmd_reg);
  334. }
  335. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  336. while (rdcount < pktnum) {
  337. timeout = ARASAN_NAND_POLL_TIMEOUT;
  338. while (!(readl(&info->reg->intsts_reg) &
  339. ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
  340. udelay(1);
  341. timeout--;
  342. }
  343. if (!timeout) {
  344. puts("arasan_read_page: timedout:Buff RDY\n");
  345. return -ETIMEDOUT;
  346. }
  347. rdcount++;
  348. if (pktnum == rdcount) {
  349. reg_val = readl(&info->reg->intsts_enr);
  350. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  351. writel(reg_val, &info->reg->intsts_enr);
  352. } else {
  353. reg_val = readl(&info->reg->intsts_enr);
  354. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  355. &info->reg->intsts_enr);
  356. }
  357. reg_val = readl(&info->reg->intsts_reg);
  358. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  359. &info->reg->intsts_reg);
  360. for (i = 0; i < pktsize/4; i++)
  361. bufptr[i] = readl(&info->reg->buf_dataport);
  362. bufptr += pktsize/4;
  363. if (rdcount >= pktnum)
  364. break;
  365. writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  366. &info->reg->intsts_enr);
  367. }
  368. timeout = ARASAN_NAND_POLL_TIMEOUT;
  369. while (!(readl(&info->reg->intsts_reg) &
  370. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  371. udelay(1);
  372. timeout--;
  373. }
  374. if (!timeout) {
  375. puts("arasan rd_page timedout:Xfer CMPLT\n");
  376. return -ETIMEDOUT;
  377. }
  378. reg_val = readl(&info->reg->intsts_enr);
  379. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  380. &info->reg->intsts_enr);
  381. reg_val = readl(&info->reg->intsts_reg);
  382. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  383. &info->reg->intsts_reg);
  384. if (!nand->on_die_ecc_enabled) {
  385. if (readl(&info->reg->intsts_reg) &
  386. ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
  387. printf("arasan rd_page:sbiterror\n");
  388. return -1;
  389. }
  390. if (readl(&info->reg->intsts_reg) &
  391. ARASAN_NAND_INT_STS_ERR_EN_MASK) {
  392. mtd->ecc_stats.failed++;
  393. printf("arasan rd_page:multibiterror\n");
  394. return -1;
  395. }
  396. }
  397. return 0;
  398. }
  399. static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
  400. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  401. {
  402. int status;
  403. status = arasan_nand_read_page(mtd, buf, (mtd->writesize));
  404. if (oob_required)
  405. chip->ecc.read_oob(mtd, chip, page);
  406. return status;
  407. }
  408. static void arasan_nand_fill_tx(struct mtd_info *mtd, const u8 *buf, int len)
  409. {
  410. struct nand_chip *chip = mtd_to_nand(mtd);
  411. struct nand_drv *info = nand_get_controller_data(chip);
  412. u32 __iomem *nand = &info->reg->buf_dataport;
  413. if (((unsigned long)buf & 0x3) != 0) {
  414. if (((unsigned long)buf & 0x1) != 0) {
  415. if (len) {
  416. writeb(*buf, nand);
  417. buf += 1;
  418. len--;
  419. }
  420. }
  421. if (((unsigned long)buf & 0x3) != 0) {
  422. if (len >= 2) {
  423. writew(*(u16 *)buf, nand);
  424. buf += 2;
  425. len -= 2;
  426. }
  427. }
  428. }
  429. while (len >= 4) {
  430. writel(*(u32 *)buf, nand);
  431. buf += 4;
  432. len -= 4;
  433. }
  434. if (len) {
  435. if (len >= 2) {
  436. writew(*(u16 *)buf, nand);
  437. buf += 2;
  438. len -= 2;
  439. }
  440. if (len)
  441. writeb(*buf, nand);
  442. }
  443. }
  444. static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
  445. struct nand_chip *chip, const u8 *buf, int oob_required,
  446. int page)
  447. {
  448. struct nand_drv *info = nand_get_controller_data(chip);
  449. struct nand_config *nand = &info->config;
  450. u32 reg_val, i, pktsize, pktnum;
  451. const u32 *bufptr = (const u32 *)buf;
  452. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  453. u32 size = mtd->writesize;
  454. u32 rdcount = 0;
  455. u8 column_addr_cycles;
  456. if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
  457. pktsize = ARASAN_NAND_PKTSIZE_1K;
  458. else
  459. pktsize = ARASAN_NAND_PKTSIZE_512;
  460. if (size % pktsize)
  461. pktnum = size/pktsize + 1;
  462. else
  463. pktnum = size/pktsize;
  464. reg_val = readl(&info->reg->pkt_reg);
  465. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  466. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  467. reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
  468. writel(reg_val, &info->reg->pkt_reg);
  469. if (!nand->on_die_ecc_enabled) {
  470. arasan_nand_enable_ecc(mtd);
  471. column_addr_cycles = (chip->onfi_params.addr_cycles &
  472. ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
  473. ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
  474. writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
  475. &info->reg->ecc_sprcmd_reg);
  476. }
  477. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  478. while (rdcount < pktnum) {
  479. timeout = ARASAN_NAND_POLL_TIMEOUT;
  480. while (!(readl(&info->reg->intsts_reg) &
  481. ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
  482. udelay(1);
  483. timeout--;
  484. }
  485. if (!timeout) {
  486. puts("arasan_write_page: timedout:Buff RDY\n");
  487. return -ETIMEDOUT;
  488. }
  489. rdcount++;
  490. if (pktnum == rdcount) {
  491. reg_val = readl(&info->reg->intsts_enr);
  492. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  493. writel(reg_val, &info->reg->intsts_enr);
  494. } else {
  495. reg_val = readl(&info->reg->intsts_enr);
  496. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  497. &info->reg->intsts_enr);
  498. }
  499. reg_val = readl(&info->reg->intsts_reg);
  500. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  501. &info->reg->intsts_reg);
  502. for (i = 0; i < pktsize/4; i++)
  503. writel(bufptr[i], &info->reg->buf_dataport);
  504. bufptr += pktsize/4;
  505. if (rdcount >= pktnum)
  506. break;
  507. writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  508. &info->reg->intsts_enr);
  509. }
  510. timeout = ARASAN_NAND_POLL_TIMEOUT;
  511. while (!(readl(&info->reg->intsts_reg) &
  512. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  513. udelay(1);
  514. timeout--;
  515. }
  516. if (!timeout) {
  517. puts("arasan write_page timedout:Xfer CMPLT\n");
  518. return -ETIMEDOUT;
  519. }
  520. reg_val = readl(&info->reg->intsts_enr);
  521. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  522. &info->reg->intsts_enr);
  523. reg_val = readl(&info->reg->intsts_reg);
  524. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  525. &info->reg->intsts_reg);
  526. if (oob_required)
  527. chip->ecc.write_oob(mtd, chip, nand->page);
  528. return 0;
  529. }
  530. static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  531. int page)
  532. {
  533. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  534. chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize));
  535. return 0;
  536. }
  537. static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  538. int page)
  539. {
  540. int status = 0;
  541. const u8 *buf = chip->oob_poi;
  542. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  543. chip->write_buf(mtd, buf, mtd->oobsize);
  544. return status;
  545. }
  546. static int arasan_nand_reset(struct mtd_info *mtd,
  547. struct arasan_nand_command_format *curr_cmd)
  548. {
  549. struct nand_chip *chip = mtd_to_nand(mtd);
  550. struct nand_drv *info = nand_get_controller_data(chip);
  551. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  552. u32 cmd_reg = 0;
  553. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  554. &info->reg->intsts_enr);
  555. cmd_reg = readl(&info->reg->cmd_reg);
  556. cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
  557. cmd_reg |= curr_cmd->cmd1 |
  558. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  559. writel(cmd_reg, &info->reg->cmd_reg);
  560. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  561. while (!(readl(&info->reg->intsts_reg) &
  562. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  563. udelay(1);
  564. timeout--;
  565. }
  566. if (!timeout) {
  567. printf("ERROR:%s timedout\n", __func__);
  568. return -ETIMEDOUT;
  569. }
  570. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  571. &info->reg->intsts_enr);
  572. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  573. &info->reg->intsts_reg);
  574. return 0;
  575. }
  576. static u8 arasan_nand_page(struct mtd_info *mtd)
  577. {
  578. u8 page_val = 0;
  579. switch (mtd->writesize) {
  580. case 512:
  581. page_val = 0;
  582. break;
  583. case 2048:
  584. page_val = 1;
  585. break;
  586. case 4096:
  587. page_val = 2;
  588. break;
  589. case 8192:
  590. page_val = 3;
  591. break;
  592. case 16384:
  593. page_val = 4;
  594. break;
  595. case 1024:
  596. page_val = 5;
  597. break;
  598. default:
  599. printf("%s:Pagesize>16K\n", __func__);
  600. break;
  601. }
  602. return page_val;
  603. }
  604. static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
  605. int column, int page_addr, struct mtd_info *mtd)
  606. {
  607. struct nand_chip *chip = mtd_to_nand(mtd);
  608. struct nand_drv *info = nand_get_controller_data(chip);
  609. u32 reg_val, page;
  610. u8 page_val, addr_cycles;
  611. writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  612. &info->reg->intsts_enr);
  613. reg_val = readl(&info->reg->cmd_reg);
  614. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  615. reg_val |= curr_cmd->cmd1 |
  616. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  617. if (curr_cmd->cmd1 == NAND_CMD_SEQIN) {
  618. reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
  619. page_val = arasan_nand_page(mtd);
  620. reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
  621. }
  622. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  623. addr_cycles = arasan_nand_get_addrcycle(mtd);
  624. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  625. return ERR_ADDR_CYCLE;
  626. reg_val |= (addr_cycles <<
  627. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
  628. writel(reg_val, &info->reg->cmd_reg);
  629. if (page_addr == -1)
  630. page_addr = 0;
  631. page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
  632. ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
  633. column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
  634. writel(page | column, &info->reg->memadr_reg1);
  635. reg_val = readl(&info->reg->memadr_reg2);
  636. reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
  637. reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
  638. writel(reg_val, &info->reg->memadr_reg2);
  639. return 0;
  640. }
  641. static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  642. {
  643. struct nand_chip *chip = mtd_to_nand(mtd);
  644. struct nand_drv *info = nand_get_controller_data(chip);
  645. u32 reg_val;
  646. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  647. reg_val = readl(&info->reg->pkt_reg);
  648. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  649. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  650. reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
  651. writel(reg_val, &info->reg->pkt_reg);
  652. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  653. while (!(readl(&info->reg->intsts_reg) &
  654. ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
  655. udelay(1);
  656. timeout--;
  657. }
  658. if (!timeout)
  659. puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
  660. reg_val = readl(&info->reg->intsts_enr);
  661. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  662. writel(reg_val, &info->reg->intsts_enr);
  663. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  664. &info->reg->intsts_enr);
  665. reg_val = readl(&info->reg->intsts_reg);
  666. writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
  667. &info->reg->intsts_reg);
  668. arasan_nand_fill_tx(mtd, buf, len);
  669. timeout = ARASAN_NAND_POLL_TIMEOUT;
  670. while (!(readl(&info->reg->intsts_reg) &
  671. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  672. udelay(1);
  673. timeout--;
  674. }
  675. if (!timeout)
  676. puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
  677. writel(readl(&info->reg->intsts_enr) |
  678. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  679. &info->reg->intsts_enr);
  680. writel(readl(&info->reg->intsts_reg) |
  681. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  682. &info->reg->intsts_reg);
  683. }
  684. static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
  685. int column, int page_addr, struct mtd_info *mtd)
  686. {
  687. struct nand_chip *chip = mtd_to_nand(mtd);
  688. struct nand_drv *info = nand_get_controller_data(chip);
  689. u32 reg_val, page;
  690. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  691. u8 row_addr_cycles;
  692. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  693. &info->reg->intsts_enr);
  694. reg_val = readl(&info->reg->cmd_reg);
  695. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  696. reg_val |= curr_cmd->cmd1 |
  697. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  698. row_addr_cycles = arasan_nand_get_addrcycle(mtd);
  699. if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  700. return ERR_ADDR_CYCLE;
  701. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  702. reg_val |= (row_addr_cycles <<
  703. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
  704. writel(reg_val, &info->reg->cmd_reg);
  705. page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
  706. ARASAN_NAND_MEM_ADDR1_COL_MASK;
  707. column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
  708. writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
  709. &info->reg->memadr_reg1);
  710. reg_val = readl(&info->reg->memadr_reg2);
  711. reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
  712. reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
  713. writel(reg_val, &info->reg->memadr_reg2);
  714. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  715. while (!(readl(&info->reg->intsts_reg) &
  716. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  717. udelay(1);
  718. timeout--;
  719. }
  720. if (!timeout) {
  721. printf("ERROR:%s timedout:Xfer CMPLT\n", __func__);
  722. return -ETIMEDOUT;
  723. }
  724. reg_val = readl(&info->reg->intsts_enr);
  725. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  726. &info->reg->intsts_enr);
  727. reg_val = readl(&info->reg->intsts_reg);
  728. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  729. &info->reg->intsts_reg);
  730. return 0;
  731. }
  732. static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
  733. int column, int page_addr, struct mtd_info *mtd)
  734. {
  735. struct nand_chip *chip = mtd_to_nand(mtd);
  736. struct nand_drv *info = nand_get_controller_data(chip);
  737. u32 reg_val;
  738. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  739. u8 addr_cycles;
  740. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  741. &info->reg->intsts_enr);
  742. reg_val = readl(&info->reg->cmd_reg);
  743. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  744. reg_val |= curr_cmd->cmd1 |
  745. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  746. addr_cycles = arasan_nand_get_addrcycle(mtd);
  747. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  748. return ERR_ADDR_CYCLE;
  749. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  750. reg_val |= (addr_cycles <<
  751. ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
  752. writel(reg_val, &info->reg->cmd_reg);
  753. reg_val = readl(&info->reg->pkt_reg);
  754. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  755. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  756. reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
  757. writel(reg_val, &info->reg->pkt_reg);
  758. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  759. while (!(readl(&info->reg->intsts_reg) &
  760. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  761. udelay(1);
  762. timeout--;
  763. }
  764. if (!timeout) {
  765. printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__);
  766. return -ETIMEDOUT;
  767. }
  768. reg_val = readl(&info->reg->intsts_enr);
  769. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  770. &info->reg->intsts_enr);
  771. reg_val = readl(&info->reg->intsts_reg);
  772. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  773. &info->reg->intsts_reg);
  774. return 0;
  775. }
  776. static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
  777. int column, int page_addr, struct mtd_info *mtd)
  778. {
  779. struct nand_chip *chip = mtd_to_nand(mtd);
  780. struct nand_drv *info = nand_get_controller_data(chip);
  781. u32 reg_val, addr_cycles, page;
  782. u8 page_val;
  783. reg_val = readl(&info->reg->intsts_enr);
  784. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  785. &info->reg->intsts_enr);
  786. reg_val = readl(&info->reg->cmd_reg);
  787. reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
  788. reg_val |= curr_cmd->cmd1 |
  789. (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
  790. if (curr_cmd->cmd1 == NAND_CMD_RNDOUT ||
  791. curr_cmd->cmd1 == NAND_CMD_READ0) {
  792. reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
  793. page_val = arasan_nand_page(mtd);
  794. reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
  795. }
  796. reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK;
  797. reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
  798. addr_cycles = arasan_nand_get_addrcycle(mtd);
  799. if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
  800. return ERR_ADDR_CYCLE;
  801. reg_val |= (addr_cycles << 28);
  802. writel(reg_val, &info->reg->cmd_reg);
  803. if (page_addr == -1)
  804. page_addr = 0;
  805. page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
  806. ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
  807. column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
  808. writel(page | column, &info->reg->memadr_reg1);
  809. reg_val = readl(&info->reg->memadr_reg2);
  810. reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
  811. reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
  812. writel(reg_val, &info->reg->memadr_reg2);
  813. buf_index = 0;
  814. return 0;
  815. }
  816. static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
  817. {
  818. struct nand_chip *chip = mtd_to_nand(mtd);
  819. struct nand_drv *info = nand_get_controller_data(chip);
  820. u32 reg_val, i;
  821. u32 *bufptr = (u32 *)buf;
  822. u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
  823. reg_val = readl(&info->reg->pkt_reg);
  824. reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
  825. ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
  826. reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
  827. writel(reg_val, &info->reg->pkt_reg);
  828. writel(curr_cmd->pgm, &info->reg->pgm_reg);
  829. while (!(readl(&info->reg->intsts_reg) &
  830. ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
  831. udelay(1);
  832. timeout--;
  833. }
  834. if (!timeout)
  835. puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
  836. reg_val = readl(&info->reg->intsts_enr);
  837. reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
  838. writel(reg_val, &info->reg->intsts_enr);
  839. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  840. &info->reg->intsts_enr);
  841. reg_val = readl(&info->reg->intsts_reg);
  842. writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
  843. &info->reg->intsts_reg);
  844. buf_index = 0;
  845. for (i = 0; i < size / 4; i++)
  846. bufptr[i] = readl(&info->reg->buf_dataport);
  847. if (size & 0x03)
  848. bufptr[i] = readl(&info->reg->buf_dataport);
  849. timeout = ARASAN_NAND_POLL_TIMEOUT;
  850. while (!(readl(&info->reg->intsts_reg) &
  851. ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
  852. udelay(1);
  853. timeout--;
  854. }
  855. if (!timeout)
  856. puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
  857. reg_val = readl(&info->reg->intsts_enr);
  858. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  859. &info->reg->intsts_enr);
  860. reg_val = readl(&info->reg->intsts_reg);
  861. writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  862. &info->reg->intsts_reg);
  863. }
  864. static u8 arasan_nand_read_byte(struct mtd_info *mtd)
  865. {
  866. struct nand_chip *chip = mtd_to_nand(mtd);
  867. struct nand_drv *info = nand_get_controller_data(chip);
  868. u32 size;
  869. u8 val;
  870. struct nand_onfi_params *p;
  871. if (buf_index == 0) {
  872. p = &chip->onfi_params;
  873. if (curr_cmd->cmd1 == NAND_CMD_READID)
  874. size = 4;
  875. else if (curr_cmd->cmd1 == NAND_CMD_PARAM)
  876. size = sizeof(struct nand_onfi_params);
  877. else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT)
  878. size = le16_to_cpu(p->ext_param_page_length) * 16;
  879. else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
  880. size = 4;
  881. else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
  882. return readb(&info->reg->flash_sts_reg);
  883. else
  884. size = 8;
  885. chip->read_buf(mtd, &buf_data[0], size);
  886. }
  887. val = *(&buf_data[0] + buf_index);
  888. buf_index++;
  889. return val;
  890. }
  891. static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  892. int column, int page_addr)
  893. {
  894. struct nand_chip *chip = mtd_to_nand(mtd);
  895. struct nand_drv *info = nand_get_controller_data(chip);
  896. struct nand_config *nand = &info->config;
  897. u32 i, ret = 0;
  898. curr_cmd = NULL;
  899. writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
  900. &info->reg->intsts_enr);
  901. if ((command == NAND_CMD_READOOB) &&
  902. (mtd->writesize > 512)) {
  903. column += mtd->writesize;
  904. command = NAND_CMD_READ0;
  905. }
  906. /* Get the command format */
  907. for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE ||
  908. arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) {
  909. if (command == arasan_nand_commands[i].cmd1) {
  910. curr_cmd = &arasan_nand_commands[i];
  911. break;
  912. }
  913. }
  914. if (curr_cmd == NULL) {
  915. printf("Unsupported Command; 0x%x\n", command);
  916. return;
  917. }
  918. if (curr_cmd->cmd1 == NAND_CMD_RESET)
  919. ret = arasan_nand_reset(mtd, curr_cmd);
  920. if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
  921. (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
  922. (curr_cmd->cmd1 == NAND_CMD_RNDOUT) ||
  923. (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) ||
  924. (curr_cmd->cmd1 == NAND_CMD_READ0))
  925. ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd);
  926. if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) ||
  927. (curr_cmd->cmd1 == NAND_CMD_SEQIN)) {
  928. nand->page = page_addr;
  929. ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd);
  930. }
  931. if (curr_cmd->cmd1 == NAND_CMD_ERASE1)
  932. ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd);
  933. if (curr_cmd->cmd1 == NAND_CMD_STATUS)
  934. ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd);
  935. if (ret != 0)
  936. printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
  937. }
  938. static void arasan_check_ondie(struct mtd_info *mtd)
  939. {
  940. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  941. struct nand_drv *info = nand_get_controller_data(nand_chip);
  942. struct nand_config *nand = &info->config;
  943. u8 maf_id, dev_id;
  944. u8 get_feature[4];
  945. u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
  946. u32 i;
  947. nand_chip->select_chip(mtd, 0);
  948. /* Send the command for reading device ID */
  949. nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  950. nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
  951. /* Read manufacturer and device IDs */
  952. maf_id = nand_chip->read_byte(mtd);
  953. dev_id = nand_chip->read_byte(mtd);
  954. if ((maf_id == NAND_MFR_MICRON) &&
  955. ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) ||
  956. (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) ||
  957. (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) ||
  958. (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) ||
  959. (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) {
  960. nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
  961. ONDIE_ECC_FEATURE_ADDR, -1);
  962. nand_chip->write_buf(mtd, &set_feature[0], 4);
  963. nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
  964. ONDIE_ECC_FEATURE_ADDR, -1);
  965. for (i = 0; i < 4; i++)
  966. get_feature[i] = nand_chip->read_byte(mtd);
  967. if (get_feature[0] & ENABLE_ONDIE_ECC) {
  968. nand->on_die_ecc_enabled = true;
  969. printf("On-DIE ECC Enabled\n");
  970. } else {
  971. printf("%s: Unable to enable OnDie ECC\n", __func__);
  972. }
  973. /* Use the BBT pattern descriptors */
  974. nand_chip->bbt_td = &bbt_main_descr;
  975. nand_chip->bbt_md = &bbt_mirror_descr;
  976. }
  977. }
  978. static int arasan_nand_ecc_init(struct mtd_info *mtd)
  979. {
  980. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  981. struct nand_drv *info = nand_get_controller_data(nand_chip);
  982. int found = -1;
  983. u32 regval, eccpos_start, i, eccaddr;
  984. for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
  985. if ((ecc_matrix[i].pagesize == mtd->writesize) &&
  986. (ecc_matrix[i].ecc_codeword_size >=
  987. nand_chip->ecc_step_ds)) {
  988. if (ecc_matrix[i].eccbits >=
  989. nand_chip->ecc_strength_ds) {
  990. found = i;
  991. break;
  992. }
  993. found = i;
  994. }
  995. }
  996. if (found < 0)
  997. return 1;
  998. eccaddr = mtd->writesize + mtd->oobsize -
  999. ecc_matrix[found].eccsize;
  1000. regval = eccaddr |
  1001. (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
  1002. (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
  1003. writel(regval, &info->reg->ecc_reg);
  1004. if (ecc_matrix[found].bch) {
  1005. regval = readl(&info->reg->memadr_reg2);
  1006. regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
  1007. regval |= (ecc_matrix[found].bchval <<
  1008. ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
  1009. writel(regval, &info->reg->memadr_reg2);
  1010. }
  1011. nand_oob.eccbytes = ecc_matrix[found].eccsize;
  1012. eccpos_start = mtd->oobsize - nand_oob.eccbytes;
  1013. for (i = 0; i < nand_oob.eccbytes; i++)
  1014. nand_oob.eccpos[i] = eccpos_start + i;
  1015. nand_oob.oobfree[0].offset = 2;
  1016. nand_oob.oobfree[0].length = eccpos_start - 2;
  1017. nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
  1018. nand_chip->ecc.strength = ecc_matrix[found].eccbits;
  1019. nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
  1020. nand_chip->ecc.layout = &nand_oob;
  1021. return 0;
  1022. }
  1023. static int arasan_probe(struct udevice *dev)
  1024. {
  1025. struct arasan_nand_info *arasan = dev_get_priv(dev);
  1026. struct nand_chip *nand_chip = &arasan->nand_chip;
  1027. struct nand_drv *info = &arasan->nand_ctrl;
  1028. struct nand_config *nand = &info->config;
  1029. struct mtd_info *mtd;
  1030. int err = -1;
  1031. info->reg = (struct nand_regs *)dev_read_addr(dev);
  1032. mtd = nand_to_mtd(nand_chip);
  1033. nand_set_controller_data(nand_chip, &arasan->nand_ctrl);
  1034. #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
  1035. nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
  1036. #endif
  1037. /* Set the driver entry points for MTD */
  1038. nand_chip->cmdfunc = arasan_nand_cmd_function;
  1039. nand_chip->select_chip = arasan_nand_select_chip;
  1040. nand_chip->read_byte = arasan_nand_read_byte;
  1041. /* Buffer read/write routines */
  1042. nand_chip->read_buf = arasan_nand_read_buf;
  1043. nand_chip->write_buf = arasan_nand_write_buf;
  1044. nand_chip->bbt_options = NAND_BBT_USE_FLASH;
  1045. writel(0x0, &info->reg->cmd_reg);
  1046. writel(0x0, &info->reg->pgm_reg);
  1047. /* first scan to find the device and get the page size */
  1048. if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) {
  1049. printf("%s: nand_scan_ident failed\n", __func__);
  1050. goto fail;
  1051. }
  1052. nand_chip->ecc.mode = NAND_ECC_HW;
  1053. nand_chip->ecc.hwctl = NULL;
  1054. nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
  1055. nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
  1056. nand_chip->ecc.read_oob = arasan_nand_read_oob;
  1057. nand_chip->ecc.write_oob = arasan_nand_write_oob;
  1058. arasan_check_ondie(mtd);
  1059. /*
  1060. * If on die supported, then give priority to on-die ecc and use
  1061. * it instead of controller ecc.
  1062. */
  1063. if (nand->on_die_ecc_enabled) {
  1064. nand_chip->ecc.strength = 1;
  1065. nand_chip->ecc.size = mtd->writesize;
  1066. nand_chip->ecc.bytes = 0;
  1067. nand_chip->ecc.layout = &ondie_nand_oob_64;
  1068. } else {
  1069. if (arasan_nand_ecc_init(mtd)) {
  1070. printf("%s: nand_ecc_init failed\n", __func__);
  1071. goto fail;
  1072. }
  1073. }
  1074. if (nand_scan_tail(mtd)) {
  1075. printf("%s: nand_scan_tail failed\n", __func__);
  1076. goto fail;
  1077. }
  1078. if (nand_register(0, mtd)) {
  1079. printf("Nand Register Fail\n");
  1080. goto fail;
  1081. }
  1082. return 0;
  1083. fail:
  1084. free(nand);
  1085. return err;
  1086. }
  1087. static const struct udevice_id arasan_nand_dt_ids[] = {
  1088. {.compatible = "arasan,nfc-v3p10",},
  1089. { /* sentinel */ }
  1090. };
  1091. U_BOOT_DRIVER(arasan_nand) = {
  1092. .name = "arasan_nand",
  1093. .id = UCLASS_MTD,
  1094. .of_match = arasan_nand_dt_ids,
  1095. .probe = arasan_probe,
  1096. .priv_auto_alloc_size = sizeof(struct arasan_nand_info),
  1097. };
  1098. void board_nand_init(void)
  1099. {
  1100. struct udevice *dev;
  1101. int ret;
  1102. ret = uclass_get_device_by_driver(UCLASS_MTD,
  1103. DM_GET_DRIVER(arasan_nand), &dev);
  1104. if (ret && ret != -ENODEV)
  1105. pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
  1106. }