Kconfig 12 KB

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  1. menuconfig MTD_RAW_NAND
  2. bool "Raw NAND Device Support"
  3. if MTD_RAW_NAND
  4. config SYS_NAND_SELF_INIT
  5. bool
  6. help
  7. This option, if enabled, provides more flexible and linux-like
  8. NAND initialization process.
  9. config SYS_NAND_DRIVER_ECC_LAYOUT
  10. bool
  11. help
  12. Omit standard ECC layouts to safe space. Select this if your driver
  13. is known to provide its own ECC layout.
  14. config SYS_NAND_USE_FLASH_BBT
  15. bool "Enable BBT (Bad Block Table) support"
  16. help
  17. Enable the BBT (Bad Block Table) usage.
  18. config NAND_ATMEL
  19. bool "Support Atmel NAND controller"
  20. imply SYS_NAND_USE_FLASH_BBT
  21. help
  22. Enable this driver for NAND flash platforms using an Atmel NAND
  23. controller.
  24. if NAND_ATMEL
  25. config ATMEL_NAND_HWECC
  26. bool "Atmel Hardware ECC"
  27. default n
  28. config ATMEL_NAND_HW_PMECC
  29. bool "Atmel Programmable Multibit ECC (PMECC)"
  30. select ATMEL_NAND_HWECC
  31. default n
  32. help
  33. The Programmable Multibit ECC (PMECC) controller is a programmable
  34. binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
  35. config PMECC_CAP
  36. int "PMECC Correctable ECC Bits"
  37. depends on ATMEL_NAND_HW_PMECC
  38. default 2
  39. help
  40. Correctable ECC bits, can be 2, 4, 8, 12, and 24.
  41. config PMECC_SECTOR_SIZE
  42. int "PMECC Sector Size"
  43. depends on ATMEL_NAND_HW_PMECC
  44. default 512
  45. help
  46. Sector size, in bytes, can be 512 or 1024.
  47. config SPL_GENERATE_ATMEL_PMECC_HEADER
  48. bool "Atmel PMECC Header Generation"
  49. select ATMEL_NAND_HWECC
  50. select ATMEL_NAND_HW_PMECC
  51. default n
  52. help
  53. Generate Programmable Multibit ECC (PMECC) header for SPL image.
  54. endif
  55. config NAND_BRCMNAND
  56. bool "Support Broadcom NAND controller"
  57. depends on OF_CONTROL && DM && DM_MTD
  58. help
  59. Enable the driver for NAND flash on platforms using a Broadcom NAND
  60. controller.
  61. config NAND_BRCMNAND_6368
  62. bool "Support Broadcom NAND controller on bcm6368"
  63. depends on NAND_BRCMNAND && ARCH_BMIPS
  64. help
  65. Enable support for broadcom nand driver on bcm6368.
  66. config NAND_BRCMNAND_68360
  67. bool "Support Broadcom NAND controller on bcm68360"
  68. depends on NAND_BRCMNAND && ARCH_BCM68360
  69. help
  70. Enable support for broadcom nand driver on bcm68360.
  71. config NAND_BRCMNAND_6838
  72. bool "Support Broadcom NAND controller on bcm6838"
  73. depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
  74. help
  75. Enable support for broadcom nand driver on bcm6838.
  76. config NAND_BRCMNAND_6858
  77. bool "Support Broadcom NAND controller on bcm6858"
  78. depends on NAND_BRCMNAND && ARCH_BCM6858
  79. help
  80. Enable support for broadcom nand driver on bcm6858.
  81. config NAND_BRCMNAND_63158
  82. bool "Support Broadcom NAND controller on bcm63158"
  83. depends on NAND_BRCMNAND && ARCH_BCM63158
  84. help
  85. Enable support for broadcom nand driver on bcm63158.
  86. config NAND_DAVINCI
  87. bool "Support TI Davinci NAND controller"
  88. help
  89. Enable this driver for NAND flash controllers available in TI Davinci
  90. and Keystone2 platforms
  91. config NAND_DENALI
  92. bool
  93. select SYS_NAND_SELF_INIT
  94. imply CMD_NAND
  95. config NAND_DENALI_DT
  96. bool "Support Denali NAND controller as a DT device"
  97. select NAND_DENALI
  98. depends on OF_CONTROL && DM_MTD
  99. help
  100. Enable the driver for NAND flash on platforms using a Denali NAND
  101. controller as a DT device.
  102. config NAND_LPC32XX_SLC
  103. bool "Support LPC32XX_SLC controller"
  104. help
  105. Enable the LPC32XX SLC NAND controller.
  106. config NAND_OMAP_GPMC
  107. bool "Support OMAP GPMC NAND controller"
  108. depends on ARCH_OMAP2PLUS
  109. help
  110. Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
  111. GPMC controller is used for parallel NAND flash devices, and can
  112. do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
  113. and BCH16 ECC algorithms.
  114. config NAND_OMAP_GPMC_PREFETCH
  115. bool "Enable GPMC Prefetch"
  116. depends on NAND_OMAP_GPMC
  117. default y
  118. help
  119. On OMAP platforms that use the GPMC controller
  120. (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
  121. uses the prefetch mode to speed up read operations.
  122. config NAND_OMAP_ELM
  123. bool "Enable ELM driver for OMAPxx and AMxx platforms."
  124. depends on NAND_OMAP_GPMC && !OMAP34XX
  125. help
  126. ELM controller is used for ECC error detection (not ECC calculation)
  127. of BCH4, BCH8 and BCH16 ECC algorithms.
  128. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  129. thus such SoC platforms need to depend on software library for ECC error
  130. detection. However ECC calculation on such plaforms would still be
  131. done by GPMC controller.
  132. config NAND_VF610_NFC
  133. bool "Support for Freescale NFC for VF610"
  134. select SYS_NAND_SELF_INIT
  135. select SYS_NAND_DRIVER_ECC_LAYOUT
  136. imply CMD_NAND
  137. help
  138. Enables support for NAND Flash Controller on some Freescale
  139. processors like the VF610, MCF54418 or Kinetis K70.
  140. The driver supports a maximum 2k page size. The driver
  141. currently does not support hardware ECC.
  142. if NAND_VF610_NFC
  143. config NAND_VF610_NFC_DT
  144. bool "Support Vybrid's vf610 NAND controller as a DT device"
  145. depends on OF_CONTROL && DM_MTD
  146. help
  147. Enable the driver for Vybrid's vf610 NAND flash on platforms
  148. using device tree.
  149. choice
  150. prompt "Hardware ECC strength"
  151. depends on NAND_VF610_NFC
  152. default SYS_NAND_VF610_NFC_45_ECC_BYTES
  153. help
  154. Select the ECC strength used in the hardware BCH ECC block.
  155. config SYS_NAND_VF610_NFC_45_ECC_BYTES
  156. bool "24-error correction (45 ECC bytes)"
  157. config SYS_NAND_VF610_NFC_60_ECC_BYTES
  158. bool "32-error correction (60 ECC bytes)"
  159. endchoice
  160. endif
  161. config NAND_PXA3XX
  162. bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
  163. select SYS_NAND_SELF_INIT
  164. imply CMD_NAND
  165. help
  166. This enables the driver for the NAND flash device found on
  167. PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
  168. config NAND_SUNXI
  169. bool "Support for NAND on Allwinner SoCs"
  170. default ARCH_SUNXI
  171. depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
  172. select SYS_NAND_SELF_INIT
  173. select SYS_NAND_U_BOOT_LOCATIONS
  174. select SPL_NAND_SUPPORT
  175. imply CMD_NAND
  176. ---help---
  177. Enable support for NAND. This option enables the standard and
  178. SPL drivers.
  179. The SPL driver only supports reading from the NAND using DMA
  180. transfers.
  181. if NAND_SUNXI
  182. config NAND_SUNXI_SPL_ECC_STRENGTH
  183. int "Allwinner NAND SPL ECC Strength"
  184. default 64
  185. config NAND_SUNXI_SPL_ECC_SIZE
  186. int "Allwinner NAND SPL ECC Step Size"
  187. default 1024
  188. config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
  189. int "Allwinner NAND SPL Usable Page Size"
  190. default 1024
  191. endif
  192. config NAND_ARASAN
  193. bool "Configure Arasan Nand"
  194. select SYS_NAND_SELF_INIT
  195. depends on DM_MTD
  196. imply CMD_NAND
  197. help
  198. This enables Nand driver support for Arasan nand flash
  199. controller. This uses the hardware ECC for read and
  200. write operations.
  201. config NAND_MXC
  202. bool "MXC NAND support"
  203. depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
  204. imply CMD_NAND
  205. help
  206. This enables the NAND driver for the NAND flash controller on the
  207. i.MX27 / i.MX31 / i.MX5 rocessors.
  208. config NAND_MXS
  209. bool "MXS NAND support"
  210. depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
  211. select SYS_NAND_SELF_INIT
  212. imply CMD_NAND
  213. select APBH_DMA
  214. select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
  215. select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
  216. help
  217. This enables NAND driver for the NAND flash controller on the
  218. MXS processors.
  219. if NAND_MXS
  220. config NAND_MXS_DT
  221. bool "Support MXS NAND controller as a DT device"
  222. depends on OF_CONTROL && DM_MTD
  223. help
  224. Enable the driver for MXS NAND flash on platforms using
  225. device tree.
  226. config NAND_MXS_USE_MINIMUM_ECC
  227. bool "Use minimum ECC strength supported by the controller"
  228. default false
  229. endif
  230. config NAND_ZYNQ
  231. bool "Support for Zynq Nand controller"
  232. select SYS_NAND_SELF_INIT
  233. select DM_MTD
  234. imply CMD_NAND
  235. help
  236. This enables Nand driver support for Nand flash controller
  237. found on Zynq SoC.
  238. config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  239. bool "Enable use of 1st stage bootloader timing for NAND"
  240. depends on NAND_ZYNQ
  241. help
  242. This flag prevent U-boot reconfigure NAND flash controller and reuse
  243. the NAND timing from 1st stage bootloader.
  244. config NAND_STM32_FMC2
  245. bool "Support for NAND controller on STM32MP SoCs"
  246. depends on ARCH_STM32MP
  247. select SYS_NAND_SELF_INIT
  248. imply CMD_NAND
  249. help
  250. Enables support for NAND Flash chips on SoCs containing the FMC2
  251. NAND controller. This controller is found on STM32MP SoCs.
  252. The controller supports a maximum 8k page size and supports
  253. a maximum 8-bit correction error per sector of 512 bytes.
  254. comment "Generic NAND options"
  255. config SYS_NAND_BLOCK_SIZE
  256. hex "NAND chip eraseblock size"
  257. depends on ARCH_SUNXI
  258. help
  259. Number of data bytes in one eraseblock for the NAND chip on the
  260. board. This is the multiple of NAND_PAGE_SIZE and the number of
  261. pages.
  262. config SYS_NAND_PAGE_SIZE
  263. hex "NAND chip page size"
  264. depends on ARCH_SUNXI
  265. help
  266. Number of data bytes in one page for the NAND chip on the
  267. board, not including the OOB area.
  268. config SYS_NAND_OOBSIZE
  269. hex "NAND chip OOB size"
  270. depends on ARCH_SUNXI
  271. help
  272. Number of bytes in the Out-Of-Band area for the NAND chip on
  273. the board.
  274. # Enhance depends when converting drivers to Kconfig which use this config
  275. # option (mxc_nand, ndfc, omap_gpmc).
  276. config SYS_NAND_BUSWIDTH_16BIT
  277. bool "Use 16-bit NAND interface"
  278. depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
  279. help
  280. Indicates that NAND device has 16-bit wide data-bus. In absence of this
  281. config, bus-width of NAND device is assumed to be either 8-bit and later
  282. determined by reading ONFI params.
  283. Above config is useful when NAND device's bus-width information cannot
  284. be determined from on-chip ONFI params, like in following scenarios:
  285. - SPL boot does not support reading of ONFI parameters. This is done to
  286. keep SPL code foot-print small.
  287. - In current U-Boot flow using nand_init(), driver initialization
  288. happens in board_nand_init() which is called before any device probe
  289. (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
  290. not available while configuring controller. So a static CONFIG_NAND_xx
  291. is needed to know the device's bus-width in advance.
  292. config SYS_NAND_MAX_CHIPS
  293. int "NAND max chips"
  294. default 1
  295. depends on NAND_ARASAN
  296. help
  297. The maximum number of NAND chips per device to be supported.
  298. if SPL
  299. config SYS_NAND_U_BOOT_LOCATIONS
  300. bool "Define U-boot binaries locations in NAND"
  301. help
  302. Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
  303. This option should not be enabled when compiling U-boot for boards
  304. defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
  305. file.
  306. config SYS_NAND_U_BOOT_OFFS
  307. hex "Location in NAND to read U-Boot from"
  308. default 0x800000 if NAND_SUNXI
  309. depends on SYS_NAND_U_BOOT_LOCATIONS
  310. help
  311. Set the offset from the start of the nand where u-boot should be
  312. loaded from.
  313. config SYS_NAND_U_BOOT_OFFS_REDUND
  314. hex "Location in NAND to read U-Boot from"
  315. default SYS_NAND_U_BOOT_OFFS
  316. depends on SYS_NAND_U_BOOT_LOCATIONS
  317. help
  318. Set the offset from the start of the nand where the redundant u-boot
  319. should be loaded from.
  320. config SPL_NAND_AM33XX_BCH
  321. bool "Enables SPL-NAND driver which supports ELM based"
  322. depends on NAND_OMAP_GPMC && !OMAP34XX
  323. default y
  324. help
  325. Hardware ECC correction. This is useful for platforms which have ELM
  326. hardware engine and use NAND boot mode.
  327. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  328. so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
  329. SPL-NAND driver with software ECC correction support.
  330. config SPL_NAND_DENALI
  331. bool "Support Denali NAND controller for SPL"
  332. help
  333. This is a small implementation of the Denali NAND controller
  334. for use on SPL.
  335. config NAND_DENALI_SPARE_AREA_SKIP_BYTES
  336. int "Number of bytes skipped in OOB area"
  337. depends on SPL_NAND_DENALI
  338. range 0 63
  339. help
  340. This option specifies the number of bytes to skip from the beginning
  341. of OOB area before last ECC sector data starts. This is potentially
  342. used to preserve the bad block marker in the OOB area.
  343. config SPL_NAND_SIMPLE
  344. bool "Use simple SPL NAND driver"
  345. depends on !SPL_NAND_AM33XX_BCH
  346. help
  347. Support for NAND boot using simple NAND drivers that
  348. expose the cmd_ctrl() interface.
  349. endif
  350. endif # if NAND