sh_i2c.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011, 2013 Renesas Solutions Corp.
  4. * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  5. *
  6. * NOTE: This driver should be converted to driver model before June 2017.
  7. * Please see doc/driver-model/i2c-howto.rst for instructions.
  8. */
  9. #include <common.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <linux/delay.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /* Every register is 32bit aligned, but only 8bits in size */
  16. #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
  17. struct sh_i2c {
  18. ureg(icdr);
  19. ureg(iccr);
  20. ureg(icsr);
  21. ureg(icic);
  22. ureg(iccl);
  23. ureg(icch);
  24. };
  25. #undef ureg
  26. /* ICCR */
  27. #define SH_I2C_ICCR_ICE (1 << 7)
  28. #define SH_I2C_ICCR_RACK (1 << 6)
  29. #define SH_I2C_ICCR_RTS (1 << 4)
  30. #define SH_I2C_ICCR_BUSY (1 << 2)
  31. #define SH_I2C_ICCR_SCP (1 << 0)
  32. /* ICSR / ICIC */
  33. #define SH_IC_BUSY (1 << 4)
  34. #define SH_IC_TACK (1 << 2)
  35. #define SH_IC_WAIT (1 << 1)
  36. #define SH_IC_DTE (1 << 0)
  37. #ifdef CONFIG_SH_I2C_8BIT
  38. /* store 8th bit of iccl and icch in ICIC register */
  39. #define SH_I2C_ICIC_ICCLB8 (1 << 7)
  40. #define SH_I2C_ICIC_ICCHB8 (1 << 6)
  41. #endif
  42. static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
  43. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
  44. #ifdef CONFIG_SYS_I2C_SH_BASE1
  45. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
  46. #endif
  47. #ifdef CONFIG_SYS_I2C_SH_BASE2
  48. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
  49. #endif
  50. #ifdef CONFIG_SYS_I2C_SH_BASE3
  51. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
  52. #endif
  53. #ifdef CONFIG_SYS_I2C_SH_BASE4
  54. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
  55. #endif
  56. };
  57. static u16 iccl, icch;
  58. #define IRQ_WAIT 1000
  59. static void sh_irq_dte(struct sh_i2c *dev)
  60. {
  61. int i;
  62. for (i = 0; i < IRQ_WAIT; i++) {
  63. if (SH_IC_DTE & readb(&dev->icsr))
  64. break;
  65. udelay(10);
  66. }
  67. }
  68. static int sh_irq_dte_with_tack(struct sh_i2c *dev)
  69. {
  70. int i;
  71. for (i = 0; i < IRQ_WAIT; i++) {
  72. if (SH_IC_DTE & readb(&dev->icsr))
  73. break;
  74. if (SH_IC_TACK & readb(&dev->icsr))
  75. return -1;
  76. udelay(10);
  77. }
  78. return 0;
  79. }
  80. static void sh_irq_busy(struct sh_i2c *dev)
  81. {
  82. int i;
  83. for (i = 0; i < IRQ_WAIT; i++) {
  84. if (!(SH_IC_BUSY & readb(&dev->icsr)))
  85. break;
  86. udelay(10);
  87. }
  88. }
  89. static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
  90. {
  91. u8 icic = SH_IC_TACK;
  92. debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
  93. __func__, chip, addr, iccl, icch);
  94. clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  95. setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  96. writeb(iccl & 0xff, &dev->iccl);
  97. writeb(icch & 0xff, &dev->icch);
  98. #ifdef CONFIG_SH_I2C_8BIT
  99. if (iccl > 0xff)
  100. icic |= SH_I2C_ICIC_ICCLB8;
  101. if (icch > 0xff)
  102. icic |= SH_I2C_ICIC_ICCHB8;
  103. #endif
  104. writeb(icic, &dev->icic);
  105. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
  106. sh_irq_dte(dev);
  107. clrbits_8(&dev->icsr, SH_IC_TACK);
  108. writeb(chip << 1, &dev->icdr);
  109. if (sh_irq_dte_with_tack(dev) != 0)
  110. return -1;
  111. writeb(addr, &dev->icdr);
  112. if (stop)
  113. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
  114. if (sh_irq_dte_with_tack(dev) != 0)
  115. return -1;
  116. return 0;
  117. }
  118. static void sh_i2c_finish(struct sh_i2c *dev)
  119. {
  120. writeb(0, &dev->icsr);
  121. clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  122. }
  123. static int
  124. sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
  125. {
  126. int ret = -1;
  127. if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
  128. goto exit0;
  129. udelay(10);
  130. writeb(val, &dev->icdr);
  131. if (sh_irq_dte_with_tack(dev) != 0)
  132. goto exit0;
  133. writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
  134. if (sh_irq_dte_with_tack(dev) != 0)
  135. goto exit0;
  136. sh_irq_busy(dev);
  137. ret = 0;
  138. exit0:
  139. sh_i2c_finish(dev);
  140. return ret;
  141. }
  142. static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
  143. {
  144. int ret = -1;
  145. #if defined(CONFIG_SH73A0)
  146. if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
  147. goto exit0;
  148. #else
  149. if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
  150. goto exit0;
  151. udelay(100);
  152. #endif
  153. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
  154. sh_irq_dte(dev);
  155. writeb(chip << 1 | 0x01, &dev->icdr);
  156. if (sh_irq_dte_with_tack(dev) != 0)
  157. goto exit0;
  158. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
  159. if (sh_irq_dte_with_tack(dev) != 0)
  160. goto exit0;
  161. ret = readb(&dev->icdr) & 0xff;
  162. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
  163. readb(&dev->icdr); /* Dummy read */
  164. sh_irq_busy(dev);
  165. exit0:
  166. sh_i2c_finish(dev);
  167. return ret;
  168. }
  169. static void
  170. sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  171. {
  172. int num, denom, tmp;
  173. /* No i2c support prior to relocation */
  174. if (!(gd->flags & GD_FLG_RELOC))
  175. return;
  176. /*
  177. * Calculate the value for iccl. From the data sheet:
  178. * iccl = (p-clock / transfer-rate) * (L / (L + H))
  179. * where L and H are the SCL low and high ratio.
  180. */
  181. num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
  182. denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
  183. tmp = num * 10 / denom;
  184. if (tmp % 10 >= 5)
  185. iccl = (u16)((num/denom) + 1);
  186. else
  187. iccl = (u16)(num/denom);
  188. /* Calculate the value for icch. From the data sheet:
  189. icch = (p clock / transfer rate) * (H / (L + H)) */
  190. num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
  191. tmp = num * 10 / denom;
  192. if (tmp % 10 >= 5)
  193. icch = (u16)((num/denom) + 1);
  194. else
  195. icch = (u16)(num/denom);
  196. debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
  197. CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
  198. }
  199. static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  200. uint addr, int alen, u8 *data, int len)
  201. {
  202. int ret, i;
  203. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  204. for (i = 0; i < len; i++) {
  205. ret = sh_i2c_raw_read(dev, chip, addr + i);
  206. if (ret < 0)
  207. return -1;
  208. data[i] = ret & 0xff;
  209. debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
  210. }
  211. return 0;
  212. }
  213. static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
  214. int alen, u8 *data, int len)
  215. {
  216. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  217. int i;
  218. for (i = 0; i < len; i++) {
  219. debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
  220. if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
  221. return -1;
  222. }
  223. return 0;
  224. }
  225. static int
  226. sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
  227. {
  228. u8 dummy[1];
  229. return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
  230. }
  231. static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
  232. unsigned int speed)
  233. {
  234. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  235. sh_i2c_finish(dev);
  236. sh_i2c_init(adap, speed, 0);
  237. return 0;
  238. }
  239. /*
  240. * Register RCAR i2c adapters
  241. */
  242. U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  243. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
  244. #ifdef CONFIG_SYS_I2C_SH_BASE1
  245. U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  246. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
  247. #endif
  248. #ifdef CONFIG_SYS_I2C_SH_BASE2
  249. U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  250. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
  251. #endif
  252. #ifdef CONFIG_SYS_I2C_SH_BASE3
  253. U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  254. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
  255. #endif
  256. #ifdef CONFIG_SYS_I2C_SH_BASE4
  257. U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  258. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
  259. #endif