i2c-cdns.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
  4. * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
  5. *
  6. * This file is based on: drivers/i2c/zynq_i2c.c,
  7. * with added driver-model support and code cleanup.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <linux/bitops.h>
  13. #include <linux/delay.h>
  14. #include <linux/types.h>
  15. #include <linux/io.h>
  16. #include <linux/errno.h>
  17. #include <dm/root.h>
  18. #include <i2c.h>
  19. #include <fdtdec.h>
  20. #include <mapmem.h>
  21. #include <wait_bit.h>
  22. #include <clk.h>
  23. /* i2c register set */
  24. struct cdns_i2c_regs {
  25. u32 control;
  26. u32 status;
  27. u32 address;
  28. u32 data;
  29. u32 interrupt_status;
  30. u32 transfer_size;
  31. u32 slave_mon_pause;
  32. u32 time_out;
  33. u32 interrupt_mask;
  34. u32 interrupt_enable;
  35. u32 interrupt_disable;
  36. };
  37. /* Control register fields */
  38. #define CDNS_I2C_CONTROL_RW 0x00000001
  39. #define CDNS_I2C_CONTROL_MS 0x00000002
  40. #define CDNS_I2C_CONTROL_NEA 0x00000004
  41. #define CDNS_I2C_CONTROL_ACKEN 0x00000008
  42. #define CDNS_I2C_CONTROL_HOLD 0x00000010
  43. #define CDNS_I2C_CONTROL_SLVMON 0x00000020
  44. #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
  45. #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
  46. #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
  47. #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
  48. #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
  49. /* Status register values */
  50. #define CDNS_I2C_STATUS_RXDV 0x00000020
  51. #define CDNS_I2C_STATUS_TXDV 0x00000040
  52. #define CDNS_I2C_STATUS_RXOVF 0x00000080
  53. #define CDNS_I2C_STATUS_BA 0x00000100
  54. /* Interrupt register fields */
  55. #define CDNS_I2C_INTERRUPT_COMP 0x00000001
  56. #define CDNS_I2C_INTERRUPT_DATA 0x00000002
  57. #define CDNS_I2C_INTERRUPT_NACK 0x00000004
  58. #define CDNS_I2C_INTERRUPT_TO 0x00000008
  59. #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
  60. #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
  61. #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
  62. #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
  63. #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
  64. #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
  65. CDNS_I2C_INTERRUPT_DATA | \
  66. CDNS_I2C_INTERRUPT_NACK | \
  67. CDNS_I2C_INTERRUPT_TO | \
  68. CDNS_I2C_INTERRUPT_SLVRDY | \
  69. CDNS_I2C_INTERRUPT_RXOVF | \
  70. CDNS_I2C_INTERRUPT_TXOVF | \
  71. CDNS_I2C_INTERRUPT_RXUNF | \
  72. CDNS_I2C_INTERRUPT_ARBLOST)
  73. #define CDNS_I2C_FIFO_DEPTH 16
  74. #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
  75. #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  76. #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
  77. #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
  78. #ifdef DEBUG
  79. static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  80. {
  81. int int_status;
  82. int status;
  83. int_status = readl(&cdns_i2c->interrupt_status);
  84. status = readl(&cdns_i2c->status);
  85. if (int_status || status) {
  86. debug("Status: ");
  87. if (int_status & CDNS_I2C_INTERRUPT_COMP)
  88. debug("COMP ");
  89. if (int_status & CDNS_I2C_INTERRUPT_DATA)
  90. debug("DATA ");
  91. if (int_status & CDNS_I2C_INTERRUPT_NACK)
  92. debug("NACK ");
  93. if (int_status & CDNS_I2C_INTERRUPT_TO)
  94. debug("TO ");
  95. if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
  96. debug("SLVRDY ");
  97. if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
  98. debug("RXOVF ");
  99. if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
  100. debug("TXOVF ");
  101. if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
  102. debug("RXUNF ");
  103. if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
  104. debug("ARBLOST ");
  105. if (status & CDNS_I2C_STATUS_RXDV)
  106. debug("RXDV ");
  107. if (status & CDNS_I2C_STATUS_TXDV)
  108. debug("TXDV ");
  109. if (status & CDNS_I2C_STATUS_RXOVF)
  110. debug("RXOVF ");
  111. if (status & CDNS_I2C_STATUS_BA)
  112. debug("BA ");
  113. debug("TS%d ", readl(&cdns_i2c->transfer_size));
  114. debug("\n");
  115. }
  116. }
  117. #endif
  118. struct i2c_cdns_bus {
  119. int id;
  120. unsigned int input_freq;
  121. struct cdns_i2c_regs __iomem *regs; /* register base */
  122. int hold_flag;
  123. u32 quirks;
  124. };
  125. struct cdns_i2c_platform_data {
  126. u32 quirks;
  127. };
  128. /* Wait for an interrupt */
  129. static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
  130. {
  131. int timeout, int_status;
  132. for (timeout = 0; timeout < 100; timeout++) {
  133. int_status = readl(&cdns_i2c->interrupt_status);
  134. if (int_status & mask)
  135. break;
  136. udelay(100);
  137. }
  138. /* Clear interrupt status flags */
  139. writel(int_status & mask, &cdns_i2c->interrupt_status);
  140. return int_status & mask;
  141. }
  142. #define CDNS_I2C_DIVA_MAX 4
  143. #define CDNS_I2C_DIVB_MAX 64
  144. static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
  145. unsigned int *a, unsigned int *b)
  146. {
  147. unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
  148. unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
  149. unsigned int last_error, current_error;
  150. /* calculate (divisor_a+1) x (divisor_b+1) */
  151. temp = input_clk / (22 * fscl);
  152. /*
  153. * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
  154. * the fscl input is out of range. Return error.
  155. */
  156. if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
  157. return -EINVAL;
  158. last_error = -1;
  159. for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
  160. div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
  161. if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
  162. continue;
  163. div_b--;
  164. actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
  165. if (actual_fscl > fscl)
  166. continue;
  167. current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
  168. (fscl - actual_fscl));
  169. if (last_error > current_error) {
  170. calc_div_a = div_a;
  171. calc_div_b = div_b;
  172. best_fscl = actual_fscl;
  173. last_error = current_error;
  174. }
  175. }
  176. *a = calc_div_a;
  177. *b = calc_div_b;
  178. *f = best_fscl;
  179. return 0;
  180. }
  181. static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  182. {
  183. struct i2c_cdns_bus *bus = dev_get_priv(dev);
  184. u32 div_a = 0, div_b = 0;
  185. unsigned long speed_p = speed;
  186. int ret = 0;
  187. if (speed > I2C_SPEED_FAST_RATE) {
  188. debug("%s, failed to set clock speed to %u\n", __func__,
  189. speed);
  190. return -EINVAL;
  191. }
  192. ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
  193. if (ret)
  194. return ret;
  195. debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
  196. __func__, div_a, div_b, bus->input_freq, speed, speed_p);
  197. writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
  198. (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
  199. /* Enable master mode, ack, and 7-bit addressing */
  200. setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
  201. CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
  202. return 0;
  203. }
  204. static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
  205. {
  206. return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
  207. }
  208. static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
  209. u32 len)
  210. {
  211. u8 *cur_data = data;
  212. struct cdns_i2c_regs *regs = i2c_bus->regs;
  213. u32 ret;
  214. /* Set the controller in Master transmit mode and clear FIFO */
  215. setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
  216. clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
  217. /* Check message size against FIFO depth, and set hold bus bit
  218. * if it is greater than FIFO depth
  219. */
  220. if (len > CDNS_I2C_FIFO_DEPTH)
  221. setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  222. /* Clear the interrupts in status register */
  223. writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
  224. writel(addr, &regs->address);
  225. while (len-- && !is_arbitration_lost(regs)) {
  226. writel(*(cur_data++), &regs->data);
  227. if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
  228. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  229. CDNS_I2C_INTERRUPT_ARBLOST);
  230. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  231. return -EAGAIN;
  232. if (ret & CDNS_I2C_INTERRUPT_COMP)
  233. continue;
  234. /* Release the bus */
  235. clrbits_le32(&regs->control,
  236. CDNS_I2C_CONTROL_HOLD);
  237. return -ETIMEDOUT;
  238. }
  239. }
  240. if (len && is_arbitration_lost(regs))
  241. return -EAGAIN;
  242. /* All done... release the bus */
  243. if (!i2c_bus->hold_flag)
  244. clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  245. /* Wait for the address and data to be sent */
  246. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  247. CDNS_I2C_INTERRUPT_ARBLOST);
  248. if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
  249. CDNS_I2C_INTERRUPT_COMP)))
  250. return -ETIMEDOUT;
  251. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  252. return -EAGAIN;
  253. return 0;
  254. }
  255. static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
  256. {
  257. return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
  258. }
  259. static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
  260. u32 recv_count)
  261. {
  262. u8 *cur_data = data;
  263. struct cdns_i2c_regs *regs = i2c_bus->regs;
  264. u32 curr_recv_count;
  265. int updatetx, hold_quirk;
  266. u32 ret;
  267. curr_recv_count = recv_count;
  268. /* Check for the message size against the FIFO depth */
  269. if (recv_count > CDNS_I2C_FIFO_DEPTH)
  270. setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  271. setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
  272. CDNS_I2C_CONTROL_RW);
  273. if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
  274. curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
  275. writel(curr_recv_count, &regs->transfer_size);
  276. } else {
  277. writel(recv_count, &regs->transfer_size);
  278. }
  279. /* Start reading data */
  280. writel(addr, &regs->address);
  281. updatetx = recv_count > curr_recv_count;
  282. hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
  283. while (recv_count && !is_arbitration_lost(regs)) {
  284. while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
  285. if (recv_count < CDNS_I2C_FIFO_DEPTH &&
  286. !i2c_bus->hold_flag) {
  287. clrbits_le32(&regs->control,
  288. CDNS_I2C_CONTROL_HOLD);
  289. }
  290. *(cur_data)++ = readl(&regs->data);
  291. recv_count--;
  292. curr_recv_count--;
  293. if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
  294. break;
  295. }
  296. if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
  297. /* wait while fifo is full */
  298. while (readl(&regs->transfer_size) !=
  299. (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
  300. ;
  301. /*
  302. * Check number of bytes to be received against maximum
  303. * transfer size and update register accordingly.
  304. */
  305. if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
  306. CDNS_I2C_TRANSFER_SIZE) {
  307. writel(CDNS_I2C_TRANSFER_SIZE,
  308. &regs->transfer_size);
  309. curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
  310. CDNS_I2C_FIFO_DEPTH;
  311. } else {
  312. writel(recv_count - CDNS_I2C_FIFO_DEPTH,
  313. &regs->transfer_size);
  314. curr_recv_count = recv_count;
  315. }
  316. } else if (recv_count && !hold_quirk && !curr_recv_count) {
  317. writel(addr, &regs->address);
  318. if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
  319. writel(CDNS_I2C_TRANSFER_SIZE,
  320. &regs->transfer_size);
  321. curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
  322. } else {
  323. writel(recv_count, &regs->transfer_size);
  324. curr_recv_count = recv_count;
  325. }
  326. }
  327. }
  328. /* Wait for the address and data to be sent */
  329. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  330. CDNS_I2C_INTERRUPT_ARBLOST);
  331. if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
  332. CDNS_I2C_INTERRUPT_COMP)))
  333. return -ETIMEDOUT;
  334. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  335. return -EAGAIN;
  336. return 0;
  337. }
  338. static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  339. int nmsgs)
  340. {
  341. struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
  342. int ret = 0;
  343. int count;
  344. bool hold_quirk;
  345. struct i2c_msg *message = msg;
  346. int num_msgs = nmsgs;
  347. hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
  348. if (nmsgs > 1) {
  349. /*
  350. * This controller does not give completion interrupt after a
  351. * master receive message if HOLD bit is set (repeated start),
  352. * resulting in SW timeout. Hence, if a receive message is
  353. * followed by any other message, an error is returned
  354. * indicating that this sequence is not supported.
  355. */
  356. for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
  357. if (msg[count].flags & I2C_M_RD) {
  358. printf("Can't do repeated start after a receive message\n");
  359. return -EOPNOTSUPP;
  360. }
  361. }
  362. i2c_bus->hold_flag = 1;
  363. setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
  364. } else {
  365. i2c_bus->hold_flag = 0;
  366. }
  367. debug("i2c_xfer: %d messages\n", nmsgs);
  368. for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
  369. nmsgs > 0; nmsgs--, msg++) {
  370. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  371. if (msg->flags & I2C_M_RD) {
  372. ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
  373. msg->len);
  374. } else {
  375. ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
  376. msg->len);
  377. }
  378. if (ret == -EAGAIN) {
  379. msg = message;
  380. nmsgs = num_msgs;
  381. retry++;
  382. printf("%s,arbitration lost, retrying:%d\n", __func__,
  383. retry);
  384. continue;
  385. }
  386. if (ret) {
  387. debug("i2c_write: error sending\n");
  388. return -EREMOTEIO;
  389. }
  390. }
  391. return ret;
  392. }
  393. static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
  394. {
  395. struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
  396. struct cdns_i2c_platform_data *pdata =
  397. (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
  398. struct clk clk;
  399. int ret;
  400. i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
  401. if (!i2c_bus->regs)
  402. return -ENOMEM;
  403. if (pdata)
  404. i2c_bus->quirks = pdata->quirks;
  405. ret = clk_get_by_index(dev, 0, &clk);
  406. if (ret)
  407. return ret;
  408. i2c_bus->input_freq = clk_get_rate(&clk);
  409. return 0;
  410. }
  411. static const struct dm_i2c_ops cdns_i2c_ops = {
  412. .xfer = cdns_i2c_xfer,
  413. .set_bus_speed = cdns_i2c_set_bus_speed,
  414. };
  415. static const struct cdns_i2c_platform_data r1p10_i2c_def = {
  416. .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
  417. };
  418. static const struct udevice_id cdns_i2c_of_match[] = {
  419. { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
  420. { .compatible = "cdns,i2c-r1p14" },
  421. { /* end of table */ }
  422. };
  423. U_BOOT_DRIVER(cdns_i2c) = {
  424. .name = "i2c_cdns",
  425. .id = UCLASS_I2C,
  426. .of_match = cdns_i2c_of_match,
  427. .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
  428. .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
  429. .ops = &cdns_i2c_ops,
  430. };