clk_zynqmp.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ZynqMP clock driver
  4. *
  5. * Copyright (C) 2016 Xilinx, Inc.
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/bitops.h>
  12. #include <clk-uclass.h>
  13. #include <clk.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <dm.h>
  16. #include <linux/err.h>
  17. static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  18. static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  19. /* Full power domain clocks */
  20. #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
  21. #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
  22. #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
  23. #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
  24. #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
  25. #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
  26. #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
  27. /* Peripheral clocks */
  28. #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
  29. #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
  30. #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
  31. #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
  32. #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
  33. #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
  34. #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
  35. #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
  36. #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
  37. #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
  38. #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
  39. #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
  40. #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
  41. #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
  42. #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
  43. #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
  44. /* Low power domain clocks */
  45. #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
  46. #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
  47. #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
  48. #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
  49. #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
  50. /* Peripheral clocks */
  51. #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
  52. #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
  53. #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
  54. #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
  55. #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
  56. #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
  57. #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
  58. #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
  59. #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
  60. #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
  61. #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
  62. #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
  63. #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
  64. #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
  65. #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
  66. #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
  67. #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
  68. #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
  69. #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
  70. #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
  71. #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
  72. #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
  73. #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
  74. #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
  75. #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
  76. #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
  77. #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
  78. #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
  79. #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
  80. #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
  81. #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
  82. #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
  83. #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
  84. #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
  85. #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
  86. #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
  87. #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
  88. #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
  89. #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
  90. #define ZYNQ_CLK_MAXDIV 0x3f
  91. #define CLK_CTRL_DIV1_SHIFT 16
  92. #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  93. #define CLK_CTRL_DIV0_SHIFT 8
  94. #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  95. #define CLK_CTRL_SRCSEL_SHIFT 0
  96. #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  97. #define PLLCTRL_FBDIV_MASK 0x7f00
  98. #define PLLCTRL_FBDIV_SHIFT 8
  99. #define PLLCTRL_RESET_MASK 1
  100. #define PLLCTRL_RESET_SHIFT 0
  101. #define PLLCTRL_BYPASS_MASK 0x8
  102. #define PLLCTRL_BYPASS_SHFT 3
  103. #define PLLCTRL_POST_SRC_SHFT 24
  104. #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
  105. #define PLLCTRL_PRE_SRC_SHFT 20
  106. #define PLLCTRL_PRE_SRC_MASK (0x7 << PLLCTRL_PRE_SRC_SHFT)
  107. #define NUM_MIO_PINS 77
  108. enum zynqmp_clk {
  109. iopll, rpll,
  110. apll, dpll, vpll,
  111. iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
  112. acpu, acpu_half,
  113. dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
  114. dp_video_ref, dp_audio_ref,
  115. dp_stc_ref, gdma_ref, dpdma_ref,
  116. ddr_ref, sata_ref, pcie_ref,
  117. gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
  118. topsw_main, topsw_lsbus,
  119. gtgref0_ref,
  120. lpd_switch, lpd_lsbus,
  121. usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
  122. cpu_r5, cpu_r5_core,
  123. csu_spb, csu_pll, pcap,
  124. iou_switch,
  125. gem_tsu_ref, gem_tsu,
  126. gem0_ref, gem1_ref, gem2_ref, gem3_ref,
  127. gem0_rx, gem1_rx, gem2_rx, gem3_rx,
  128. qspi_ref,
  129. sdio0_ref, sdio1_ref,
  130. uart0_ref, uart1_ref,
  131. spi0_ref, spi1_ref,
  132. nand_ref,
  133. i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
  134. dll_ref,
  135. adma_ref,
  136. timestamp_ref,
  137. ams_ref,
  138. pl0, pl1, pl2, pl3,
  139. wdt,
  140. clk_max,
  141. };
  142. static const char * const clk_names[clk_max] = {
  143. "iopll", "rpll", "apll", "dpll",
  144. "vpll", "iopll_to_fpd", "rpll_to_fpd",
  145. "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
  146. "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
  147. "dbg_trace", "dbg_tstmp", "dp_video_ref",
  148. "dp_audio_ref", "dp_stc_ref", "gdma_ref",
  149. "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
  150. "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
  151. "topsw_main", "topsw_lsbus", "gtgref0_ref",
  152. "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
  153. "usb1_bus_ref", "usb3_dual_ref", "usb0",
  154. "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
  155. "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
  156. "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
  157. "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
  158. "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
  159. "uart0_ref", "uart1_ref", "spi0_ref",
  160. "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
  161. "can0_ref", "can1_ref", "can0", "can1",
  162. "dll_ref", "adma_ref", "timestamp_ref",
  163. "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
  164. };
  165. struct zynqmp_clk_priv {
  166. unsigned long ps_clk_freq;
  167. unsigned long video_clk;
  168. unsigned long pss_alt_ref_clk;
  169. unsigned long gt_crx_ref_clk;
  170. unsigned long aux_ref_clk;
  171. };
  172. static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
  173. {
  174. switch (id) {
  175. case iopll:
  176. return CRL_APB_IOPLL_CTRL;
  177. case rpll:
  178. return CRL_APB_RPLL_CTRL;
  179. case apll:
  180. return CRF_APB_APLL_CTRL;
  181. case dpll:
  182. return CRF_APB_DPLL_CTRL;
  183. case vpll:
  184. return CRF_APB_VPLL_CTRL;
  185. case acpu:
  186. return CRF_APB_ACPU_CTRL;
  187. case ddr_ref:
  188. return CRF_APB_DDR_CTRL;
  189. case qspi_ref:
  190. return CRL_APB_QSPI_REF_CTRL;
  191. case gem0_ref:
  192. return CRL_APB_GEM0_REF_CTRL;
  193. case gem1_ref:
  194. return CRL_APB_GEM1_REF_CTRL;
  195. case gem2_ref:
  196. return CRL_APB_GEM2_REF_CTRL;
  197. case gem3_ref:
  198. return CRL_APB_GEM3_REF_CTRL;
  199. case uart0_ref:
  200. return CRL_APB_UART0_REF_CTRL;
  201. case uart1_ref:
  202. return CRL_APB_UART1_REF_CTRL;
  203. case sdio0_ref:
  204. return CRL_APB_SDIO0_REF_CTRL;
  205. case sdio1_ref:
  206. return CRL_APB_SDIO1_REF_CTRL;
  207. case spi0_ref:
  208. return CRL_APB_SPI0_REF_CTRL;
  209. case spi1_ref:
  210. return CRL_APB_SPI1_REF_CTRL;
  211. case nand_ref:
  212. return CRL_APB_NAND_REF_CTRL;
  213. case i2c0_ref:
  214. return CRL_APB_I2C0_REF_CTRL;
  215. case i2c1_ref:
  216. return CRL_APB_I2C1_REF_CTRL;
  217. case can0_ref:
  218. return CRL_APB_CAN0_REF_CTRL;
  219. case can1_ref:
  220. return CRL_APB_CAN1_REF_CTRL;
  221. case pl0:
  222. return CRL_APB_PL0_REF_CTRL;
  223. case pl1:
  224. return CRL_APB_PL1_REF_CTRL;
  225. case pl2:
  226. return CRL_APB_PL2_REF_CTRL;
  227. case pl3:
  228. return CRL_APB_PL3_REF_CTRL;
  229. case wdt:
  230. return CRF_APB_TOPSW_LSBUS_CTRL;
  231. case iopll_to_fpd:
  232. return CRL_APB_IOPLL_TO_FPD_CTRL;
  233. default:
  234. debug("Invalid clk id%d\n", id);
  235. }
  236. return 0;
  237. }
  238. static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
  239. {
  240. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  241. CLK_CTRL_SRCSEL_SHIFT;
  242. switch (srcsel) {
  243. case 2:
  244. return dpll;
  245. case 3:
  246. return vpll;
  247. case 0 ... 1:
  248. default:
  249. return apll;
  250. }
  251. }
  252. static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
  253. {
  254. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  255. CLK_CTRL_SRCSEL_SHIFT;
  256. switch (srcsel) {
  257. case 1:
  258. return vpll;
  259. case 0:
  260. default:
  261. return dpll;
  262. }
  263. }
  264. static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
  265. {
  266. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  267. CLK_CTRL_SRCSEL_SHIFT;
  268. switch (srcsel) {
  269. case 2:
  270. return rpll;
  271. case 3:
  272. return dpll;
  273. case 0 ... 1:
  274. default:
  275. return iopll;
  276. }
  277. }
  278. static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
  279. {
  280. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  281. CLK_CTRL_SRCSEL_SHIFT;
  282. switch (srcsel) {
  283. case 2:
  284. return iopll_to_fpd;
  285. case 3:
  286. return dpll;
  287. case 0 ... 1:
  288. default:
  289. return apll;
  290. }
  291. }
  292. static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
  293. struct zynqmp_clk_priv *priv,
  294. bool is_pre_src)
  295. {
  296. u32 src_sel;
  297. if (is_pre_src)
  298. src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
  299. PLLCTRL_PRE_SRC_SHFT;
  300. else
  301. src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
  302. PLLCTRL_POST_SRC_SHFT;
  303. switch (src_sel) {
  304. case 4:
  305. return priv->video_clk;
  306. case 5:
  307. return priv->pss_alt_ref_clk;
  308. case 6:
  309. return priv->aux_ref_clk;
  310. case 7:
  311. return priv->gt_crx_ref_clk;
  312. case 0 ... 3:
  313. default:
  314. return priv->ps_clk_freq;
  315. }
  316. }
  317. static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
  318. enum zynqmp_clk id)
  319. {
  320. u32 clk_ctrl, reset, mul;
  321. ulong freq;
  322. int ret;
  323. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  324. if (ret) {
  325. printf("%s mio read fail\n", __func__);
  326. return -EIO;
  327. }
  328. if (clk_ctrl & PLLCTRL_BYPASS_MASK)
  329. freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
  330. else
  331. freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
  332. reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
  333. if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
  334. return 0;
  335. mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
  336. freq *= mul;
  337. if (clk_ctrl & (1 << 16))
  338. freq /= 2;
  339. return freq;
  340. }
  341. static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
  342. enum zynqmp_clk id)
  343. {
  344. u32 clk_ctrl, div;
  345. enum zynqmp_clk pll;
  346. int ret;
  347. unsigned long pllrate;
  348. ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
  349. if (ret) {
  350. printf("%s mio read fail\n", __func__);
  351. return -EIO;
  352. }
  353. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  354. pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
  355. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  356. if (IS_ERR_VALUE(pllrate))
  357. return pllrate;
  358. return DIV_ROUND_CLOSEST(pllrate, div);
  359. }
  360. static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
  361. {
  362. u32 clk_ctrl, div;
  363. enum zynqmp_clk pll;
  364. int ret;
  365. ulong pllrate;
  366. ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
  367. if (ret) {
  368. printf("%s mio read fail\n", __func__);
  369. return -EIO;
  370. }
  371. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  372. pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
  373. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  374. if (IS_ERR_VALUE(pllrate))
  375. return pllrate;
  376. return DIV_ROUND_CLOSEST(pllrate, div);
  377. }
  378. static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
  379. enum zynqmp_clk id, bool two_divs)
  380. {
  381. enum zynqmp_clk pll;
  382. u32 clk_ctrl, div0;
  383. u32 div1 = 1;
  384. int ret;
  385. ulong pllrate;
  386. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  387. if (ret) {
  388. printf("%s mio read fail\n", __func__);
  389. return -EIO;
  390. }
  391. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  392. if (!div0)
  393. div0 = 1;
  394. if (two_divs) {
  395. div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
  396. if (!div1)
  397. div1 = 1;
  398. }
  399. pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
  400. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  401. if (IS_ERR_VALUE(pllrate))
  402. return pllrate;
  403. return
  404. DIV_ROUND_CLOSEST(
  405. DIV_ROUND_CLOSEST(pllrate, div0), div1);
  406. }
  407. static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
  408. enum zynqmp_clk id, bool two_divs)
  409. {
  410. enum zynqmp_clk pll;
  411. u32 clk_ctrl, div0;
  412. u32 div1 = 1;
  413. int ret;
  414. ulong pllrate;
  415. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  416. if (ret) {
  417. printf("%d %s mio read fail\n", __LINE__, __func__);
  418. return -EIO;
  419. }
  420. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  421. if (!div0)
  422. div0 = 1;
  423. pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
  424. if (two_divs) {
  425. ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
  426. if (ret) {
  427. printf("%d %s mio read fail\n", __LINE__, __func__);
  428. return -EIO;
  429. }
  430. div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  431. if (!div1)
  432. div1 = 1;
  433. }
  434. if (pll == iopll_to_fpd)
  435. pll = iopll;
  436. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  437. if (IS_ERR_VALUE(pllrate))
  438. return pllrate;
  439. return
  440. DIV_ROUND_CLOSEST(
  441. DIV_ROUND_CLOSEST(pllrate, div0), div1);
  442. }
  443. static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
  444. ulong pll_rate,
  445. u32 *div0, u32 *div1)
  446. {
  447. long new_err, best_err = (long)(~0UL >> 1);
  448. ulong new_rate, best_rate = 0;
  449. u32 d0, d1;
  450. for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
  451. for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
  452. new_rate = DIV_ROUND_CLOSEST(
  453. DIV_ROUND_CLOSEST(pll_rate, d0), d1);
  454. new_err = abs(new_rate - rate);
  455. if (new_err < best_err) {
  456. *div0 = d0;
  457. *div1 = d1;
  458. best_err = new_err;
  459. best_rate = new_rate;
  460. }
  461. }
  462. }
  463. return best_rate;
  464. }
  465. static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
  466. enum zynqmp_clk id, ulong rate,
  467. bool two_divs)
  468. {
  469. enum zynqmp_clk pll;
  470. u32 clk_ctrl, div0 = 0, div1 = 0;
  471. ulong pll_rate, new_rate;
  472. u32 reg;
  473. int ret;
  474. u32 mask;
  475. reg = zynqmp_clk_get_register(id);
  476. ret = zynqmp_mmio_read(reg, &clk_ctrl);
  477. if (ret) {
  478. printf("%s mio read fail\n", __func__);
  479. return -EIO;
  480. }
  481. pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
  482. pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
  483. if (IS_ERR_VALUE(pll_rate))
  484. return pll_rate;
  485. clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
  486. if (two_divs) {
  487. clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
  488. new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
  489. &div0, &div1);
  490. clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
  491. } else {
  492. div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
  493. if (div0 > ZYNQ_CLK_MAXDIV)
  494. div0 = ZYNQ_CLK_MAXDIV;
  495. new_rate = DIV_ROUND_CLOSEST(rate, div0);
  496. }
  497. clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
  498. mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
  499. (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
  500. ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
  501. if (ret) {
  502. printf("%s mio write fail\n", __func__);
  503. return -EIO;
  504. }
  505. return new_rate;
  506. }
  507. static ulong zynqmp_clk_get_rate(struct clk *clk)
  508. {
  509. struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
  510. enum zynqmp_clk id = clk->id;
  511. bool two_divs = false;
  512. switch (id) {
  513. case iopll ... vpll:
  514. return zynqmp_clk_get_pll_rate(priv, id);
  515. case acpu:
  516. return zynqmp_clk_get_cpu_rate(priv, id);
  517. case ddr_ref:
  518. return zynqmp_clk_get_ddr_rate(priv);
  519. case gem0_ref ... gem3_ref:
  520. case qspi_ref ... can1_ref:
  521. case pl0 ... pl3:
  522. two_divs = true;
  523. return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
  524. case wdt:
  525. two_divs = true;
  526. return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
  527. default:
  528. return -ENXIO;
  529. }
  530. }
  531. static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
  532. {
  533. struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
  534. enum zynqmp_clk id = clk->id;
  535. bool two_divs = true;
  536. switch (id) {
  537. case gem0_ref ... gem3_ref:
  538. case qspi_ref ... can1_ref:
  539. return zynqmp_clk_set_peripheral_rate(priv, id,
  540. rate, two_divs);
  541. default:
  542. return -ENXIO;
  543. }
  544. }
  545. int soc_clk_dump(void)
  546. {
  547. struct udevice *dev;
  548. int i, ret;
  549. ret = uclass_get_device_by_driver(UCLASS_CLK,
  550. DM_GET_DRIVER(zynqmp_clk), &dev);
  551. if (ret)
  552. return ret;
  553. printf("clk\t\tfrequency\n");
  554. for (i = 0; i < clk_max; i++) {
  555. const char *name = clk_names[i];
  556. if (name) {
  557. struct clk clk;
  558. unsigned long rate;
  559. clk.id = i;
  560. ret = clk_request(dev, &clk);
  561. if (ret < 0)
  562. return ret;
  563. rate = clk_get_rate(&clk);
  564. clk_free(&clk);
  565. if ((rate == (unsigned long)-ENOSYS) ||
  566. (rate == (unsigned long)-ENXIO) ||
  567. (rate == (unsigned long)-EIO))
  568. printf("%10s%20s\n", name, "unknown");
  569. else
  570. printf("%10s%20lu\n", name, rate);
  571. }
  572. }
  573. return 0;
  574. }
  575. static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
  576. {
  577. struct clk clk;
  578. int ret;
  579. ret = clk_get_by_name(dev, name, &clk);
  580. if (ret < 0) {
  581. dev_err(dev, "failed to get %s\n", name);
  582. return ret;
  583. }
  584. *freq = clk_get_rate(&clk);
  585. if (IS_ERR_VALUE(*freq)) {
  586. dev_err(dev, "failed to get rate %s\n", name);
  587. return -EINVAL;
  588. }
  589. return 0;
  590. }
  591. static int zynqmp_clk_probe(struct udevice *dev)
  592. {
  593. int ret;
  594. struct zynqmp_clk_priv *priv = dev_get_priv(dev);
  595. debug("%s\n", __func__);
  596. ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
  597. if (ret < 0)
  598. return -EINVAL;
  599. ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
  600. if (ret < 0)
  601. return -EINVAL;
  602. ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
  603. &priv->pss_alt_ref_clk);
  604. if (ret < 0)
  605. return -EINVAL;
  606. ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
  607. if (ret < 0)
  608. return -EINVAL;
  609. ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
  610. &priv->gt_crx_ref_clk);
  611. if (ret < 0)
  612. return -EINVAL;
  613. return 0;
  614. }
  615. static struct clk_ops zynqmp_clk_ops = {
  616. .set_rate = zynqmp_clk_set_rate,
  617. .get_rate = zynqmp_clk_get_rate,
  618. };
  619. static const struct udevice_id zynqmp_clk_ids[] = {
  620. { .compatible = "xlnx,zynqmp-clk" },
  621. { }
  622. };
  623. U_BOOT_DRIVER(zynqmp_clk) = {
  624. .name = "zynqmp_clk",
  625. .id = UCLASS_CLK,
  626. .of_match = zynqmp_clk_ids,
  627. .probe = zynqmp_clk_probe,
  628. .ops = &zynqmp_clk_ops,
  629. .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
  630. };