sunxi_display.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Display driver for Allwinner SoCs.
  4. *
  5. * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
  6. * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <efi_loader.h>
  11. #include <init.h>
  12. #include <time.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/display.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/lcdc.h>
  17. #include <asm/arch/pwm.h>
  18. #include <asm/arch/tve.h>
  19. #include <asm/global_data.h>
  20. #include <asm/gpio.h>
  21. #include <asm/io.h>
  22. #include <axp_pmic.h>
  23. #include <errno.h>
  24. #include <fdtdec.h>
  25. #include <fdt_support.h>
  26. #include <i2c.h>
  27. #include <malloc.h>
  28. #include <video_fb.h>
  29. #include "../videomodes.h"
  30. #include "../anx9804.h"
  31. #include "../hitachi_tx18d42vm_lcd.h"
  32. #include "../ssd2828.h"
  33. #include "simplefb_common.h"
  34. #ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
  35. #define PWM_ON 0
  36. #define PWM_OFF 1
  37. #else
  38. #define PWM_ON 1
  39. #define PWM_OFF 0
  40. #endif
  41. DECLARE_GLOBAL_DATA_PTR;
  42. enum sunxi_monitor {
  43. sunxi_monitor_none,
  44. sunxi_monitor_dvi,
  45. sunxi_monitor_hdmi,
  46. sunxi_monitor_lcd,
  47. sunxi_monitor_vga,
  48. sunxi_monitor_composite_pal,
  49. sunxi_monitor_composite_ntsc,
  50. sunxi_monitor_composite_pal_m,
  51. sunxi_monitor_composite_pal_nc,
  52. };
  53. #define SUNXI_MONITOR_LAST sunxi_monitor_composite_pal_nc
  54. struct sunxi_display {
  55. GraphicDevice graphic_device;
  56. enum sunxi_monitor monitor;
  57. unsigned int depth;
  58. unsigned int fb_addr;
  59. unsigned int fb_size;
  60. } sunxi_display;
  61. const struct ctfb_res_modes composite_video_modes[2] = {
  62. /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */
  63. { 720, 576, 50, 37037, 27000, 137, 5, 20, 27, 2, 2, 0, FB_VMODE_INTERLACED },
  64. { 720, 480, 60, 37037, 27000, 116, 20, 16, 27, 2, 2, 0, FB_VMODE_INTERLACED },
  65. };
  66. #ifdef CONFIG_VIDEO_HDMI
  67. /*
  68. * Wait up to 200ms for value to be set in given part of reg.
  69. */
  70. static int await_completion(u32 *reg, u32 mask, u32 val)
  71. {
  72. unsigned long tmo = timer_get_us() + 200000;
  73. while ((readl(reg) & mask) != val) {
  74. if (timer_get_us() > tmo) {
  75. printf("DDC: timeout reading EDID\n");
  76. return -ETIME;
  77. }
  78. }
  79. return 0;
  80. }
  81. static int sunxi_hdmi_hpd_detect(int hpd_delay)
  82. {
  83. struct sunxi_ccm_reg * const ccm =
  84. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  85. struct sunxi_hdmi_reg * const hdmi =
  86. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  87. unsigned long tmo = timer_get_us() + hpd_delay * 1000;
  88. /* Set pll3 to 300MHz */
  89. clock_set_pll3(300000000);
  90. /* Set hdmi parent to pll3 */
  91. clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  92. CCM_HDMI_CTRL_PLL3);
  93. /* Set ahb gating to pass */
  94. #ifdef CONFIG_SUNXI_GEN_SUN6I
  95. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  96. #endif
  97. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  98. /* Clock on */
  99. setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  100. writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  101. writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  102. /* Enable PLLs for eventual DDC */
  103. writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
  104. &hdmi->pad_ctrl1);
  105. writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
  106. &hdmi->pll_ctrl);
  107. writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
  108. while (timer_get_us() < tmo) {
  109. if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  110. return 1;
  111. }
  112. return 0;
  113. }
  114. static void sunxi_hdmi_shutdown(void)
  115. {
  116. struct sunxi_ccm_reg * const ccm =
  117. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  118. struct sunxi_hdmi_reg * const hdmi =
  119. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  120. clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  121. clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  122. clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  123. #ifdef CONFIG_SUNXI_GEN_SUN6I
  124. clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  125. #endif
  126. clock_set_pll3(0);
  127. }
  128. static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
  129. {
  130. struct sunxi_hdmi_reg * const hdmi =
  131. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  132. setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
  133. writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
  134. SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
  135. SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
  136. SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
  137. #ifndef CONFIG_MACH_SUN6I
  138. writel(n, &hdmi->ddc_byte_count);
  139. writel(cmnd, &hdmi->ddc_cmnd);
  140. #else
  141. writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
  142. #endif
  143. setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
  144. return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
  145. }
  146. static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
  147. {
  148. struct sunxi_hdmi_reg * const hdmi =
  149. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  150. int i, n;
  151. while (count > 0) {
  152. if (count > 16)
  153. n = 16;
  154. else
  155. n = count;
  156. if (sunxi_hdmi_ddc_do_command(
  157. SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
  158. offset, n))
  159. return -ETIME;
  160. for (i = 0; i < n; i++)
  161. *buf++ = readb(&hdmi->ddc_fifo_data);
  162. offset += n;
  163. count -= n;
  164. }
  165. return 0;
  166. }
  167. static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
  168. {
  169. int r, retries = 2;
  170. do {
  171. r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
  172. if (r)
  173. continue;
  174. r = edid_check_checksum(buf);
  175. if (r) {
  176. printf("EDID block %d: checksum error%s\n",
  177. block, retries ? ", retrying" : "");
  178. }
  179. } while (r && retries--);
  180. return r;
  181. }
  182. static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode,
  183. bool verbose_mode)
  184. {
  185. struct edid1_info edid1;
  186. struct edid_cea861_info cea681[4];
  187. struct edid_detailed_timing *t =
  188. (struct edid_detailed_timing *)edid1.monitor_details.timing;
  189. struct sunxi_hdmi_reg * const hdmi =
  190. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  191. struct sunxi_ccm_reg * const ccm =
  192. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  193. int i, r, ext_blocks = 0;
  194. /* Reset i2c controller */
  195. setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
  196. writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
  197. SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
  198. SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
  199. SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
  200. if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
  201. return -EIO;
  202. writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
  203. #ifndef CONFIG_MACH_SUN6I
  204. writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
  205. SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
  206. #endif
  207. r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
  208. if (r == 0) {
  209. r = edid_check_info(&edid1);
  210. if (r) {
  211. if (verbose_mode)
  212. printf("EDID: invalid EDID data\n");
  213. r = -EINVAL;
  214. }
  215. }
  216. if (r == 0) {
  217. ext_blocks = edid1.extension_flag;
  218. if (ext_blocks > 4)
  219. ext_blocks = 4;
  220. for (i = 0; i < ext_blocks; i++) {
  221. if (sunxi_hdmi_edid_get_block(1 + i,
  222. (u8 *)&cea681[i]) != 0) {
  223. ext_blocks = i;
  224. break;
  225. }
  226. }
  227. }
  228. /* Disable DDC engine, no longer needed */
  229. clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
  230. clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
  231. if (r)
  232. return r;
  233. /* We want version 1.3 or 1.2 with detailed timing info */
  234. if (edid1.version != 1 || (edid1.revision < 3 &&
  235. !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
  236. printf("EDID: unsupported version %d.%d\n",
  237. edid1.version, edid1.revision);
  238. return -EINVAL;
  239. }
  240. /* Take the first usable detailed timing */
  241. for (i = 0; i < 4; i++, t++) {
  242. r = video_edid_dtd_to_ctfb_res_modes(t, mode);
  243. if (r == 0)
  244. break;
  245. }
  246. if (i == 4) {
  247. printf("EDID: no usable detailed timing found\n");
  248. return -ENOENT;
  249. }
  250. /* Check for basic audio support, if found enable hdmi output */
  251. sunxi_display.monitor = sunxi_monitor_dvi;
  252. for (i = 0; i < ext_blocks; i++) {
  253. if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
  254. cea681[i].revision < 2)
  255. continue;
  256. if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
  257. sunxi_display.monitor = sunxi_monitor_hdmi;
  258. }
  259. return 0;
  260. }
  261. #endif /* CONFIG_VIDEO_HDMI */
  262. #ifdef CONFIG_MACH_SUN4I
  263. /*
  264. * Testing has shown that on sun4i the display backend engine does not have
  265. * deep enough fifo-s causing flickering / tearing in full-hd mode due to
  266. * fifo underruns. So on sun4i we use the display frontend engine to do the
  267. * dma from memory, as the frontend does have deep enough fifo-s.
  268. */
  269. static const u32 sun4i_vert_coef[32] = {
  270. 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
  271. 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
  272. 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
  273. 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
  274. 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
  275. 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
  276. 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
  277. 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
  278. };
  279. static const u32 sun4i_horz_coef[64] = {
  280. 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
  281. 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
  282. 0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
  283. 0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
  284. 0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
  285. 0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
  286. 0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
  287. 0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
  288. 0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
  289. 0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
  290. 0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
  291. 0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
  292. 0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
  293. 0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
  294. 0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
  295. 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
  296. };
  297. static void sunxi_frontend_init(void)
  298. {
  299. struct sunxi_ccm_reg * const ccm =
  300. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  301. struct sunxi_de_fe_reg * const de_fe =
  302. (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
  303. int i;
  304. /* Clocks on */
  305. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0);
  306. setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0);
  307. clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000);
  308. setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN);
  309. for (i = 0; i < 32; i++) {
  310. writel(sun4i_horz_coef[2 * i], &de_fe->ch0_horzcoef0[i]);
  311. writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch0_horzcoef1[i]);
  312. writel(sun4i_vert_coef[i], &de_fe->ch0_vertcoef[i]);
  313. writel(sun4i_horz_coef[2 * i], &de_fe->ch1_horzcoef0[i]);
  314. writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch1_horzcoef1[i]);
  315. writel(sun4i_vert_coef[i], &de_fe->ch1_vertcoef[i]);
  316. }
  317. setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY);
  318. }
  319. static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
  320. unsigned int address)
  321. {
  322. struct sunxi_de_fe_reg * const de_fe =
  323. (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
  324. setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
  325. writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
  326. writel(mode->xres * 4, &de_fe->ch0_stride);
  327. writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
  328. writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
  329. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  330. &de_fe->ch0_insize);
  331. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  332. &de_fe->ch0_outsize);
  333. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_horzfact);
  334. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_vertfact);
  335. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  336. &de_fe->ch1_insize);
  337. writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
  338. &de_fe->ch1_outsize);
  339. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_horzfact);
  340. writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_vertfact);
  341. setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY);
  342. }
  343. static void sunxi_frontend_enable(void)
  344. {
  345. struct sunxi_de_fe_reg * const de_fe =
  346. (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
  347. setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START);
  348. }
  349. #else
  350. static void sunxi_frontend_init(void) {}
  351. static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
  352. unsigned int address) {}
  353. static void sunxi_frontend_enable(void) {}
  354. #endif
  355. static bool sunxi_is_composite(void)
  356. {
  357. switch (sunxi_display.monitor) {
  358. case sunxi_monitor_none:
  359. case sunxi_monitor_dvi:
  360. case sunxi_monitor_hdmi:
  361. case sunxi_monitor_lcd:
  362. case sunxi_monitor_vga:
  363. return false;
  364. case sunxi_monitor_composite_pal:
  365. case sunxi_monitor_composite_ntsc:
  366. case sunxi_monitor_composite_pal_m:
  367. case sunxi_monitor_composite_pal_nc:
  368. return true;
  369. }
  370. return false; /* Never reached */
  371. }
  372. /*
  373. * This is the entity that mixes and matches the different layers and inputs.
  374. * Allwinner calls it the back-end, but i like composer better.
  375. */
  376. static void sunxi_composer_init(void)
  377. {
  378. struct sunxi_ccm_reg * const ccm =
  379. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  380. struct sunxi_de_be_reg * const de_be =
  381. (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  382. int i;
  383. sunxi_frontend_init();
  384. #ifdef CONFIG_SUNXI_GEN_SUN6I
  385. /* Reset off */
  386. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
  387. #endif
  388. /* Clocks on */
  389. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
  390. #ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
  391. setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
  392. #endif
  393. clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
  394. /* Engine bug, clear registers after reset */
  395. for (i = 0x0800; i < 0x1000; i += 4)
  396. writel(0, SUNXI_DE_BE0_BASE + i);
  397. setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
  398. }
  399. static const u32 sunxi_rgb2yuv_coef[12] = {
  400. 0x00000107, 0x00000204, 0x00000064, 0x00000108,
  401. 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  402. 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  403. };
  404. static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
  405. unsigned int address)
  406. {
  407. struct sunxi_de_be_reg * const de_be =
  408. (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  409. int i;
  410. sunxi_frontend_mode_set(mode, address);
  411. writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
  412. &de_be->disp_size);
  413. writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
  414. &de_be->layer0_size);
  415. #ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
  416. writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
  417. writel(address << 3, &de_be->layer0_addr_low32b);
  418. writel(address >> 29, &de_be->layer0_addr_high4b);
  419. #else
  420. writel(SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0, &de_be->layer0_attr0_ctrl);
  421. #endif
  422. writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
  423. setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
  424. if (mode->vmode == FB_VMODE_INTERLACED)
  425. setbits_le32(&de_be->mode,
  426. #ifndef CONFIG_MACH_SUN5I
  427. SUNXI_DE_BE_MODE_DEFLICKER_ENABLE |
  428. #endif
  429. SUNXI_DE_BE_MODE_INTERLACE_ENABLE);
  430. if (sunxi_is_composite()) {
  431. writel(SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE,
  432. &de_be->output_color_ctrl);
  433. for (i = 0; i < 12; i++)
  434. writel(sunxi_rgb2yuv_coef[i],
  435. &de_be->output_color_coef[i]);
  436. }
  437. }
  438. static void sunxi_composer_enable(void)
  439. {
  440. struct sunxi_de_be_reg * const de_be =
  441. (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  442. sunxi_frontend_enable();
  443. setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
  444. setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
  445. }
  446. static void sunxi_lcdc_init(void)
  447. {
  448. struct sunxi_ccm_reg * const ccm =
  449. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  450. struct sunxi_lcdc_reg * const lcdc =
  451. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  452. /* Reset off */
  453. #ifdef CONFIG_SUNXI_GEN_SUN6I
  454. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
  455. #else
  456. setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
  457. #endif
  458. /* Clock on */
  459. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
  460. #ifdef CONFIG_VIDEO_LCD_IF_LVDS
  461. #ifdef CONFIG_SUNXI_GEN_SUN6I
  462. setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS);
  463. #else
  464. setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
  465. #endif
  466. #endif
  467. lcdc_init(lcdc);
  468. }
  469. static void sunxi_lcdc_panel_enable(void)
  470. {
  471. int pin, reset_pin;
  472. /*
  473. * Start with backlight disabled to avoid the screen flashing to
  474. * white while the lcd inits.
  475. */
  476. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
  477. if (pin >= 0) {
  478. gpio_request(pin, "lcd_backlight_enable");
  479. gpio_direction_output(pin, 0);
  480. }
  481. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
  482. if (pin >= 0) {
  483. gpio_request(pin, "lcd_backlight_pwm");
  484. gpio_direction_output(pin, PWM_OFF);
  485. }
  486. reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_RESET);
  487. if (reset_pin >= 0) {
  488. gpio_request(reset_pin, "lcd_reset");
  489. gpio_direction_output(reset_pin, 0); /* Assert reset */
  490. }
  491. /* Give the backlight some time to turn off and power up the panel. */
  492. mdelay(40);
  493. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
  494. if (pin >= 0) {
  495. gpio_request(pin, "lcd_power");
  496. gpio_direction_output(pin, 1);
  497. }
  498. if (reset_pin >= 0)
  499. gpio_direction_output(reset_pin, 1); /* De-assert reset */
  500. }
  501. static void sunxi_lcdc_backlight_enable(void)
  502. {
  503. int pin;
  504. /*
  505. * We want to have scanned out at least one frame before enabling the
  506. * backlight to avoid the screen flashing to white when we enable it.
  507. */
  508. mdelay(40);
  509. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
  510. if (pin >= 0)
  511. gpio_direction_output(pin, 1);
  512. pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
  513. #ifdef SUNXI_PWM_PIN0
  514. if (pin == SUNXI_PWM_PIN0) {
  515. writel(SUNXI_PWM_CTRL_POLARITY0(PWM_ON) |
  516. SUNXI_PWM_CTRL_ENABLE0 |
  517. SUNXI_PWM_CTRL_PRESCALE0(0xf), SUNXI_PWM_CTRL_REG);
  518. writel(SUNXI_PWM_PERIOD_80PCT, SUNXI_PWM_CH0_PERIOD);
  519. sunxi_gpio_set_cfgpin(pin, SUNXI_PWM_MUX);
  520. return;
  521. }
  522. #endif
  523. if (pin >= 0)
  524. gpio_direction_output(pin, PWM_ON);
  525. }
  526. static void sunxi_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
  527. struct display_timing *timing)
  528. {
  529. timing->pixelclock.typ = mode->pixclock_khz * 1000;
  530. timing->hactive.typ = mode->xres;
  531. timing->hfront_porch.typ = mode->right_margin;
  532. timing->hback_porch.typ = mode->left_margin;
  533. timing->hsync_len.typ = mode->hsync_len;
  534. timing->vactive.typ = mode->yres;
  535. timing->vfront_porch.typ = mode->lower_margin;
  536. timing->vback_porch.typ = mode->upper_margin;
  537. timing->vsync_len.typ = mode->vsync_len;
  538. timing->flags = 0;
  539. if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
  540. timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
  541. else
  542. timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
  543. if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
  544. timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
  545. else
  546. timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
  547. if (mode->vmode == FB_VMODE_INTERLACED)
  548. timing->flags |= DISPLAY_FLAGS_INTERLACED;
  549. }
  550. static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
  551. bool for_ext_vga_dac)
  552. {
  553. struct sunxi_lcdc_reg * const lcdc =
  554. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  555. struct sunxi_ccm_reg * const ccm =
  556. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  557. int clk_div, clk_double, pin;
  558. struct display_timing timing;
  559. #if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
  560. for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
  561. #else
  562. for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
  563. #endif
  564. #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
  565. sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
  566. #endif
  567. #ifdef CONFIG_VIDEO_LCD_IF_LVDS
  568. sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
  569. #endif
  570. #ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
  571. sunxi_gpio_set_drv(pin, 3);
  572. #endif
  573. }
  574. lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
  575. sunxi_is_composite());
  576. sunxi_ctfb_mode_to_display_timing(mode, &timing);
  577. lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
  578. sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
  579. }
  580. #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
  581. static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
  582. int *clk_div, int *clk_double,
  583. bool use_portd_hvsync)
  584. {
  585. struct sunxi_lcdc_reg * const lcdc =
  586. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  587. struct sunxi_ccm_reg * const ccm =
  588. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  589. struct display_timing timing;
  590. sunxi_ctfb_mode_to_display_timing(mode, &timing);
  591. lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
  592. sunxi_is_composite());
  593. if (use_portd_hvsync) {
  594. sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
  595. sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
  596. }
  597. lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
  598. sunxi_is_composite());
  599. }
  600. #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
  601. #ifdef CONFIG_VIDEO_HDMI
  602. static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
  603. {
  604. struct sunxi_hdmi_reg * const hdmi =
  605. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  606. u8 checksum = 0;
  607. u8 avi_info_frame[17] = {
  608. 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
  609. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  610. 0x00
  611. };
  612. u8 vendor_info_frame[19] = {
  613. 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
  614. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  615. 0x00, 0x00, 0x00
  616. };
  617. int i;
  618. if (mode->pixclock_khz <= 27000)
  619. avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
  620. else
  621. avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
  622. if (mode->xres * 100 / mode->yres < 156)
  623. avi_info_frame[5] |= 0x18; /* 4 : 3 */
  624. else
  625. avi_info_frame[5] |= 0x28; /* 16 : 9 */
  626. for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
  627. checksum += avi_info_frame[i];
  628. avi_info_frame[3] = 0x100 - checksum;
  629. for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
  630. writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
  631. writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
  632. writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
  633. for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
  634. writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
  635. writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
  636. writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
  637. setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
  638. }
  639. static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
  640. int clk_div, int clk_double)
  641. {
  642. struct sunxi_hdmi_reg * const hdmi =
  643. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  644. int x, y;
  645. /* Write clear interrupt status bits */
  646. writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
  647. if (sunxi_display.monitor == sunxi_monitor_hdmi)
  648. sunxi_hdmi_setup_info_frames(mode);
  649. /* Set input sync enable */
  650. writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
  651. /* Init various registers, select pll3 as clock source */
  652. writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
  653. writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
  654. writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
  655. writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
  656. writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
  657. /* Setup clk div and doubler */
  658. clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
  659. SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
  660. if (!clk_double)
  661. setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
  662. /* Setup timing registers */
  663. writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
  664. &hdmi->video_size);
  665. x = mode->hsync_len + mode->left_margin;
  666. y = mode->vsync_len + mode->upper_margin;
  667. writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
  668. x = mode->right_margin;
  669. y = mode->lower_margin;
  670. writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
  671. x = mode->hsync_len;
  672. y = mode->vsync_len;
  673. writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
  674. if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
  675. setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
  676. if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
  677. setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
  678. }
  679. static void sunxi_hdmi_enable(void)
  680. {
  681. struct sunxi_hdmi_reg * const hdmi =
  682. (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  683. udelay(100);
  684. setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
  685. }
  686. #endif /* CONFIG_VIDEO_HDMI */
  687. #if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
  688. static void sunxi_tvencoder_mode_set(void)
  689. {
  690. struct sunxi_ccm_reg * const ccm =
  691. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  692. struct sunxi_tve_reg * const tve =
  693. (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
  694. /* Reset off */
  695. setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
  696. /* Clock on */
  697. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
  698. switch (sunxi_display.monitor) {
  699. case sunxi_monitor_vga:
  700. tvencoder_mode_set(tve, tve_mode_vga);
  701. break;
  702. case sunxi_monitor_composite_pal_nc:
  703. tvencoder_mode_set(tve, tve_mode_composite_pal_nc);
  704. break;
  705. case sunxi_monitor_composite_pal:
  706. tvencoder_mode_set(tve, tve_mode_composite_pal);
  707. break;
  708. case sunxi_monitor_composite_pal_m:
  709. tvencoder_mode_set(tve, tve_mode_composite_pal_m);
  710. break;
  711. case sunxi_monitor_composite_ntsc:
  712. tvencoder_mode_set(tve, tve_mode_composite_ntsc);
  713. break;
  714. case sunxi_monitor_none:
  715. case sunxi_monitor_dvi:
  716. case sunxi_monitor_hdmi:
  717. case sunxi_monitor_lcd:
  718. break;
  719. }
  720. }
  721. #endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */
  722. static void sunxi_drc_init(void)
  723. {
  724. #ifdef CONFIG_SUNXI_GEN_SUN6I
  725. struct sunxi_ccm_reg * const ccm =
  726. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  727. /* On sun6i the drc must be clocked even when in pass-through mode */
  728. #ifdef CONFIG_MACH_SUN8I_A33
  729. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
  730. #endif
  731. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
  732. clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
  733. #endif
  734. }
  735. #ifdef CONFIG_VIDEO_VGA_VIA_LCD
  736. static void sunxi_vga_external_dac_enable(void)
  737. {
  738. int pin;
  739. pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
  740. if (pin >= 0) {
  741. gpio_request(pin, "vga_enable");
  742. gpio_direction_output(pin, 1);
  743. }
  744. }
  745. #endif /* CONFIG_VIDEO_VGA_VIA_LCD */
  746. #ifdef CONFIG_VIDEO_LCD_SSD2828
  747. static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
  748. {
  749. struct ssd2828_config cfg = {
  750. .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
  751. .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
  752. .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
  753. .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
  754. .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
  755. .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
  756. .ssd2828_color_depth = 24,
  757. #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
  758. .mipi_dsi_number_of_data_lanes = 4,
  759. .mipi_dsi_bitrate_per_data_lane_mbps = 513,
  760. .mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
  761. .mipi_dsi_delay_after_set_display_on_ms = 200
  762. #else
  763. #error MIPI LCD panel needs configuration parameters
  764. #endif
  765. };
  766. if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
  767. printf("SSD2828: SPI pins are not properly configured\n");
  768. return 1;
  769. }
  770. if (cfg.reset_pin == -1) {
  771. printf("SSD2828: Reset pin is not properly configured\n");
  772. return 1;
  773. }
  774. return ssd2828_init(&cfg, mode);
  775. }
  776. #endif /* CONFIG_VIDEO_LCD_SSD2828 */
  777. static void sunxi_engines_init(void)
  778. {
  779. sunxi_composer_init();
  780. sunxi_lcdc_init();
  781. sunxi_drc_init();
  782. }
  783. static void sunxi_mode_set(const struct ctfb_res_modes *mode,
  784. unsigned int address)
  785. {
  786. int __maybe_unused clk_div, clk_double;
  787. struct sunxi_lcdc_reg * const lcdc =
  788. (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  789. struct sunxi_tve_reg * __maybe_unused const tve =
  790. (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
  791. switch (sunxi_display.monitor) {
  792. case sunxi_monitor_none:
  793. break;
  794. case sunxi_monitor_dvi:
  795. case sunxi_monitor_hdmi:
  796. #ifdef CONFIG_VIDEO_HDMI
  797. sunxi_composer_mode_set(mode, address);
  798. sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
  799. sunxi_hdmi_mode_set(mode, clk_div, clk_double);
  800. sunxi_composer_enable();
  801. lcdc_enable(lcdc, sunxi_display.depth);
  802. sunxi_hdmi_enable();
  803. #endif
  804. break;
  805. case sunxi_monitor_lcd:
  806. sunxi_lcdc_panel_enable();
  807. if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
  808. /*
  809. * The anx9804 needs 1.8V from eldo3, we do this here
  810. * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
  811. * to avoid turning this on when using hdmi output.
  812. */
  813. axp_set_eldo(3, 1800);
  814. anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
  815. ANX9804_DATA_RATE_1620M,
  816. sunxi_display.depth);
  817. }
  818. if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
  819. mdelay(50); /* Wait for lcd controller power on */
  820. hitachi_tx18d42vm_init();
  821. }
  822. if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
  823. unsigned int orig_i2c_bus = i2c_get_bus_num();
  824. i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
  825. i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
  826. i2c_set_bus_num(orig_i2c_bus);
  827. }
  828. sunxi_composer_mode_set(mode, address);
  829. sunxi_lcdc_tcon0_mode_set(mode, false);
  830. sunxi_composer_enable();
  831. lcdc_enable(lcdc, sunxi_display.depth);
  832. #ifdef CONFIG_VIDEO_LCD_SSD2828
  833. sunxi_ssd2828_init(mode);
  834. #endif
  835. sunxi_lcdc_backlight_enable();
  836. break;
  837. case sunxi_monitor_vga:
  838. #ifdef CONFIG_VIDEO_VGA
  839. sunxi_composer_mode_set(mode, address);
  840. sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
  841. sunxi_tvencoder_mode_set();
  842. sunxi_composer_enable();
  843. lcdc_enable(lcdc, sunxi_display.depth);
  844. tvencoder_enable(tve);
  845. #elif defined CONFIG_VIDEO_VGA_VIA_LCD
  846. sunxi_composer_mode_set(mode, address);
  847. sunxi_lcdc_tcon0_mode_set(mode, true);
  848. sunxi_composer_enable();
  849. lcdc_enable(lcdc, sunxi_display.depth);
  850. sunxi_vga_external_dac_enable();
  851. #endif
  852. break;
  853. case sunxi_monitor_composite_pal:
  854. case sunxi_monitor_composite_ntsc:
  855. case sunxi_monitor_composite_pal_m:
  856. case sunxi_monitor_composite_pal_nc:
  857. #ifdef CONFIG_VIDEO_COMPOSITE
  858. sunxi_composer_mode_set(mode, address);
  859. sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
  860. sunxi_tvencoder_mode_set();
  861. sunxi_composer_enable();
  862. lcdc_enable(lcdc, sunxi_display.depth);
  863. tvencoder_enable(tve);
  864. #endif
  865. break;
  866. }
  867. }
  868. static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
  869. {
  870. switch (monitor) {
  871. case sunxi_monitor_none: return "none";
  872. case sunxi_monitor_dvi: return "dvi";
  873. case sunxi_monitor_hdmi: return "hdmi";
  874. case sunxi_monitor_lcd: return "lcd";
  875. case sunxi_monitor_vga: return "vga";
  876. case sunxi_monitor_composite_pal: return "composite-pal";
  877. case sunxi_monitor_composite_ntsc: return "composite-ntsc";
  878. case sunxi_monitor_composite_pal_m: return "composite-pal-m";
  879. case sunxi_monitor_composite_pal_nc: return "composite-pal-nc";
  880. }
  881. return NULL; /* never reached */
  882. }
  883. ulong board_get_usable_ram_top(ulong total_size)
  884. {
  885. return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
  886. }
  887. static bool sunxi_has_hdmi(void)
  888. {
  889. #ifdef CONFIG_VIDEO_HDMI
  890. return true;
  891. #else
  892. return false;
  893. #endif
  894. }
  895. static bool sunxi_has_lcd(void)
  896. {
  897. char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
  898. return lcd_mode[0] != 0;
  899. }
  900. static bool sunxi_has_vga(void)
  901. {
  902. #if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_VGA_VIA_LCD
  903. return true;
  904. #else
  905. return false;
  906. #endif
  907. }
  908. static bool sunxi_has_composite(void)
  909. {
  910. #ifdef CONFIG_VIDEO_COMPOSITE
  911. return true;
  912. #else
  913. return false;
  914. #endif
  915. }
  916. static enum sunxi_monitor sunxi_get_default_mon(bool allow_hdmi)
  917. {
  918. if (allow_hdmi && sunxi_has_hdmi())
  919. return sunxi_monitor_dvi;
  920. else if (sunxi_has_lcd())
  921. return sunxi_monitor_lcd;
  922. else if (sunxi_has_vga())
  923. return sunxi_monitor_vga;
  924. else if (sunxi_has_composite())
  925. return sunxi_monitor_composite_pal;
  926. else
  927. return sunxi_monitor_none;
  928. }
  929. void *video_hw_init(void)
  930. {
  931. static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
  932. const struct ctfb_res_modes *mode;
  933. struct ctfb_res_modes custom;
  934. const char *options;
  935. #ifdef CONFIG_VIDEO_HDMI
  936. int hpd, hpd_delay, edid;
  937. bool hdmi_present;
  938. #endif
  939. int i, overscan_offset, overscan_x, overscan_y;
  940. unsigned int fb_dma_addr;
  941. char mon[16];
  942. char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
  943. memset(&sunxi_display, 0, sizeof(struct sunxi_display));
  944. video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
  945. &sunxi_display.depth, &options);
  946. #ifdef CONFIG_VIDEO_HDMI
  947. hpd = video_get_option_int(options, "hpd", 1);
  948. hpd_delay = video_get_option_int(options, "hpd_delay", 500);
  949. edid = video_get_option_int(options, "edid", 1);
  950. #endif
  951. overscan_x = video_get_option_int(options, "overscan_x", -1);
  952. overscan_y = video_get_option_int(options, "overscan_y", -1);
  953. sunxi_display.monitor = sunxi_get_default_mon(true);
  954. video_get_option_string(options, "monitor", mon, sizeof(mon),
  955. sunxi_get_mon_desc(sunxi_display.monitor));
  956. for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
  957. if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
  958. sunxi_display.monitor = i;
  959. break;
  960. }
  961. }
  962. if (i > SUNXI_MONITOR_LAST)
  963. printf("Unknown monitor: '%s', falling back to '%s'\n",
  964. mon, sunxi_get_mon_desc(sunxi_display.monitor));
  965. #ifdef CONFIG_VIDEO_HDMI
  966. /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
  967. if (sunxi_display.monitor == sunxi_monitor_dvi ||
  968. sunxi_display.monitor == sunxi_monitor_hdmi) {
  969. /* Always call hdp_detect, as it also enables clocks, etc. */
  970. hdmi_present = (sunxi_hdmi_hpd_detect(hpd_delay) == 1);
  971. if (hdmi_present && edid) {
  972. printf("HDMI connected: ");
  973. if (sunxi_hdmi_edid_get_mode(&custom, true) == 0)
  974. mode = &custom;
  975. else
  976. hdmi_present = false;
  977. }
  978. /* Fall back to EDID in case HPD failed */
  979. if (edid && !hdmi_present) {
  980. if (sunxi_hdmi_edid_get_mode(&custom, false) == 0) {
  981. mode = &custom;
  982. hdmi_present = true;
  983. }
  984. }
  985. /* Shut down when display was not found */
  986. if ((hpd || edid) && !hdmi_present) {
  987. sunxi_hdmi_shutdown();
  988. sunxi_display.monitor = sunxi_get_default_mon(false);
  989. } /* else continue with hdmi/dvi without a cable connected */
  990. }
  991. #endif
  992. switch (sunxi_display.monitor) {
  993. case sunxi_monitor_none:
  994. return NULL;
  995. case sunxi_monitor_dvi:
  996. case sunxi_monitor_hdmi:
  997. if (!sunxi_has_hdmi()) {
  998. printf("HDMI/DVI not supported on this board\n");
  999. sunxi_display.monitor = sunxi_monitor_none;
  1000. return NULL;
  1001. }
  1002. break;
  1003. case sunxi_monitor_lcd:
  1004. if (!sunxi_has_lcd()) {
  1005. printf("LCD not supported on this board\n");
  1006. sunxi_display.monitor = sunxi_monitor_none;
  1007. return NULL;
  1008. }
  1009. sunxi_display.depth = video_get_params(&custom, lcd_mode);
  1010. mode = &custom;
  1011. break;
  1012. case sunxi_monitor_vga:
  1013. if (!sunxi_has_vga()) {
  1014. printf("VGA not supported on this board\n");
  1015. sunxi_display.monitor = sunxi_monitor_none;
  1016. return NULL;
  1017. }
  1018. sunxi_display.depth = 18;
  1019. break;
  1020. case sunxi_monitor_composite_pal:
  1021. case sunxi_monitor_composite_ntsc:
  1022. case sunxi_monitor_composite_pal_m:
  1023. case sunxi_monitor_composite_pal_nc:
  1024. if (!sunxi_has_composite()) {
  1025. printf("Composite video not supported on this board\n");
  1026. sunxi_display.monitor = sunxi_monitor_none;
  1027. return NULL;
  1028. }
  1029. if (sunxi_display.monitor == sunxi_monitor_composite_pal ||
  1030. sunxi_display.monitor == sunxi_monitor_composite_pal_nc)
  1031. mode = &composite_video_modes[0];
  1032. else
  1033. mode = &composite_video_modes[1];
  1034. sunxi_display.depth = 24;
  1035. break;
  1036. }
  1037. /* Yes these defaults are quite high, overscan on composite sucks... */
  1038. if (overscan_x == -1)
  1039. overscan_x = sunxi_is_composite() ? 32 : 0;
  1040. if (overscan_y == -1)
  1041. overscan_y = sunxi_is_composite() ? 20 : 0;
  1042. sunxi_display.fb_size =
  1043. (mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
  1044. overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
  1045. /* We want to keep the fb_base for simplefb page aligned, where as
  1046. * the sunxi dma engines will happily accept an unaligned address. */
  1047. if (overscan_offset)
  1048. sunxi_display.fb_size += 0x1000;
  1049. if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
  1050. printf("Error need %dkB for fb, but only %dkB is reserved\n",
  1051. sunxi_display.fb_size >> 10,
  1052. CONFIG_SUNXI_MAX_FB_SIZE >> 10);
  1053. return NULL;
  1054. }
  1055. printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n",
  1056. mode->xres, mode->yres,
  1057. (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
  1058. sunxi_get_mon_desc(sunxi_display.monitor),
  1059. overscan_x, overscan_y);
  1060. gd->fb_base = gd->bd->bi_dram[0].start +
  1061. gd->bd->bi_dram[0].size - sunxi_display.fb_size;
  1062. sunxi_engines_init();
  1063. #ifdef CONFIG_EFI_LOADER
  1064. efi_add_memory_map(gd->fb_base,
  1065. ALIGN(sunxi_display.fb_size, EFI_PAGE_SIZE) >>
  1066. EFI_PAGE_SHIFT,
  1067. EFI_RESERVED_MEMORY_TYPE, false);
  1068. #endif
  1069. fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;
  1070. sunxi_display.fb_addr = gd->fb_base;
  1071. if (overscan_offset) {
  1072. fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
  1073. sunxi_display.fb_addr += (overscan_offset + 0xfff) & ~0xfff;
  1074. memset((void *)gd->fb_base, 0, sunxi_display.fb_size);
  1075. flush_cache(gd->fb_base, sunxi_display.fb_size);
  1076. }
  1077. sunxi_mode_set(mode, fb_dma_addr);
  1078. /*
  1079. * These are the only members of this structure that are used. All the
  1080. * others are driver specific. The pitch is stored in plnSizeX.
  1081. */
  1082. graphic_device->frameAdrs = sunxi_display.fb_addr;
  1083. graphic_device->gdfIndex = GDF_32BIT_X888RGB;
  1084. graphic_device->gdfBytesPP = 4;
  1085. graphic_device->winSizeX = mode->xres - 2 * overscan_x;
  1086. graphic_device->winSizeY = mode->yres - 2 * overscan_y;
  1087. graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP;
  1088. return graphic_device;
  1089. }
  1090. /*
  1091. * Simplefb support.
  1092. */
  1093. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
  1094. int sunxi_simplefb_setup(void *blob)
  1095. {
  1096. static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
  1097. int offset, ret;
  1098. u64 start, size;
  1099. const char *pipeline = NULL;
  1100. #ifdef CONFIG_MACH_SUN4I
  1101. #define PIPELINE_PREFIX "de_fe0-"
  1102. #else
  1103. #define PIPELINE_PREFIX
  1104. #endif
  1105. switch (sunxi_display.monitor) {
  1106. case sunxi_monitor_none:
  1107. return 0;
  1108. case sunxi_monitor_dvi:
  1109. case sunxi_monitor_hdmi:
  1110. pipeline = PIPELINE_PREFIX "de_be0-lcd0-hdmi";
  1111. break;
  1112. case sunxi_monitor_lcd:
  1113. pipeline = PIPELINE_PREFIX "de_be0-lcd0";
  1114. break;
  1115. case sunxi_monitor_vga:
  1116. #ifdef CONFIG_VIDEO_VGA
  1117. pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
  1118. #elif defined CONFIG_VIDEO_VGA_VIA_LCD
  1119. pipeline = PIPELINE_PREFIX "de_be0-lcd0";
  1120. #endif
  1121. break;
  1122. case sunxi_monitor_composite_pal:
  1123. case sunxi_monitor_composite_ntsc:
  1124. case sunxi_monitor_composite_pal_m:
  1125. case sunxi_monitor_composite_pal_nc:
  1126. pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
  1127. break;
  1128. }
  1129. offset = sunxi_simplefb_fdt_match(blob, pipeline);
  1130. if (offset < 0) {
  1131. eprintf("Cannot setup simplefb: node not found\n");
  1132. return 0; /* Keep older kernels working */
  1133. }
  1134. /*
  1135. * Do not report the framebuffer as free RAM to the OS, note we cannot
  1136. * use fdt_add_mem_rsv() here, because then it is still seen as RAM,
  1137. * and e.g. Linux refuses to iomap RAM on ARM, see:
  1138. * linux/arch/arm/mm/ioremap.c around line 301.
  1139. */
  1140. start = gd->bd->bi_dram[0].start;
  1141. size = gd->bd->bi_dram[0].size - sunxi_display.fb_size;
  1142. ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
  1143. if (ret) {
  1144. eprintf("Cannot setup simplefb: Error reserving memory\n");
  1145. return ret;
  1146. }
  1147. ret = fdt_setup_simplefb_node(blob, offset, sunxi_display.fb_addr,
  1148. graphic_device->winSizeX, graphic_device->winSizeY,
  1149. graphic_device->plnSizeX, "x8r8g8b8");
  1150. if (ret)
  1151. eprintf("Cannot setup simplefb: Error setting properties\n");
  1152. return ret;
  1153. }
  1154. #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */