m53menlo.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Menlosystems M53Menlo board
  4. *
  5. * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
  6. * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/iomux-mx53.h>
  17. #include <asm/mach-imx/mx5_video.h>
  18. #include <asm/mach-imx/video.h>
  19. #include <asm/gpio.h>
  20. #include <asm/spl.h>
  21. #include <env.h>
  22. #include <fdt_support.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <gzip.h>
  25. #include <i2c.h>
  26. #include <ipu_pixfmt.h>
  27. #include <linux/errno.h>
  28. #include <linux/fb.h>
  29. #include <mmc.h>
  30. #include <netdev.h>
  31. #include <spl.h>
  32. #include <splash.h>
  33. #include <usb/ehci-ci.h>
  34. #include <video_console.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static u32 mx53_dram_size[2];
  37. ulong board_get_usable_ram_top(ulong total_size)
  38. {
  39. /*
  40. * WARNING: We must override get_effective_memsize() function here
  41. * to report only the size of the first DRAM bank. This is to make
  42. * U-Boot relocator place U-Boot into valid memory, that is, at the
  43. * end of the first DRAM bank. If we did not override this function
  44. * like so, U-Boot would be placed at the address of the first DRAM
  45. * bank + total DRAM size - sizeof(uboot), which in the setup where
  46. * each DRAM bank contains 512MiB of DRAM would result in placing
  47. * U-Boot into invalid memory area close to the end of the first
  48. * DRAM bank.
  49. */
  50. return PHYS_SDRAM_2 + mx53_dram_size[1];
  51. }
  52. int dram_init(void)
  53. {
  54. mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  55. mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  56. gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  57. return 0;
  58. }
  59. int dram_init_banksize(void)
  60. {
  61. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  62. gd->bd->bi_dram[0].size = mx53_dram_size[0];
  63. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  64. gd->bd->bi_dram[1].size = mx53_dram_size[1];
  65. return 0;
  66. }
  67. static void setup_iomux_uart(void)
  68. {
  69. static const iomux_v3_cfg_t uart_pads[] = {
  70. MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  71. MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  72. };
  73. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  74. }
  75. static void setup_iomux_fec(void)
  76. {
  77. static const iomux_v3_cfg_t fec_pads[] = {
  78. /* MDIO pads */
  79. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  80. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  81. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  82. /* FEC 0 pads */
  83. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  84. PAD_CTL_HYS | PAD_CTL_PKE),
  85. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  86. PAD_CTL_HYS | PAD_CTL_PKE),
  87. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  88. PAD_CTL_HYS | PAD_CTL_PKE),
  89. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  90. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  91. PAD_CTL_HYS | PAD_CTL_PKE),
  92. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  93. PAD_CTL_HYS | PAD_CTL_PKE),
  94. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  95. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  96. /* FEC 1 pads */
  97. NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
  98. PAD_CTL_HYS | PAD_CTL_PKE),
  99. NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
  100. PAD_CTL_HYS | PAD_CTL_PKE),
  101. NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
  102. PAD_CTL_HYS | PAD_CTL_PKE),
  103. NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
  104. PAD_CTL_HYS | PAD_CTL_PKE),
  105. NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
  106. PAD_CTL_HYS | PAD_CTL_PKE),
  107. NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
  108. NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
  109. PAD_CTL_HYS | PAD_CTL_PKE),
  110. NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
  111. };
  112. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  113. }
  114. #ifdef CONFIG_FSL_ESDHC_IMX
  115. struct fsl_esdhc_cfg esdhc_cfg = {
  116. MMC_SDHC1_BASE_ADDR,
  117. };
  118. int board_mmc_getcd(struct mmc *mmc)
  119. {
  120. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
  121. gpio_direction_input(IMX_GPIO_NR(1, 1));
  122. return !gpio_get_value(IMX_GPIO_NR(1, 1));
  123. }
  124. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  125. PAD_CTL_PUS_100K_UP)
  126. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  127. PAD_CTL_DSE_HIGH)
  128. int board_mmc_init(bd_t *bis)
  129. {
  130. static const iomux_v3_cfg_t sd1_pads[] = {
  131. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  132. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  133. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  134. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  135. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  136. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  137. };
  138. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  139. imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
  140. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  141. }
  142. #endif
  143. static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
  144. {
  145. static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  146. int ret;
  147. /* For ETM0430G0DH6 model, this must be enabled before the clock. */
  148. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  149. /*
  150. * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
  151. * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  152. */
  153. ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
  154. if (ret)
  155. puts("IPU: Failed to configure LDB clock\n");
  156. /* Configure CCM_CSCMR2 */
  157. clrsetbits_le32(&mxc_ccm->cscmr2,
  158. (0x7 << 26) | BIT(10) | BIT(8),
  159. (0x5 << 26) | BIT(10) | BIT(8));
  160. /* Configure LDB_CTRL */
  161. writel(0x201, 0x53fa8008);
  162. }
  163. static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
  164. {
  165. gpio_request(IMX_GPIO_NR(6, 0), "LCD");
  166. /* For ETM0430G0DH6 model, this must be enabled before the clock. */
  167. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  168. /*
  169. * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
  170. * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  171. */
  172. enable_lvds_clock(dev, 63);
  173. }
  174. static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
  175. {
  176. gpio_request(IMX_GPIO_NR(6, 0), "LCD");
  177. /*
  178. * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
  179. * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  180. */
  181. enable_lvds_clock(dev, 233);
  182. /* For ETM0700G0DH6 model, this may be enabled after the clock. */
  183. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  184. }
  185. static const char *lvds_compat_string;
  186. static int detect_lvds(struct display_info_t const *dev)
  187. {
  188. u8 touchid[23];
  189. u8 *touchptr = &touchid[0];
  190. int ret;
  191. ret = i2c_set_bus_num(0);
  192. if (ret)
  193. return 0;
  194. /* Touchscreen is at address 0x38, ID register is 0xbb. */
  195. ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
  196. if (ret)
  197. return 0;
  198. /* EP0430 prefixes the response with 0xbb, skip it. */
  199. if (*touchptr == 0xbb)
  200. touchptr++;
  201. /* Skip the 'EP' prefix. */
  202. touchptr += 2;
  203. ret = !memcmp(touchptr, &dev->mode.name[7], 4);
  204. if (ret)
  205. lvds_compat_string = dev->mode.name;
  206. return ret;
  207. }
  208. void board_preboot_os(void)
  209. {
  210. /* Power off the LCD to prevent awful color flicker */
  211. gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
  212. }
  213. int ft_board_setup(void *blob, bd_t *bd)
  214. {
  215. if (lvds_compat_string)
  216. do_fixup_by_path_string(blob, "/panel", "compatible",
  217. lvds_compat_string);
  218. return 0;
  219. }
  220. struct display_info_t const displays[] = {
  221. {
  222. .bus = 0,
  223. .addr = 0,
  224. .detect = detect_lvds,
  225. .enable = enable_lvds_etm0430g0dh6,
  226. .pixfmt = IPU_PIX_FMT_RGB666,
  227. .mode = {
  228. .name = "edt,etm0430g0dh6",
  229. .refresh = 60,
  230. .xres = 480,
  231. .yres = 272,
  232. .pixclock = 111111, /* picosecond (9 MHz) */
  233. .left_margin = 2,
  234. .right_margin = 2,
  235. .upper_margin = 2,
  236. .lower_margin = 2,
  237. .hsync_len = 41,
  238. .vsync_len = 10,
  239. .sync = 0x40000000,
  240. .vmode = FB_VMODE_NONINTERLACED
  241. }
  242. }, {
  243. .bus = 0,
  244. .addr = 0,
  245. .detect = detect_lvds,
  246. .enable = enable_lvds_etm0700g0dh6,
  247. .pixfmt = IPU_PIX_FMT_RGB666,
  248. .mode = {
  249. .name = "edt,etm0700g0dh6",
  250. .refresh = 60,
  251. .xres = 800,
  252. .yres = 480,
  253. .pixclock = 30048, /* picosecond (33.28 MHz) */
  254. .left_margin = 40,
  255. .right_margin = 88,
  256. .upper_margin = 10,
  257. .lower_margin = 33,
  258. .hsync_len = 128,
  259. .vsync_len = 2,
  260. .sync = FB_SYNC_EXT,
  261. .vmode = FB_VMODE_NONINTERLACED
  262. }
  263. }
  264. };
  265. size_t display_count = ARRAY_SIZE(displays);
  266. #ifdef CONFIG_SPLASH_SCREEN
  267. static struct splash_location default_splash_locations[] = {
  268. {
  269. .name = "mmc_fs",
  270. .storage = SPLASH_STORAGE_MMC,
  271. .flags = SPLASH_STORAGE_FS,
  272. .devpart = "0:1",
  273. },
  274. };
  275. int splash_screen_prepare(void)
  276. {
  277. return splash_source_load(default_splash_locations,
  278. ARRAY_SIZE(default_splash_locations));
  279. }
  280. #endif
  281. int board_late_init(void)
  282. {
  283. #if defined(CONFIG_VIDEO_IPUV3)
  284. struct udevice *dev;
  285. int xpos, ypos, ret;
  286. char *s;
  287. void *dst;
  288. ulong addr, len;
  289. splash_get_pos(&xpos, &ypos);
  290. s = env_get("splashimage");
  291. if (!s)
  292. return 0;
  293. addr = simple_strtoul(s, NULL, 16);
  294. dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
  295. if (!dst)
  296. return -ENOMEM;
  297. ret = splash_screen_prepare();
  298. if (ret < 0)
  299. return ret;
  300. len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
  301. ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
  302. (uchar *)addr, &len);
  303. if (ret) {
  304. printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
  305. free(dst);
  306. return ret;
  307. }
  308. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  309. if (ret)
  310. return ret;
  311. ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
  312. if (ret)
  313. return ret;
  314. #endif
  315. return 0;
  316. }
  317. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  318. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  319. static void setup_iomux_i2c(void)
  320. {
  321. static const iomux_v3_cfg_t i2c_pads[] = {
  322. /* I2C1 */
  323. NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
  324. NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
  325. /* I2C2 */
  326. NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
  327. NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
  328. };
  329. imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
  330. }
  331. static void setup_iomux_video(void)
  332. {
  333. static const iomux_v3_cfg_t lcd_pads[] = {
  334. MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
  335. MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
  336. MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
  337. MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
  338. MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
  339. };
  340. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  341. }
  342. static void setup_iomux_nand(void)
  343. {
  344. static const iomux_v3_cfg_t nand_pads[] = {
  345. NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  346. PAD_CTL_DSE_HIGH),
  347. NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  348. PAD_CTL_DSE_HIGH),
  349. NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  350. PAD_CTL_DSE_HIGH),
  351. NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  352. PAD_CTL_DSE_HIGH),
  353. NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  354. PAD_CTL_PUS_100K_UP),
  355. NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  356. PAD_CTL_PUS_100K_UP),
  357. NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  358. PAD_CTL_DSE_HIGH),
  359. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
  360. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  361. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
  362. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  363. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
  364. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  365. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
  366. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  367. NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
  368. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  369. NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
  370. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  371. NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
  372. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  373. NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
  374. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  375. };
  376. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  377. }
  378. static void m53_set_clock(void)
  379. {
  380. int ret;
  381. const u32 ref_clk = MXC_HCLK;
  382. const u32 dramclk = 400;
  383. u32 cpuclk;
  384. gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
  385. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
  386. PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
  387. gpio_direction_input(IMX_GPIO_NR(4, 0));
  388. /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
  389. cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
  390. ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
  391. if (ret)
  392. printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
  393. ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
  394. if (ret) {
  395. printf("CPU: Switch peripheral clock to %dMHz failed\n",
  396. dramclk);
  397. }
  398. ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
  399. if (ret)
  400. printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
  401. }
  402. static void m53_set_nand(void)
  403. {
  404. u32 i;
  405. /* NAND flash is muxed on ATA pins */
  406. setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
  407. /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
  408. for (i = 0x4; i < 0x94; i += 0x18) {
  409. clrbits_le32(WEIM_BASE_ADDR + i,
  410. WEIM_GCR2_MUX16_BYP_GRANT_MASK);
  411. }
  412. mxc_set_clock(0, 33, MXC_NFC_CLK);
  413. enable_nfc_clk(1);
  414. }
  415. int board_early_init_f(void)
  416. {
  417. setup_iomux_uart();
  418. setup_iomux_fec();
  419. setup_iomux_i2c();
  420. setup_iomux_nand();
  421. setup_iomux_video();
  422. m53_set_clock();
  423. mxc_set_sata_internal_clock();
  424. /* NAND clock @ 33MHz */
  425. m53_set_nand();
  426. return 0;
  427. }
  428. int board_init(void)
  429. {
  430. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  431. return 0;
  432. }
  433. int checkboard(void)
  434. {
  435. puts("Board: Menlosystems M53Menlo\n");
  436. return 0;
  437. }
  438. /*
  439. * NAND SPL
  440. */
  441. #ifdef CONFIG_SPL_BUILD
  442. void spl_board_init(void)
  443. {
  444. setup_iomux_nand();
  445. m53_set_clock();
  446. m53_set_nand();
  447. }
  448. u32 spl_boot_device(void)
  449. {
  450. return BOOT_DEVICE_NAND;
  451. }
  452. #endif