dram.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <asm/mrccache.h>
  12. #include <asm/mtrr.h>
  13. #include <asm/post.h>
  14. #include <asm/arch/mrc.h>
  15. #include <asm/arch/msg_port.h>
  16. #include <asm/arch/quark.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
  19. {
  20. struct mrc_data_container *cache;
  21. struct mrc_region entry;
  22. int ret;
  23. ret = mrccache_get_region(NULL, &entry);
  24. if (ret)
  25. return ret;
  26. cache = mrccache_find_current(&entry);
  27. if (!cache)
  28. return -ENOENT;
  29. debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
  30. cache->data, cache->data_size, cache->checksum);
  31. /* copy mrc cache to the mrc_params */
  32. memcpy(&mrc_params->timings, cache->data, cache->data_size);
  33. return 0;
  34. }
  35. static int mrc_configure_params(struct mrc_params *mrc_params)
  36. {
  37. const void *blob = gd->fdt_blob;
  38. int node;
  39. int mrc_flags;
  40. node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
  41. if (node < 0) {
  42. debug("%s: Cannot find MRC node\n", __func__);
  43. return -EINVAL;
  44. }
  45. #ifdef CONFIG_ENABLE_MRC_CACHE
  46. mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
  47. if (mrc_params->boot_mode)
  48. mrc_params->boot_mode = BM_COLD;
  49. else
  50. mrc_params->boot_mode = BM_FAST;
  51. #else
  52. mrc_params->boot_mode = BM_COLD;
  53. #endif
  54. /*
  55. * TODO:
  56. *
  57. * We need determine ECC by pin strap state
  58. *
  59. * Disable ECC by default for now
  60. */
  61. mrc_params->ecc_enables = 0;
  62. mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
  63. if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
  64. mrc_params->scrambling_enables = 1;
  65. else
  66. mrc_params->scrambling_enables = 0;
  67. mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
  68. mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
  69. mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
  70. mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
  71. mrc_params->channel_enables = fdtdec_get_int(blob, node,
  72. "chan-mask", 0);
  73. mrc_params->channel_width = fdtdec_get_int(blob, node,
  74. "chan-width", 0);
  75. mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
  76. mrc_params->refresh_rate = fdtdec_get_int(blob, node,
  77. "refresh-rate", 0);
  78. mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
  79. "sr-temp-range", 0);
  80. mrc_params->ron_value = fdtdec_get_int(blob, node,
  81. "ron-value", 0);
  82. mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
  83. "rtt-nom-value", 0);
  84. mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
  85. "rd-odt-value", 0);
  86. mrc_params->params.density = fdtdec_get_int(blob, node,
  87. "dram-density", 0);
  88. mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
  89. mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
  90. mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
  91. mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
  92. mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
  93. debug("MRC dram_width %d\n", mrc_params->dram_width);
  94. debug("MRC rank_enables %d\n", mrc_params->rank_enables);
  95. debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
  96. debug("MRC flags: %s\n",
  97. (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
  98. debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
  99. mrc_params->params.density, mrc_params->params.cl,
  100. mrc_params->params.ras, mrc_params->params.wtr,
  101. mrc_params->params.rrd, mrc_params->params.faw);
  102. return 0;
  103. }
  104. int dram_init(void)
  105. {
  106. struct mrc_params mrc_params;
  107. #ifdef CONFIG_ENABLE_MRC_CACHE
  108. char *cache;
  109. #endif
  110. int ret;
  111. memset(&mrc_params, 0, sizeof(struct mrc_params));
  112. ret = mrc_configure_params(&mrc_params);
  113. if (ret)
  114. return ret;
  115. /* Set up the DRAM by calling the memory reference code */
  116. mrc_init(&mrc_params);
  117. if (mrc_params.status)
  118. return -EIO;
  119. gd->ram_size = mrc_params.mem_size;
  120. post_code(POST_DRAM);
  121. /* variable range MTRR#2: RAM area */
  122. disable_caches();
  123. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
  124. 0 | MTRR_TYPE_WRBACK);
  125. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
  126. (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
  127. enable_caches();
  128. #ifdef CONFIG_ENABLE_MRC_CACHE
  129. cache = malloc(sizeof(struct mrc_timings));
  130. if (cache) {
  131. memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
  132. gd->arch.mrc_output = cache;
  133. gd->arch.mrc_output_len = sizeof(struct mrc_timings);
  134. }
  135. #endif
  136. return 0;
  137. }
  138. int dram_init_banksize(void)
  139. {
  140. gd->bd->bi_dram[0].start = 0;
  141. gd->bd->bi_dram[0].size = gd->ram_size;
  142. return 0;
  143. }
  144. /*
  145. * This function looks for the highest region of memory lower than 4GB which
  146. * has enough space for U-Boot where U-Boot is aligned on a page boundary.
  147. * It overrides the default implementation found elsewhere which simply
  148. * picks the end of ram, wherever that may be. The location of the stack,
  149. * the relocation address, and how far U-Boot is moved by relocation are
  150. * set in the global data structure.
  151. */
  152. ulong board_get_usable_ram_top(ulong total_size)
  153. {
  154. return gd->ram_size;
  155. }