mrc.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <syscon.h>
  9. #include <asm/cpu.h>
  10. #include <asm/gpio.h>
  11. #include <asm/intel_regs.h>
  12. #include <asm/mrc_common.h>
  13. #include <asm/pch_common.h>
  14. #include <asm/post.h>
  15. #include <asm/arch/me.h>
  16. #include <asm/report_platform.h>
  17. static const char *const ecc_decoder[] = {
  18. "inactive",
  19. "active on IO",
  20. "disabled on IO",
  21. "active"
  22. };
  23. ulong mrc_common_board_get_usable_ram_top(ulong total_size)
  24. {
  25. struct memory_info *info = &gd->arch.meminfo;
  26. uintptr_t dest_addr = 0;
  27. struct memory_area *largest = NULL;
  28. int i;
  29. /* Find largest area of memory below 4GB */
  30. for (i = 0; i < info->num_areas; i++) {
  31. struct memory_area *area = &info->area[i];
  32. if (area->start >= 1ULL << 32)
  33. continue;
  34. if (!largest || area->size > largest->size)
  35. largest = area;
  36. }
  37. /* If no suitable area was found, return an error. */
  38. assert(largest);
  39. if (!largest || largest->size < (2 << 20))
  40. panic("No available memory found for relocation");
  41. dest_addr = largest->start + largest->size;
  42. return (ulong)dest_addr;
  43. }
  44. void mrc_common_dram_init_banksize(void)
  45. {
  46. struct memory_info *info = &gd->arch.meminfo;
  47. int num_banks;
  48. int i;
  49. for (i = 0, num_banks = 0; i < info->num_areas; i++) {
  50. struct memory_area *area = &info->area[i];
  51. if (area->start >= 1ULL << 32)
  52. continue;
  53. gd->bd->bi_dram[num_banks].start = area->start;
  54. gd->bd->bi_dram[num_banks].size = area->size;
  55. num_banks++;
  56. }
  57. }
  58. int mrc_add_memory_area(struct memory_info *info, uint64_t start,
  59. uint64_t end)
  60. {
  61. struct memory_area *ptr;
  62. if (info->num_areas == CONFIG_NR_DRAM_BANKS)
  63. return -ENOSPC;
  64. ptr = &info->area[info->num_areas];
  65. ptr->start = start;
  66. ptr->size = end - start;
  67. info->total_memory += ptr->size;
  68. if (ptr->start < (1ULL << 32))
  69. info->total_32bit_memory += ptr->size;
  70. debug("%d: memory %llx size %llx, total now %llx / %llx\n",
  71. info->num_areas, ptr->start, ptr->size,
  72. info->total_32bit_memory, info->total_memory);
  73. info->num_areas++;
  74. return 0;
  75. }
  76. /*
  77. * Dump in the log memory controller configuration as read from the memory
  78. * controller registers.
  79. */
  80. void report_memory_config(void)
  81. {
  82. u32 addr_decoder_common, addr_decode_ch[2];
  83. int i;
  84. addr_decoder_common = readl(MCHBAR_REG(0x5000));
  85. addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
  86. addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
  87. debug("memcfg DDR3 clock %d MHz\n",
  88. (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
  89. debug("memcfg channel assignment: A: %d, B % d, C % d\n",
  90. addr_decoder_common & 3,
  91. (addr_decoder_common >> 2) & 3,
  92. (addr_decoder_common >> 4) & 3);
  93. for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
  94. u32 ch_conf = addr_decode_ch[i];
  95. debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
  96. debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
  97. debug(" enhanced interleave mode %s\n",
  98. ((ch_conf >> 22) & 1) ? "on" : "off");
  99. debug(" rank interleave %s\n",
  100. ((ch_conf >> 21) & 1) ? "on" : "off");
  101. debug(" DIMMA %d MB width x%d %s rank%s\n",
  102. ((ch_conf >> 0) & 0xff) * 256,
  103. ((ch_conf >> 19) & 1) ? 16 : 8,
  104. ((ch_conf >> 17) & 1) ? "dual" : "single",
  105. ((ch_conf >> 16) & 1) ? "" : ", selected");
  106. debug(" DIMMB %d MB width x%d %s rank%s\n",
  107. ((ch_conf >> 8) & 0xff) * 256,
  108. ((ch_conf >> 20) & 1) ? 16 : 8,
  109. ((ch_conf >> 18) & 1) ? "dual" : "single",
  110. ((ch_conf >> 16) & 1) ? ", selected" : "");
  111. }
  112. }
  113. int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap)
  114. {
  115. const void *blob = gd->fdt_blob;
  116. int spd_index;
  117. struct gpio_desc desc[4];
  118. int spd_node;
  119. int node;
  120. int ret;
  121. ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
  122. ARRAY_SIZE(desc), GPIOD_IS_IN);
  123. if (ret < 0) {
  124. debug("%s: gpio ret=%d\n", __func__, ret);
  125. return ret;
  126. }
  127. spd_index = dm_gpio_get_values_as_int(desc, ret);
  128. debug("spd index %d\n", spd_index);
  129. node = fdt_first_subnode(blob, dev_of_offset(dev));
  130. if (node < 0)
  131. return -EINVAL;
  132. for (spd_node = fdt_first_subnode(blob, node);
  133. spd_node > 0;
  134. spd_node = fdt_next_subnode(blob, spd_node)) {
  135. int len;
  136. if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
  137. continue;
  138. *spd_datap = fdt_getprop(blob, spd_node, "data", &len);
  139. if (len < size) {
  140. printf("Missing SPD data\n");
  141. return -EINVAL;
  142. }
  143. debug("Using SDRAM SPD data for '%s'\n",
  144. fdt_get_name(blob, spd_node, NULL));
  145. return 0;
  146. }
  147. printf("No SPD data found for index %d\n", spd_index);
  148. return -ENOENT;
  149. }
  150. asmlinkage void sdram_console_tx_byte(unsigned char byte)
  151. {
  152. #ifdef DEBUG
  153. putc(byte);
  154. #endif
  155. }
  156. /**
  157. * Find the PEI executable in the ROM and execute it.
  158. *
  159. * @me_dev: Management Engine device
  160. * @pei_data: configuration data for UEFI PEI reference code
  161. */
  162. static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
  163. void *pei_data, bool use_asm_linkage)
  164. {
  165. unsigned version;
  166. const char *data;
  167. report_platform_info(dev);
  168. debug("Starting UEFI PEI System Agent\n");
  169. debug("PEI data at %p:\n", pei_data);
  170. data = (char *)CONFIG_X86_MRC_ADDR;
  171. if (data) {
  172. int rv;
  173. ulong start;
  174. debug("Calling MRC at %p\n", data);
  175. post_code(POST_PRE_MRC);
  176. start = get_timer(0);
  177. if (use_asm_linkage) {
  178. asmlinkage int (*func)(void *);
  179. func = (asmlinkage int (*)(void *))data;
  180. rv = func(pei_data);
  181. } else {
  182. int (*func)(void *);
  183. func = (int (*)(void *))data;
  184. rv = func(pei_data);
  185. }
  186. post_code(POST_MRC);
  187. if (rv) {
  188. switch (rv) {
  189. case -1:
  190. printf("PEI version mismatch.\n");
  191. break;
  192. case -2:
  193. printf("Invalid memory frequency.\n");
  194. break;
  195. default:
  196. printf("MRC returned %x.\n", rv);
  197. }
  198. printf("Nonzero MRC return value.\n");
  199. return -EFAULT;
  200. }
  201. debug("MRC execution time %lu ms\n", get_timer(start));
  202. } else {
  203. printf("UEFI PEI System Agent not found.\n");
  204. return -ENOSYS;
  205. }
  206. version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION));
  207. debug("System Agent Version %d.%d.%d Build %d\n",
  208. version >> 24 , (version >> 16) & 0xff,
  209. (version >> 8) & 0xff, version & 0xff);
  210. return 0;
  211. }
  212. int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
  213. {
  214. struct udevice *me_dev;
  215. int ret;
  216. ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
  217. if (ret)
  218. return ret;
  219. ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
  220. if (ret)
  221. return ret;
  222. quick_ram_check();
  223. post_code(POST_DRAM);
  224. report_memory_config();
  225. return 0;
  226. }