sdram.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <ram.h>
  9. #include <asm/io.h>
  10. #include <asm/arch-rockchip/sdram.h>
  11. #include <dm/uclass-internal.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
  14. struct tos_parameter_t {
  15. u32 version;
  16. u32 checksum;
  17. struct {
  18. char name[8];
  19. s64 phy_addr;
  20. u32 size;
  21. u32 flags;
  22. } tee_mem;
  23. struct {
  24. char name[8];
  25. s64 phy_addr;
  26. u32 size;
  27. u32 flags;
  28. } drm_mem;
  29. s64 reserve[8];
  30. };
  31. int dram_init_banksize(void)
  32. {
  33. size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
  34. gd->ram_top);
  35. #ifdef CONFIG_ARM64
  36. /* Reserve 0x200000 for ATF bl31 */
  37. gd->bd->bi_dram[0].start = 0x200000;
  38. gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  39. #else
  40. #ifdef CONFIG_SPL_OPTEE
  41. struct tos_parameter_t *tos_parameter;
  42. tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
  43. TRUST_PARAMETER_OFFSET);
  44. if (tos_parameter->tee_mem.flags == 1) {
  45. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  46. gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
  47. - CONFIG_SYS_SDRAM_BASE;
  48. gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
  49. tos_parameter->tee_mem.size;
  50. gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  51. + top - gd->bd->bi_dram[1].start;
  52. } else {
  53. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  54. gd->bd->bi_dram[0].size = 0x8400000;
  55. /* Reserve 32M for OPTEE with TA */
  56. gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  57. + gd->bd->bi_dram[0].size + 0x2000000;
  58. gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  59. + top - gd->bd->bi_dram[1].start;
  60. }
  61. #else
  62. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  63. gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  64. #endif
  65. #endif
  66. return 0;
  67. }
  68. size_t rockchip_sdram_size(phys_addr_t reg)
  69. {
  70. u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
  71. size_t chipsize_mb = 0;
  72. size_t size_mb = 0;
  73. u32 ch;
  74. u32 cs1_col = 0;
  75. u32 bg = 0;
  76. u32 dbw, dram_type;
  77. u32 sys_reg2 = readl(reg);
  78. u32 sys_reg3 = readl(reg + 4);
  79. u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
  80. & SYS_REG_NUM_CH_MASK);
  81. dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
  82. debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
  83. for (ch = 0; ch < ch_num; ch++) {
  84. rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
  85. SYS_REG_RANK_MASK);
  86. cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
  87. SYS_REG_COL_MASK);
  88. cs1_col = cs0_col;
  89. bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
  90. if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
  91. SYS_REG_VERSION_MASK) == 0x2) {
  92. cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
  93. SYS_REG_CS1_COL_MASK);
  94. if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
  95. SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
  96. SYS_REG_CS0_ROW_SHIFT(ch) &
  97. SYS_REG_CS0_ROW_MASK) == 7)
  98. cs0_row = 12;
  99. else
  100. cs0_row = 13 + (sys_reg2 >>
  101. SYS_REG_CS0_ROW_SHIFT(ch) &
  102. SYS_REG_CS0_ROW_MASK) +
  103. ((sys_reg3 >>
  104. SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
  105. SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
  106. if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
  107. SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
  108. SYS_REG_CS1_ROW_SHIFT(ch) &
  109. SYS_REG_CS1_ROW_MASK) == 7)
  110. cs1_row = 12;
  111. else
  112. cs1_row = 13 + (sys_reg2 >>
  113. SYS_REG_CS1_ROW_SHIFT(ch) &
  114. SYS_REG_CS1_ROW_MASK) +
  115. ((sys_reg3 >>
  116. SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
  117. SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
  118. } else {
  119. cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
  120. SYS_REG_CS0_ROW_MASK);
  121. cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
  122. SYS_REG_CS1_ROW_MASK);
  123. }
  124. bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
  125. SYS_REG_BW_MASK));
  126. row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
  127. SYS_REG_ROW_3_4_MASK;
  128. if (dram_type == DDR4) {
  129. dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
  130. SYS_REG_DBW_MASK;
  131. bg = (dbw == 2) ? 2 : 1;
  132. }
  133. chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
  134. if (rank > 1)
  135. chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
  136. (cs0_col - cs1_col));
  137. if (row_3_4)
  138. chipsize_mb = chipsize_mb * 3 / 4;
  139. size_mb += chipsize_mb;
  140. if (rank > 1)
  141. debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
  142. cs1_row %d bw %d row_3_4 %d\n",
  143. rank, cs0_col, cs1_col, bk, cs0_row,
  144. cs1_row, bw, row_3_4);
  145. else
  146. debug("rank %d cs0_col %d bk %d cs0_row %d\
  147. bw %d row_3_4 %d\n",
  148. rank, cs0_col, bk, cs0_row,
  149. bw, row_3_4);
  150. }
  151. /*
  152. * This is workaround for issue we can't get correct size for 4GB ram
  153. * in 32bit system and available before we really need ram space
  154. * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
  155. * The size of 4GB is '0x1 00000000', and this value will be truncated
  156. * to 0 in 32bit system, and system can not get correct ram size.
  157. * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
  158. * and we are now setting SDRAM_MAX_SIZE as max available space for
  159. * ram in 4GB, so we can use this directly to workaround the issue.
  160. * TODO:
  161. * 1. update correct value for SDRAM_MAX_SIZE as what dram
  162. * controller sees.
  163. * 2. update board_get_usable_ram_top() and dram_init_banksize()
  164. * to reserve memory for peripheral space after previous update.
  165. */
  166. if (size_mb > (SDRAM_MAX_SIZE >> 20))
  167. size_mb = (SDRAM_MAX_SIZE >> 20);
  168. return (size_t)size_mb << 20;
  169. }
  170. int dram_init(void)
  171. {
  172. struct ram_info ram;
  173. struct udevice *dev;
  174. int ret;
  175. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  176. if (ret) {
  177. debug("DRAM init failed: %d\n", ret);
  178. return ret;
  179. }
  180. ret = ram_get_info(dev, &ram);
  181. if (ret) {
  182. debug("Cannot get DRAM size: %d\n", ret);
  183. return ret;
  184. }
  185. gd->ram_size = ram.size;
  186. debug("SDRAM base=%lx, size=%lx\n",
  187. (unsigned long)ram.base, (unsigned long)ram.size);
  188. return 0;
  189. }
  190. ulong board_get_usable_ram_top(ulong total_size)
  191. {
  192. unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
  193. return (gd->ram_top > top) ? top : gd->ram_top;
  194. }