arm64-common.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <fdtdec.h>
  8. #include <init.h>
  9. #include <linux/libfdt.h>
  10. #include <linux/sizes.h>
  11. #include <pci.h>
  12. #include <asm/io.h>
  13. #include <asm/system.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/soc.h>
  16. #include <asm/armv8/mmu.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /*
  19. * Not all memory is mapped in the MMU. So we need to restrict the
  20. * memory size so that U-Boot does not try to access it. Also, the
  21. * internal registers are located at 0xf000.0000 - 0xffff.ffff.
  22. * Currently only 2GiB are mapped for system memory. This is what
  23. * we pass to the U-Boot subsystem here.
  24. */
  25. #define USABLE_RAM_SIZE 0x80000000
  26. ulong board_get_usable_ram_top(ulong total_size)
  27. {
  28. if (gd->ram_size > USABLE_RAM_SIZE)
  29. return USABLE_RAM_SIZE;
  30. return gd->ram_size;
  31. }
  32. /*
  33. * On ARMv8, MBus is not configured in U-Boot. To enable compilation
  34. * of the already implemented drivers, lets add a dummy version of
  35. * this function so that linking does not fail.
  36. */
  37. const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
  38. {
  39. return NULL;
  40. }
  41. /* DRAM init code ... */
  42. #define MV_SIP_DRAM_SIZE 0x82000010
  43. static u64 a8k_dram_scan_ap_sz(void)
  44. {
  45. struct pt_regs pregs;
  46. pregs.regs[0] = MV_SIP_DRAM_SIZE;
  47. pregs.regs[1] = SOC_REGS_PHY_BASE;
  48. smc_call(&pregs);
  49. return pregs.regs[0];
  50. }
  51. static void a8k_dram_init_banksize(void)
  52. {
  53. /*
  54. * The firmware (ATF) leaves a 1G whole above the 3G mark for IO
  55. * devices. Higher RAM is mapped at 4G.
  56. *
  57. * Config 2 DRAM banks:
  58. * Bank 0 - max size 4G - 1G
  59. * Bank 1 - ram size - 4G + 1G
  60. */
  61. phys_size_t max_bank0_size = SZ_4G - SZ_1G;
  62. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  63. if (gd->ram_size <= max_bank0_size) {
  64. gd->bd->bi_dram[0].size = gd->ram_size;
  65. return;
  66. }
  67. gd->bd->bi_dram[0].size = max_bank0_size;
  68. if (CONFIG_NR_DRAM_BANKS > 1) {
  69. gd->bd->bi_dram[1].start = SZ_4G;
  70. gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
  71. }
  72. }
  73. __weak int dram_init_banksize(void)
  74. {
  75. if (CONFIG_IS_ENABLED(ARMADA_8K))
  76. a8k_dram_init_banksize();
  77. else
  78. fdtdec_setup_memory_banksize();
  79. return 0;
  80. }
  81. __weak int dram_init(void)
  82. {
  83. if (CONFIG_IS_ENABLED(ARMADA_8K)) {
  84. gd->ram_size = a8k_dram_scan_ap_sz();
  85. if (gd->ram_size != 0)
  86. return 0;
  87. }
  88. if (fdtdec_setup_mem_size_base() != 0)
  89. return -EINVAL;
  90. return 0;
  91. }
  92. int arch_cpu_init(void)
  93. {
  94. /* Nothing to do (yet) */
  95. return 0;
  96. }
  97. int arch_early_init_r(void)
  98. {
  99. struct udevice *dev;
  100. int ret;
  101. int i;
  102. /*
  103. * Loop over all MISC uclass drivers to call the comphy code
  104. * and init all CP110 devices enabled in the DT
  105. */
  106. i = 0;
  107. while (1) {
  108. /* Call the comphy code via the MISC uclass driver */
  109. ret = uclass_get_device(UCLASS_MISC, i++, &dev);
  110. /* We're done, once no further CP110 device is found */
  111. if (ret)
  112. break;
  113. }
  114. /* Cause the SATA device to do its early init */
  115. uclass_first_device(UCLASS_AHCI, &dev);
  116. #ifdef CONFIG_DM_PCI
  117. /* Trigger PCIe devices detection */
  118. pci_init();
  119. #endif
  120. return 0;
  121. }