cpsw.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * CPSW Ethernet Switch Driver
  4. *
  5. * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <net.h>
  10. #include <miiphy.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <cpsw.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/io.h>
  18. #include <phy.h>
  19. #include <asm/arch/cpu.h>
  20. #include <dm.h>
  21. #include "cpsw_mdio.h"
  22. #define BITMASK(bits) (BIT(bits) - 1)
  23. #define NUM_DESCS (PKTBUFSRX * 2)
  24. #define PKT_MIN 60
  25. #define PKT_MAX (1500 + 14 + 4 + 4)
  26. #define CLEAR_BIT 1
  27. #define GIGABITEN BIT(7)
  28. #define FULLDUPLEXEN BIT(0)
  29. #define MIIEN BIT(15)
  30. #define CTL_EXT_EN BIT(18)
  31. /* DMA Registers */
  32. #define CPDMA_TXCONTROL 0x004
  33. #define CPDMA_RXCONTROL 0x014
  34. #define CPDMA_SOFTRESET 0x01c
  35. #define CPDMA_RXFREE 0x0e0
  36. #define CPDMA_TXHDP_VER1 0x100
  37. #define CPDMA_TXHDP_VER2 0x200
  38. #define CPDMA_RXHDP_VER1 0x120
  39. #define CPDMA_RXHDP_VER2 0x220
  40. #define CPDMA_TXCP_VER1 0x140
  41. #define CPDMA_TXCP_VER2 0x240
  42. #define CPDMA_RXCP_VER1 0x160
  43. #define CPDMA_RXCP_VER2 0x260
  44. /* Descriptor mode bits */
  45. #define CPDMA_DESC_SOP BIT(31)
  46. #define CPDMA_DESC_EOP BIT(30)
  47. #define CPDMA_DESC_OWNER BIT(29)
  48. #define CPDMA_DESC_EOQ BIT(28)
  49. /*
  50. * This timeout definition is a worst-case ultra defensive measure against
  51. * unexpected controller lock ups. Ideally, we should never ever hit this
  52. * scenario in practice.
  53. */
  54. #define CPDMA_TIMEOUT 100 /* msecs */
  55. struct cpsw_regs {
  56. u32 id_ver;
  57. u32 control;
  58. u32 soft_reset;
  59. u32 stat_port_en;
  60. u32 ptype;
  61. };
  62. struct cpsw_slave_regs {
  63. u32 max_blks;
  64. u32 blk_cnt;
  65. u32 flow_thresh;
  66. u32 port_vlan;
  67. u32 tx_pri_map;
  68. #ifdef CONFIG_AM33XX
  69. u32 gap_thresh;
  70. #elif defined(CONFIG_TI814X)
  71. u32 ts_ctl;
  72. u32 ts_seq_ltype;
  73. u32 ts_vlan;
  74. #endif
  75. u32 sa_lo;
  76. u32 sa_hi;
  77. };
  78. struct cpsw_host_regs {
  79. u32 max_blks;
  80. u32 blk_cnt;
  81. u32 flow_thresh;
  82. u32 port_vlan;
  83. u32 tx_pri_map;
  84. u32 cpdma_tx_pri_map;
  85. u32 cpdma_rx_chan_map;
  86. };
  87. struct cpsw_sliver_regs {
  88. u32 id_ver;
  89. u32 mac_control;
  90. u32 mac_status;
  91. u32 soft_reset;
  92. u32 rx_maxlen;
  93. u32 __reserved_0;
  94. u32 rx_pause;
  95. u32 tx_pause;
  96. u32 __reserved_1;
  97. u32 rx_pri_map;
  98. };
  99. #define ALE_ENTRY_BITS 68
  100. #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
  101. /* ALE Registers */
  102. #define ALE_CONTROL 0x08
  103. #define ALE_UNKNOWNVLAN 0x18
  104. #define ALE_TABLE_CONTROL 0x20
  105. #define ALE_TABLE 0x34
  106. #define ALE_PORTCTL 0x40
  107. #define ALE_TABLE_WRITE BIT(31)
  108. #define ALE_TYPE_FREE 0
  109. #define ALE_TYPE_ADDR 1
  110. #define ALE_TYPE_VLAN 2
  111. #define ALE_TYPE_VLAN_ADDR 3
  112. #define ALE_UCAST_PERSISTANT 0
  113. #define ALE_UCAST_UNTOUCHED 1
  114. #define ALE_UCAST_OUI 2
  115. #define ALE_UCAST_TOUCHED 3
  116. #define ALE_MCAST_FWD 0
  117. #define ALE_MCAST_BLOCK_LEARN_FWD 1
  118. #define ALE_MCAST_FWD_LEARN 2
  119. #define ALE_MCAST_FWD_2 3
  120. enum cpsw_ale_port_state {
  121. ALE_PORT_STATE_DISABLE = 0x00,
  122. ALE_PORT_STATE_BLOCK = 0x01,
  123. ALE_PORT_STATE_LEARN = 0x02,
  124. ALE_PORT_STATE_FORWARD = 0x03,
  125. };
  126. /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
  127. #define ALE_SECURE 1
  128. #define ALE_BLOCKED 2
  129. struct cpsw_slave {
  130. struct cpsw_slave_regs *regs;
  131. struct cpsw_sliver_regs *sliver;
  132. int slave_num;
  133. u32 mac_control;
  134. struct cpsw_slave_data *data;
  135. };
  136. struct cpdma_desc {
  137. /* hardware fields */
  138. u32 hw_next;
  139. u32 hw_buffer;
  140. u32 hw_len;
  141. u32 hw_mode;
  142. /* software fields */
  143. u32 sw_buffer;
  144. u32 sw_len;
  145. };
  146. struct cpdma_chan {
  147. struct cpdma_desc *head, *tail;
  148. void *hdp, *cp, *rxfree;
  149. };
  150. /* AM33xx SoC specific definitions for the CONTROL port */
  151. #define AM33XX_GMII_SEL_MODE_MII 0
  152. #define AM33XX_GMII_SEL_MODE_RMII 1
  153. #define AM33XX_GMII_SEL_MODE_RGMII 2
  154. #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
  155. #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
  156. #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
  157. #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
  158. #define GMII_SEL_MODE_MASK 0x3
  159. #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
  160. #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
  161. #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
  162. #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
  163. #define chan_read(chan, fld) __raw_readl((chan)->fld)
  164. #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
  165. #define for_active_slave(slave, priv) \
  166. slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
  167. #define for_each_slave(slave, priv) \
  168. for (slave = (priv)->slaves; slave != (priv)->slaves + \
  169. ((priv)->data)->slaves; slave++)
  170. struct cpsw_priv {
  171. #ifdef CONFIG_DM_ETH
  172. struct udevice *dev;
  173. #else
  174. struct eth_device *dev;
  175. #endif
  176. struct cpsw_platform_data *data;
  177. int host_port;
  178. struct cpsw_regs *regs;
  179. void *dma_regs;
  180. struct cpsw_host_regs *host_port_regs;
  181. void *ale_regs;
  182. struct cpdma_desc *descs;
  183. struct cpdma_desc *desc_free;
  184. struct cpdma_chan rx_chan, tx_chan;
  185. struct cpsw_slave *slaves;
  186. struct phy_device *phydev;
  187. struct mii_dev *bus;
  188. u32 phy_mask;
  189. };
  190. static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
  191. {
  192. int idx;
  193. idx = start / 32;
  194. start -= idx * 32;
  195. idx = 2 - idx; /* flip */
  196. return (ale_entry[idx] >> start) & BITMASK(bits);
  197. }
  198. static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
  199. u32 value)
  200. {
  201. int idx;
  202. value &= BITMASK(bits);
  203. idx = start / 32;
  204. start -= idx * 32;
  205. idx = 2 - idx; /* flip */
  206. ale_entry[idx] &= ~(BITMASK(bits) << start);
  207. ale_entry[idx] |= (value << start);
  208. }
  209. #define DEFINE_ALE_FIELD(name, start, bits) \
  210. static inline int cpsw_ale_get_##name(u32 *ale_entry) \
  211. { \
  212. return cpsw_ale_get_field(ale_entry, start, bits); \
  213. } \
  214. static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
  215. { \
  216. cpsw_ale_set_field(ale_entry, start, bits, value); \
  217. }
  218. DEFINE_ALE_FIELD(entry_type, 60, 2)
  219. DEFINE_ALE_FIELD(mcast_state, 62, 2)
  220. DEFINE_ALE_FIELD(port_mask, 66, 3)
  221. DEFINE_ALE_FIELD(ucast_type, 62, 2)
  222. DEFINE_ALE_FIELD(port_num, 66, 2)
  223. DEFINE_ALE_FIELD(blocked, 65, 1)
  224. DEFINE_ALE_FIELD(secure, 64, 1)
  225. DEFINE_ALE_FIELD(mcast, 40, 1)
  226. /* The MAC address field in the ALE entry cannot be macroized as above */
  227. static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
  228. {
  229. int i;
  230. for (i = 0; i < 6; i++)
  231. addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
  232. }
  233. static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
  234. {
  235. int i;
  236. for (i = 0; i < 6; i++)
  237. cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
  238. }
  239. static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
  240. {
  241. int i;
  242. __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
  243. for (i = 0; i < ALE_ENTRY_WORDS; i++)
  244. ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
  245. return idx;
  246. }
  247. static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
  248. {
  249. int i;
  250. for (i = 0; i < ALE_ENTRY_WORDS; i++)
  251. __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
  252. __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
  253. return idx;
  254. }
  255. static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
  256. {
  257. u32 ale_entry[ALE_ENTRY_WORDS];
  258. int type, idx;
  259. for (idx = 0; idx < priv->data->ale_entries; idx++) {
  260. u8 entry_addr[6];
  261. cpsw_ale_read(priv, idx, ale_entry);
  262. type = cpsw_ale_get_entry_type(ale_entry);
  263. if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
  264. continue;
  265. cpsw_ale_get_addr(ale_entry, entry_addr);
  266. if (memcmp(entry_addr, addr, 6) == 0)
  267. return idx;
  268. }
  269. return -ENOENT;
  270. }
  271. static int cpsw_ale_match_free(struct cpsw_priv *priv)
  272. {
  273. u32 ale_entry[ALE_ENTRY_WORDS];
  274. int type, idx;
  275. for (idx = 0; idx < priv->data->ale_entries; idx++) {
  276. cpsw_ale_read(priv, idx, ale_entry);
  277. type = cpsw_ale_get_entry_type(ale_entry);
  278. if (type == ALE_TYPE_FREE)
  279. return idx;
  280. }
  281. return -ENOENT;
  282. }
  283. static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
  284. {
  285. u32 ale_entry[ALE_ENTRY_WORDS];
  286. int type, idx;
  287. for (idx = 0; idx < priv->data->ale_entries; idx++) {
  288. cpsw_ale_read(priv, idx, ale_entry);
  289. type = cpsw_ale_get_entry_type(ale_entry);
  290. if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
  291. continue;
  292. if (cpsw_ale_get_mcast(ale_entry))
  293. continue;
  294. type = cpsw_ale_get_ucast_type(ale_entry);
  295. if (type != ALE_UCAST_PERSISTANT &&
  296. type != ALE_UCAST_OUI)
  297. return idx;
  298. }
  299. return -ENOENT;
  300. }
  301. static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
  302. int port, int flags)
  303. {
  304. u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
  305. int idx;
  306. cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
  307. cpsw_ale_set_addr(ale_entry, addr);
  308. cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
  309. cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
  310. cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
  311. cpsw_ale_set_port_num(ale_entry, port);
  312. idx = cpsw_ale_match_addr(priv, addr);
  313. if (idx < 0)
  314. idx = cpsw_ale_match_free(priv);
  315. if (idx < 0)
  316. idx = cpsw_ale_find_ageable(priv);
  317. if (idx < 0)
  318. return -ENOMEM;
  319. cpsw_ale_write(priv, idx, ale_entry);
  320. return 0;
  321. }
  322. static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
  323. int port_mask)
  324. {
  325. u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
  326. int idx, mask;
  327. idx = cpsw_ale_match_addr(priv, addr);
  328. if (idx >= 0)
  329. cpsw_ale_read(priv, idx, ale_entry);
  330. cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
  331. cpsw_ale_set_addr(ale_entry, addr);
  332. cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
  333. mask = cpsw_ale_get_port_mask(ale_entry);
  334. port_mask |= mask;
  335. cpsw_ale_set_port_mask(ale_entry, port_mask);
  336. if (idx < 0)
  337. idx = cpsw_ale_match_free(priv);
  338. if (idx < 0)
  339. idx = cpsw_ale_find_ageable(priv);
  340. if (idx < 0)
  341. return -ENOMEM;
  342. cpsw_ale_write(priv, idx, ale_entry);
  343. return 0;
  344. }
  345. static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
  346. {
  347. u32 tmp, mask = BIT(bit);
  348. tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
  349. tmp &= ~mask;
  350. tmp |= val ? mask : 0;
  351. __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
  352. }
  353. #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
  354. #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
  355. #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
  356. static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
  357. int val)
  358. {
  359. int offset = ALE_PORTCTL + 4 * port;
  360. u32 tmp, mask = 0x3;
  361. tmp = __raw_readl(priv->ale_regs + offset);
  362. tmp &= ~mask;
  363. tmp |= val & mask;
  364. __raw_writel(tmp, priv->ale_regs + offset);
  365. }
  366. /* Set a self-clearing bit in a register, and wait for it to clear */
  367. static inline void setbit_and_wait_for_clear32(void *addr)
  368. {
  369. __raw_writel(CLEAR_BIT, addr);
  370. while (__raw_readl(addr) & CLEAR_BIT)
  371. ;
  372. }
  373. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  374. ((mac)[2] << 16) | ((mac)[3] << 24))
  375. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  376. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  377. struct cpsw_priv *priv)
  378. {
  379. #ifdef CONFIG_DM_ETH
  380. struct eth_pdata *pdata = dev_get_platdata(priv->dev);
  381. writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
  382. writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
  383. #else
  384. __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
  385. __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
  386. #endif
  387. }
  388. static int cpsw_slave_update_link(struct cpsw_slave *slave,
  389. struct cpsw_priv *priv, int *link)
  390. {
  391. struct phy_device *phy;
  392. u32 mac_control = 0;
  393. int ret = -ENODEV;
  394. phy = priv->phydev;
  395. if (!phy)
  396. goto out;
  397. ret = phy_startup(phy);
  398. if (ret)
  399. goto out;
  400. if (link)
  401. *link = phy->link;
  402. if (phy->link) { /* link up */
  403. mac_control = priv->data->mac_control;
  404. if (phy->speed == 1000)
  405. mac_control |= GIGABITEN;
  406. if (phy->duplex == DUPLEX_FULL)
  407. mac_control |= FULLDUPLEXEN;
  408. if (phy->speed == 100)
  409. mac_control |= MIIEN;
  410. if (phy->speed == 10 && phy_interface_is_rgmii(phy))
  411. mac_control |= CTL_EXT_EN;
  412. }
  413. if (mac_control == slave->mac_control)
  414. goto out;
  415. if (mac_control) {
  416. printf("link up on port %d, speed %d, %s duplex\n",
  417. slave->slave_num, phy->speed,
  418. (phy->duplex == DUPLEX_FULL) ? "full" : "half");
  419. } else {
  420. printf("link down on port %d\n", slave->slave_num);
  421. }
  422. __raw_writel(mac_control, &slave->sliver->mac_control);
  423. slave->mac_control = mac_control;
  424. out:
  425. return ret;
  426. }
  427. static int cpsw_update_link(struct cpsw_priv *priv)
  428. {
  429. int ret = -ENODEV;
  430. struct cpsw_slave *slave;
  431. for_active_slave(slave, priv)
  432. ret = cpsw_slave_update_link(slave, priv, NULL);
  433. return ret;
  434. }
  435. static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  436. {
  437. if (priv->host_port == 0)
  438. return slave_num + 1;
  439. else
  440. return slave_num;
  441. }
  442. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  443. {
  444. u32 slave_port;
  445. setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
  446. /* setup priority mapping */
  447. __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
  448. __raw_writel(0x33221100, &slave->regs->tx_pri_map);
  449. /* setup max packet size, and mac address */
  450. __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
  451. cpsw_set_slave_mac(slave, priv);
  452. slave->mac_control = 0; /* no link yet */
  453. /* enable forwarding */
  454. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  455. cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
  456. cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
  457. priv->phy_mask |= 1 << slave->data->phy_addr;
  458. }
  459. static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
  460. {
  461. struct cpdma_desc *desc = priv->desc_free;
  462. if (desc)
  463. priv->desc_free = desc_read_ptr(desc, hw_next);
  464. return desc;
  465. }
  466. static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
  467. {
  468. if (desc) {
  469. desc_write(desc, hw_next, priv->desc_free);
  470. priv->desc_free = desc;
  471. }
  472. }
  473. static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
  474. void *buffer, int len)
  475. {
  476. struct cpdma_desc *desc, *prev;
  477. u32 mode;
  478. desc = cpdma_desc_alloc(priv);
  479. if (!desc)
  480. return -ENOMEM;
  481. if (len < PKT_MIN)
  482. len = PKT_MIN;
  483. mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
  484. desc_write(desc, hw_next, 0);
  485. desc_write(desc, hw_buffer, buffer);
  486. desc_write(desc, hw_len, len);
  487. desc_write(desc, hw_mode, mode | len);
  488. desc_write(desc, sw_buffer, buffer);
  489. desc_write(desc, sw_len, len);
  490. if (!chan->head) {
  491. /* simple case - first packet enqueued */
  492. chan->head = desc;
  493. chan->tail = desc;
  494. chan_write(chan, hdp, desc);
  495. goto done;
  496. }
  497. /* not the first packet - enqueue at the tail */
  498. prev = chan->tail;
  499. desc_write(prev, hw_next, desc);
  500. chan->tail = desc;
  501. /* next check if EOQ has been triggered already */
  502. if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
  503. chan_write(chan, hdp, desc);
  504. done:
  505. if (chan->rxfree)
  506. chan_write(chan, rxfree, 1);
  507. return 0;
  508. }
  509. static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
  510. void **buffer, int *len)
  511. {
  512. struct cpdma_desc *desc = chan->head;
  513. u32 status;
  514. if (!desc)
  515. return -ENOENT;
  516. status = desc_read(desc, hw_mode);
  517. if (len)
  518. *len = status & 0x7ff;
  519. if (buffer)
  520. *buffer = desc_read_ptr(desc, sw_buffer);
  521. if (status & CPDMA_DESC_OWNER) {
  522. if (chan_read(chan, hdp) == 0) {
  523. if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
  524. chan_write(chan, hdp, desc);
  525. }
  526. return -EBUSY;
  527. }
  528. chan->head = desc_read_ptr(desc, hw_next);
  529. chan_write(chan, cp, desc);
  530. cpdma_desc_free(priv, desc);
  531. return 0;
  532. }
  533. static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
  534. {
  535. struct cpsw_slave *slave;
  536. int i, ret;
  537. /* soft reset the controller and initialize priv */
  538. setbit_and_wait_for_clear32(&priv->regs->soft_reset);
  539. /* initialize and reset the address lookup engine */
  540. cpsw_ale_enable(priv, 1);
  541. cpsw_ale_clear(priv, 1);
  542. cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
  543. /* setup host port priority mapping */
  544. __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
  545. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  546. /* disable priority elevation and enable statistics on all ports */
  547. __raw_writel(0, &priv->regs->ptype);
  548. /* enable statistics collection only on the host port */
  549. __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
  550. __raw_writel(0x7, &priv->regs->stat_port_en);
  551. cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
  552. cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
  553. cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
  554. for_active_slave(slave, priv)
  555. cpsw_slave_init(slave, priv);
  556. ret = cpsw_update_link(priv);
  557. if (ret)
  558. goto out;
  559. /* init descriptor pool */
  560. for (i = 0; i < NUM_DESCS; i++) {
  561. desc_write(&priv->descs[i], hw_next,
  562. (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
  563. }
  564. priv->desc_free = &priv->descs[0];
  565. /* initialize channels */
  566. if (priv->data->version == CPSW_CTRL_VERSION_2) {
  567. memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
  568. priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
  569. priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
  570. priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
  571. memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
  572. priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
  573. priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
  574. } else {
  575. memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
  576. priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
  577. priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
  578. priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
  579. memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
  580. priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
  581. priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
  582. }
  583. /* clear dma state */
  584. setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
  585. if (priv->data->version == CPSW_CTRL_VERSION_2) {
  586. for (i = 0; i < priv->data->channels; i++) {
  587. __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
  588. * i);
  589. __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
  590. * i);
  591. __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
  592. * i);
  593. __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
  594. * i);
  595. __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
  596. * i);
  597. }
  598. } else {
  599. for (i = 0; i < priv->data->channels; i++) {
  600. __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
  601. * i);
  602. __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
  603. * i);
  604. __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
  605. * i);
  606. __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
  607. * i);
  608. __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
  609. * i);
  610. }
  611. }
  612. __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
  613. __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
  614. /* submit rx descs */
  615. for (i = 0; i < PKTBUFSRX; i++) {
  616. ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
  617. PKTSIZE);
  618. if (ret < 0) {
  619. printf("error %d submitting rx desc\n", ret);
  620. break;
  621. }
  622. }
  623. out:
  624. return ret;
  625. }
  626. static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
  627. {
  628. int timeout = CPDMA_TIMEOUT;
  629. /* reap completed packets */
  630. while (timeout-- &&
  631. (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
  632. ;
  633. return timeout;
  634. }
  635. static void _cpsw_halt(struct cpsw_priv *priv)
  636. {
  637. cpsw_reap_completed_packets(priv);
  638. writel(0, priv->dma_regs + CPDMA_TXCONTROL);
  639. writel(0, priv->dma_regs + CPDMA_RXCONTROL);
  640. /* soft reset the controller and initialize priv */
  641. setbit_and_wait_for_clear32(&priv->regs->soft_reset);
  642. /* clear dma state */
  643. setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
  644. }
  645. static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
  646. {
  647. int timeout;
  648. flush_dcache_range((unsigned long)packet,
  649. (unsigned long)packet + ALIGN(length, PKTALIGN));
  650. timeout = cpsw_reap_completed_packets(priv);
  651. if (timeout == -1) {
  652. printf("cpdma_process timeout\n");
  653. return -ETIMEDOUT;
  654. }
  655. return cpdma_submit(priv, &priv->tx_chan, packet, length);
  656. }
  657. static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
  658. {
  659. void *buffer;
  660. int len;
  661. int ret;
  662. ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
  663. if (ret < 0)
  664. return ret;
  665. invalidate_dcache_range((unsigned long)buffer,
  666. (unsigned long)buffer + PKTSIZE_ALIGN);
  667. *pkt = buffer;
  668. return len;
  669. }
  670. static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
  671. struct cpsw_priv *priv)
  672. {
  673. void *regs = priv->regs;
  674. struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
  675. slave->slave_num = slave_num;
  676. slave->data = data;
  677. slave->regs = regs + data->slave_reg_ofs;
  678. slave->sliver = regs + data->sliver_reg_ofs;
  679. }
  680. static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
  681. {
  682. struct phy_device *phydev;
  683. u32 supported = PHY_GBIT_FEATURES;
  684. int ret;
  685. phydev = phy_connect(priv->bus,
  686. slave->data->phy_addr,
  687. priv->dev,
  688. slave->data->phy_if);
  689. if (!phydev)
  690. return -1;
  691. phydev->supported &= supported;
  692. if (slave->data->max_speed) {
  693. ret = phy_set_supported(phydev, slave->data->max_speed);
  694. if (ret)
  695. return ret;
  696. dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
  697. slave->slave_num + 1, slave->data->max_speed);
  698. }
  699. phydev->advertising = phydev->supported;
  700. #ifdef CONFIG_DM_ETH
  701. if (ofnode_valid(slave->data->phy_of_handle))
  702. phydev->node = slave->data->phy_of_handle;
  703. #endif
  704. priv->phydev = phydev;
  705. phy_config(phydev);
  706. return 1;
  707. }
  708. static void cpsw_phy_addr_update(struct cpsw_priv *priv)
  709. {
  710. struct cpsw_platform_data *data = priv->data;
  711. u16 alive = cpsw_mdio_get_alive(priv->bus);
  712. int active = data->active_slave;
  713. int new_addr = ffs(alive) - 1;
  714. /*
  715. * If there is only one phy alive and its address does not match
  716. * that of active slave, then phy address can safely be updated.
  717. */
  718. if (hweight16(alive) == 1 &&
  719. data->slave_data[active].phy_addr != new_addr) {
  720. printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
  721. active, data->slave_data[active].phy_addr, new_addr);
  722. data->slave_data[active].phy_addr = new_addr;
  723. }
  724. }
  725. int _cpsw_register(struct cpsw_priv *priv)
  726. {
  727. struct cpsw_slave *slave;
  728. struct cpsw_platform_data *data = priv->data;
  729. void *regs = (void *)data->cpsw_base;
  730. priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
  731. if (!priv->slaves) {
  732. return -ENOMEM;
  733. }
  734. priv->host_port = data->host_port_num;
  735. priv->regs = regs;
  736. priv->host_port_regs = regs + data->host_port_reg_ofs;
  737. priv->dma_regs = regs + data->cpdma_reg_ofs;
  738. priv->ale_regs = regs + data->ale_reg_ofs;
  739. priv->descs = (void *)regs + data->bd_ram_ofs;
  740. int idx = 0;
  741. for_each_slave(slave, priv) {
  742. cpsw_slave_setup(slave, idx, priv);
  743. idx = idx + 1;
  744. }
  745. priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
  746. if (!priv->bus)
  747. return -EFAULT;
  748. cpsw_phy_addr_update(priv);
  749. for_active_slave(slave, priv)
  750. cpsw_phy_init(priv, slave);
  751. return 0;
  752. }
  753. #ifndef CONFIG_DM_ETH
  754. static int cpsw_init(struct eth_device *dev, bd_t *bis)
  755. {
  756. struct cpsw_priv *priv = dev->priv;
  757. return _cpsw_init(priv, dev->enetaddr);
  758. }
  759. static void cpsw_halt(struct eth_device *dev)
  760. {
  761. struct cpsw_priv *priv = dev->priv;
  762. return _cpsw_halt(priv);
  763. }
  764. static int cpsw_send(struct eth_device *dev, void *packet, int length)
  765. {
  766. struct cpsw_priv *priv = dev->priv;
  767. return _cpsw_send(priv, packet, length);
  768. }
  769. static int cpsw_recv(struct eth_device *dev)
  770. {
  771. struct cpsw_priv *priv = dev->priv;
  772. uchar *pkt = NULL;
  773. int len;
  774. len = _cpsw_recv(priv, &pkt);
  775. if (len > 0) {
  776. net_process_received_packet(pkt, len);
  777. cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
  778. }
  779. return len;
  780. }
  781. int cpsw_register(struct cpsw_platform_data *data)
  782. {
  783. struct cpsw_priv *priv;
  784. struct eth_device *dev;
  785. int ret;
  786. dev = calloc(sizeof(*dev), 1);
  787. if (!dev)
  788. return -ENOMEM;
  789. priv = calloc(sizeof(*priv), 1);
  790. if (!priv) {
  791. free(dev);
  792. return -ENOMEM;
  793. }
  794. priv->dev = dev;
  795. priv->data = data;
  796. strcpy(dev->name, "cpsw");
  797. dev->iobase = 0;
  798. dev->init = cpsw_init;
  799. dev->halt = cpsw_halt;
  800. dev->send = cpsw_send;
  801. dev->recv = cpsw_recv;
  802. dev->priv = priv;
  803. eth_register(dev);
  804. ret = _cpsw_register(priv);
  805. if (ret < 0) {
  806. eth_unregister(dev);
  807. free(dev);
  808. free(priv);
  809. return ret;
  810. }
  811. return 1;
  812. }
  813. #else
  814. static int cpsw_eth_start(struct udevice *dev)
  815. {
  816. struct eth_pdata *pdata = dev_get_platdata(dev);
  817. struct cpsw_priv *priv = dev_get_priv(dev);
  818. return _cpsw_init(priv, pdata->enetaddr);
  819. }
  820. static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
  821. {
  822. struct cpsw_priv *priv = dev_get_priv(dev);
  823. return _cpsw_send(priv, packet, length);
  824. }
  825. static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  826. {
  827. struct cpsw_priv *priv = dev_get_priv(dev);
  828. return _cpsw_recv(priv, packetp);
  829. }
  830. static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
  831. int length)
  832. {
  833. struct cpsw_priv *priv = dev_get_priv(dev);
  834. return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
  835. }
  836. static void cpsw_eth_stop(struct udevice *dev)
  837. {
  838. struct cpsw_priv *priv = dev_get_priv(dev);
  839. return _cpsw_halt(priv);
  840. }
  841. static const struct eth_ops cpsw_eth_ops = {
  842. .start = cpsw_eth_start,
  843. .send = cpsw_eth_send,
  844. .recv = cpsw_eth_recv,
  845. .free_pkt = cpsw_eth_free_pkt,
  846. .stop = cpsw_eth_stop,
  847. };
  848. static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
  849. phy_interface_t phy_mode)
  850. {
  851. u32 reg;
  852. u32 mask;
  853. u32 mode = 0;
  854. bool rgmii_id = false;
  855. int slave = priv->data->active_slave;
  856. reg = readl(priv->data->gmii_sel);
  857. switch (phy_mode) {
  858. case PHY_INTERFACE_MODE_RMII:
  859. mode = AM33XX_GMII_SEL_MODE_RMII;
  860. break;
  861. case PHY_INTERFACE_MODE_RGMII:
  862. case PHY_INTERFACE_MODE_RGMII_RXID:
  863. mode = AM33XX_GMII_SEL_MODE_RGMII;
  864. break;
  865. case PHY_INTERFACE_MODE_RGMII_ID:
  866. case PHY_INTERFACE_MODE_RGMII_TXID:
  867. mode = AM33XX_GMII_SEL_MODE_RGMII;
  868. rgmii_id = true;
  869. break;
  870. case PHY_INTERFACE_MODE_MII:
  871. default:
  872. mode = AM33XX_GMII_SEL_MODE_MII;
  873. break;
  874. };
  875. mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
  876. mode <<= slave * 2;
  877. if (priv->data->rmii_clock_external) {
  878. if (slave == 0)
  879. mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
  880. else
  881. mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
  882. }
  883. if (rgmii_id) {
  884. if (slave == 0)
  885. mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
  886. else
  887. mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
  888. }
  889. reg &= ~mask;
  890. reg |= mode;
  891. writel(reg, priv->data->gmii_sel);
  892. }
  893. static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
  894. phy_interface_t phy_mode)
  895. {
  896. u32 reg;
  897. u32 mask;
  898. u32 mode = 0;
  899. int slave = priv->data->active_slave;
  900. reg = readl(priv->data->gmii_sel);
  901. switch (phy_mode) {
  902. case PHY_INTERFACE_MODE_RMII:
  903. mode = AM33XX_GMII_SEL_MODE_RMII;
  904. break;
  905. case PHY_INTERFACE_MODE_RGMII:
  906. case PHY_INTERFACE_MODE_RGMII_ID:
  907. case PHY_INTERFACE_MODE_RGMII_RXID:
  908. case PHY_INTERFACE_MODE_RGMII_TXID:
  909. mode = AM33XX_GMII_SEL_MODE_RGMII;
  910. break;
  911. case PHY_INTERFACE_MODE_MII:
  912. default:
  913. mode = AM33XX_GMII_SEL_MODE_MII;
  914. break;
  915. };
  916. switch (slave) {
  917. case 0:
  918. mask = GMII_SEL_MODE_MASK;
  919. break;
  920. case 1:
  921. mask = GMII_SEL_MODE_MASK << 4;
  922. mode <<= 4;
  923. break;
  924. default:
  925. dev_err(priv->dev, "invalid slave number...\n");
  926. return;
  927. }
  928. if (priv->data->rmii_clock_external)
  929. dev_err(priv->dev, "RMII External clock is not supported\n");
  930. reg &= ~mask;
  931. reg |= mode;
  932. writel(reg, priv->data->gmii_sel);
  933. }
  934. static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
  935. phy_interface_t phy_mode)
  936. {
  937. if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
  938. cpsw_gmii_sel_am3352(priv, phy_mode);
  939. if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
  940. cpsw_gmii_sel_am3352(priv, phy_mode);
  941. else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
  942. cpsw_gmii_sel_dra7xx(priv, phy_mode);
  943. }
  944. static int cpsw_eth_probe(struct udevice *dev)
  945. {
  946. struct cpsw_priv *priv = dev_get_priv(dev);
  947. struct eth_pdata *pdata = dev_get_platdata(dev);
  948. priv->dev = dev;
  949. priv->data = pdata->priv_pdata;
  950. ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
  951. /* Select phy interface in control module */
  952. cpsw_phy_sel(priv, priv->data->phy_sel_compat,
  953. pdata->phy_interface);
  954. return _cpsw_register(priv);
  955. }
  956. #if CONFIG_IS_ENABLED(OF_CONTROL)
  957. static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
  958. int slave_index, ofnode subnode)
  959. {
  960. struct ofnode_phandle_args out_args;
  961. struct cpsw_slave_data *slave_data;
  962. const char *phy_mode;
  963. u32 phy_id[2];
  964. int ret;
  965. slave_data = &data->slave_data[slave_index];
  966. phy_mode = ofnode_read_string(subnode, "phy-mode");
  967. if (phy_mode)
  968. slave_data->phy_if = phy_get_interface_by_name(phy_mode);
  969. ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
  970. NULL, 0, 0, &out_args);
  971. if (!ret) {
  972. slave_data->phy_of_handle = out_args.node;
  973. ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
  974. &slave_data->phy_addr);
  975. if (ret)
  976. printf("error: phy addr not found in dt\n");
  977. } else {
  978. ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
  979. if (ret)
  980. printf("error: phy_id read failed\n");
  981. }
  982. slave_data->max_speed = ofnode_read_s32_default(subnode,
  983. "max-speed", 0);
  984. }
  985. static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
  986. {
  987. struct eth_pdata *pdata = dev_get_platdata(dev);
  988. struct cpsw_platform_data *data;
  989. struct gpio_desc *mode_gpios;
  990. int slave_index = 0;
  991. int num_mode_gpios;
  992. ofnode subnode;
  993. int ret;
  994. data = calloc(1, sizeof(struct cpsw_platform_data));
  995. pdata->priv_pdata = data;
  996. pdata->iobase = dev_read_addr(dev);
  997. data->version = CPSW_CTRL_VERSION_2;
  998. data->bd_ram_ofs = CPSW_BD_OFFSET;
  999. data->ale_reg_ofs = CPSW_ALE_OFFSET;
  1000. data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
  1001. data->mdio_div = CPSW_MDIO_DIV;
  1002. data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
  1003. pdata->phy_interface = -1;
  1004. data->cpsw_base = pdata->iobase;
  1005. ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
  1006. if (ret) {
  1007. printf("error: cpdma_channels not found in dt\n");
  1008. return ret;
  1009. }
  1010. ret = dev_read_s32(dev, "slaves", &data->slaves);
  1011. if (ret) {
  1012. printf("error: slaves not found in dt\n");
  1013. return ret;
  1014. }
  1015. data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
  1016. data->slaves);
  1017. ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
  1018. if (ret) {
  1019. printf("error: ale_entries not found in dt\n");
  1020. return ret;
  1021. }
  1022. ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
  1023. if (ret) {
  1024. printf("error: bd_ram_size not found in dt\n");
  1025. return ret;
  1026. }
  1027. ret = dev_read_u32(dev, "mac_control", &data->mac_control);
  1028. if (ret) {
  1029. printf("error: ale_entries not found in dt\n");
  1030. return ret;
  1031. }
  1032. num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
  1033. if (num_mode_gpios > 0) {
  1034. mode_gpios = malloc(sizeof(struct gpio_desc) *
  1035. num_mode_gpios);
  1036. gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
  1037. num_mode_gpios, GPIOD_IS_OUT);
  1038. free(mode_gpios);
  1039. }
  1040. data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
  1041. ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
  1042. const char *name;
  1043. name = ofnode_get_name(subnode);
  1044. if (!strncmp(name, "mdio", 4)) {
  1045. data->mdio_base = ofnode_get_addr(subnode);
  1046. if (data->mdio_base == FDT_ADDR_T_NONE) {
  1047. pr_err("Not able to get MDIO address space\n");
  1048. return -ENOENT;
  1049. }
  1050. }
  1051. if (!strncmp(name, "slave", 5)) {
  1052. if (slave_index >= data->slaves)
  1053. continue;
  1054. cpsw_eth_of_parse_slave(data, slave_index, subnode);
  1055. slave_index++;
  1056. }
  1057. if (!strncmp(name, "cpsw-phy-sel", 12)) {
  1058. data->gmii_sel = ofnode_get_addr(subnode);
  1059. if (data->gmii_sel == FDT_ADDR_T_NONE) {
  1060. pr_err("Not able to get gmii_sel reg address\n");
  1061. return -ENOENT;
  1062. }
  1063. if (ofnode_read_bool(subnode, "rmii-clock-ext"))
  1064. data->rmii_clock_external = true;
  1065. data->phy_sel_compat = ofnode_read_string(subnode,
  1066. "compatible");
  1067. if (!data->phy_sel_compat) {
  1068. pr_err("Not able to get gmii_sel compatible\n");
  1069. return -ENOENT;
  1070. }
  1071. }
  1072. }
  1073. data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
  1074. data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
  1075. if (data->slaves == 2) {
  1076. data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
  1077. data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
  1078. }
  1079. ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
  1080. if (ret < 0) {
  1081. pr_err("cpsw read efuse mac failed\n");
  1082. return ret;
  1083. }
  1084. pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
  1085. if (pdata->phy_interface == -1) {
  1086. debug("%s: Invalid PHY interface '%s'\n", __func__,
  1087. phy_string_for_interface(pdata->phy_interface));
  1088. return -EINVAL;
  1089. }
  1090. return 0;
  1091. }
  1092. static const struct udevice_id cpsw_eth_ids[] = {
  1093. { .compatible = "ti,cpsw" },
  1094. { .compatible = "ti,am335x-cpsw" },
  1095. { }
  1096. };
  1097. #endif
  1098. int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
  1099. {
  1100. struct cpsw_priv *priv = dev_get_priv(dev);
  1101. struct cpsw_platform_data *data = priv->data;
  1102. return data->slave_data[slave].phy_addr;
  1103. }
  1104. U_BOOT_DRIVER(eth_cpsw) = {
  1105. .name = "eth_cpsw",
  1106. .id = UCLASS_ETH,
  1107. #if CONFIG_IS_ENABLED(OF_CONTROL)
  1108. .of_match = cpsw_eth_ids,
  1109. .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
  1110. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1111. #endif
  1112. .probe = cpsw_eth_probe,
  1113. .ops = &cpsw_eth_ops,
  1114. .priv_auto_alloc_size = sizeof(struct cpsw_priv),
  1115. .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
  1116. };
  1117. #endif /* CONFIG_DM_ETH */