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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
  6. * Copyright (c) 2008 Nuovation System Designs, LLC
  7. * Grant Erickson <gerickson@nuovations.com>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0 IBM-pibs
  10. */
  11. /*
  12. * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
  13. *
  14. * The following description only applies to the NOR flash style booting.
  15. * NAND booting is different. For more details about NAND booting on 4xx
  16. * take a look at doc/README.nand-boot-ppc440.
  17. *
  18. * The CPU starts at address 0xfffffffc (last word in the address space).
  19. * The U-Boot image therefore has to be located in the "upper" area of the
  20. * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
  21. * the boot chip-select (CS0) is quite big and covers this area. On the
  22. * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
  23. * reconfigure this CS0 (and other chip-selects as well when configured
  24. * this way) in the boot process to the "correct" values matching the
  25. * board layout.
  26. */
  27. #include <asm-offsets.h>
  28. #include <config.h>
  29. #include <asm/ppc4xx.h>
  30. #include <version.h>
  31. #include <ppc_asm.tmpl>
  32. #include <ppc_defs.h>
  33. #include <asm/cache.h>
  34. #include <asm/mmu.h>
  35. #include <asm/ppc4xx-isram.h>
  36. #ifdef CONFIG_SYS_INIT_DCACHE_CS
  37. # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
  38. # define PBxAP PB1AP
  39. # define PBxCR PB0CR
  40. # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
  41. # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
  42. # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
  43. # endif
  44. # endif
  45. # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
  46. # define PBxAP PB1AP
  47. # define PBxCR PB1CR
  48. # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
  49. # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
  50. # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
  51. # endif
  52. # endif
  53. # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
  54. # define PBxAP PB2AP
  55. # define PBxCR PB2CR
  56. # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
  57. # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
  58. # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
  59. # endif
  60. # endif
  61. # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
  62. # define PBxAP PB3AP
  63. # define PBxCR PB3CR
  64. # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
  65. # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
  66. # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
  67. # endif
  68. # endif
  69. # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
  70. # define PBxAP PB4AP
  71. # define PBxCR PB4CR
  72. # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
  73. # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
  74. # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
  75. # endif
  76. # endif
  77. # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
  78. # define PBxAP PB5AP
  79. # define PBxCR PB5CR
  80. # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
  81. # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
  82. # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
  83. # endif
  84. # endif
  85. # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
  86. # define PBxAP PB6AP
  87. # define PBxCR PB6CR
  88. # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
  89. # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
  90. # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
  91. # endif
  92. # endif
  93. # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
  94. # define PBxAP PB7AP
  95. # define PBxCR PB7CR
  96. # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
  97. # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
  98. # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
  99. # endif
  100. # endif
  101. # ifndef PBxAP_VAL
  102. # define PBxAP_VAL 0
  103. # endif
  104. # ifndef PBxCR_VAL
  105. # define PBxCR_VAL 0
  106. # endif
  107. /*
  108. * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
  109. * used as temporary stack pointer for the primordial stack
  110. */
  111. # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
  112. # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
  113. EBC_BXAP_TWT_ENCODE(7) | \
  114. EBC_BXAP_BCE_DISABLE | \
  115. EBC_BXAP_BCT_2TRANS | \
  116. EBC_BXAP_CSN_ENCODE(0) | \
  117. EBC_BXAP_OEN_ENCODE(0) | \
  118. EBC_BXAP_WBN_ENCODE(0) | \
  119. EBC_BXAP_WBF_ENCODE(0) | \
  120. EBC_BXAP_TH_ENCODE(2) | \
  121. EBC_BXAP_RE_DISABLED | \
  122. EBC_BXAP_SOR_NONDELAYED | \
  123. EBC_BXAP_BEM_WRITEONLY | \
  124. EBC_BXAP_PEN_DISABLED)
  125. # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
  126. # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
  127. # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
  128. EBC_BXCR_BS_64MB | \
  129. EBC_BXCR_BU_RW | \
  130. EBC_BXCR_BW_16BIT)
  131. # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
  132. # ifndef CONFIG_SYS_INIT_RAM_PATTERN
  133. # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
  134. # endif
  135. #endif /* CONFIG_SYS_INIT_DCACHE_CS */
  136. #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
  137. #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
  138. #endif
  139. /*
  140. * Unless otherwise overridden, enable two 128MB cachable instruction regions
  141. * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
  142. * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
  143. */
  144. #if !defined(CONFIG_SYS_FLASH_BASE)
  145. /* If not already defined, set it to the "last" 128MByte region */
  146. # define CONFIG_SYS_FLASH_BASE 0xf8000000
  147. #endif
  148. #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
  149. # define CONFIG_SYS_ICACHE_SACR_VALUE \
  150. (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
  151. PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
  152. PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
  153. #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
  154. #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
  155. # define CONFIG_SYS_DCACHE_SACR_VALUE \
  156. (0x00000000)
  157. #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
  158. #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
  159. #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
  160. #endif
  161. #define function_prolog(func_name) .text; \
  162. .align 2; \
  163. .globl func_name; \
  164. func_name:
  165. #define function_epilog(func_name) .type func_name,@function; \
  166. .size func_name,.-func_name
  167. /* We don't want the MMU yet.
  168. */
  169. #undef MSR_KERNEL
  170. #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  171. .extern ext_bus_cntlr_init
  172. /*
  173. * Set up GOT: Global Offset Table
  174. *
  175. * Use r12 to access the GOT
  176. */
  177. #if !defined(CONFIG_SPL_BUILD)
  178. START_GOT
  179. GOT_ENTRY(_GOT2_TABLE_)
  180. GOT_ENTRY(_FIXUP_TABLE_)
  181. GOT_ENTRY(_start)
  182. GOT_ENTRY(_start_of_vectors)
  183. GOT_ENTRY(_end_of_vectors)
  184. GOT_ENTRY(transfer_to_handler)
  185. GOT_ENTRY(__init_end)
  186. GOT_ENTRY(__bss_end)
  187. GOT_ENTRY(__bss_start)
  188. END_GOT
  189. #endif /* CONFIG_SPL_BUILD */
  190. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
  191. /*
  192. * 4xx RAM-booting U-Boot image is started from offset 0
  193. */
  194. .text
  195. bl _start_440
  196. #endif
  197. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  198. /*
  199. * This is the entry of the real U-Boot from a board port
  200. * that supports SPL booting on the PPC4xx. We only need
  201. * to call board_init_f() here. Everything else has already
  202. * been done in the SPL u-boot version.
  203. */
  204. GET_GOT /* initialize GOT access */
  205. bl board_init_f /* run 1st part of board init code (in Flash)*/
  206. /* NOTREACHED - board_init_f() does not return */
  207. #endif
  208. /*
  209. * 440 Startup -- on reset only the top 4k of the effective
  210. * address space is mapped in by an entry in the instruction
  211. * and data shadow TLB. The .bootpg section is located in the
  212. * top 4k & does only what's necessary to map in the the rest
  213. * of the boot rom. Once the boot rom is mapped in we can
  214. * proceed with normal startup.
  215. *
  216. * NOTE: CS0 only covers the top 2MB of the effective address
  217. * space after reset.
  218. */
  219. #if defined(CONFIG_440)
  220. .section .bootpg,"ax"
  221. .globl _start_440
  222. /**************************************************************************/
  223. _start_440:
  224. /*--------------------------------------------------------------------+
  225. | 440EPX BUP Change - Hardware team request
  226. +--------------------------------------------------------------------*/
  227. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  228. sync
  229. nop
  230. nop
  231. #endif
  232. /*----------------------------------------------------------------+
  233. | Core bug fix. Clear the esr
  234. +-----------------------------------------------------------------*/
  235. li r0,0
  236. mtspr SPRN_ESR,r0
  237. /*----------------------------------------------------------------*/
  238. /* Clear and set up some registers. */
  239. /*----------------------------------------------------------------*/
  240. iccci r0,r0 /* NOTE: operands not used for 440 */
  241. dccci r0,r0 /* NOTE: operands not used for 440 */
  242. sync
  243. li r0,0
  244. mtspr SPRN_SRR0,r0
  245. mtspr SPRN_SRR1,r0
  246. mtspr SPRN_CSRR0,r0
  247. mtspr SPRN_CSRR1,r0
  248. /* NOTE: 440GX adds machine check status regs */
  249. #if defined(CONFIG_440) && !defined(CONFIG_440GP)
  250. mtspr SPRN_MCSRR0,r0
  251. mtspr SPRN_MCSRR1,r0
  252. mfspr r1,SPRN_MCSR
  253. mtspr SPRN_MCSR,r1
  254. #endif
  255. /*----------------------------------------------------------------*/
  256. /* CCR0 init */
  257. /*----------------------------------------------------------------*/
  258. /* Disable store gathering & broadcast, guarantee inst/data
  259. * cache block touch, force load/store alignment
  260. * (see errata 1.12: 440_33)
  261. */
  262. lis r1,0x0030 /* store gathering & broadcast disable */
  263. ori r1,r1,0x6000 /* cache touch */
  264. mtspr SPRN_CCR0,r1
  265. /*----------------------------------------------------------------*/
  266. /* Initialize debug */
  267. /*----------------------------------------------------------------*/
  268. mfspr r1,SPRN_DBCR0
  269. andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
  270. bne skip_debug_init /* if set, don't clear debug register */
  271. mfspr r1,SPRN_CCR0
  272. ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
  273. mtspr SPRN_CCR0,r1
  274. mtspr SPRN_DBCR0,r0
  275. mtspr SPRN_DBCR1,r0
  276. mtspr SPRN_DBCR2,r0
  277. mtspr SPRN_IAC1,r0
  278. mtspr SPRN_IAC2,r0
  279. mtspr SPRN_IAC3,r0
  280. mtspr SPRN_DAC1,r0
  281. mtspr SPRN_DAC2,r0
  282. mtspr SPRN_DVC1,r0
  283. mtspr SPRN_DVC2,r0
  284. mfspr r1,SPRN_DBSR
  285. mtspr SPRN_DBSR,r1 /* Clear all valid bits */
  286. skip_debug_init:
  287. #if defined (CONFIG_440SPE)
  288. /*----------------------------------------------------------------+
  289. | Initialize Core Configuration Reg1.
  290. | a. ICDPEI: Record even parity. Normal operation.
  291. | b. ICTPEI: Record even parity. Normal operation.
  292. | c. DCTPEI: Record even parity. Normal operation.
  293. | d. DCDPEI: Record even parity. Normal operation.
  294. | e. DCUPEI: Record even parity. Normal operation.
  295. | f. DCMPEI: Record even parity. Normal operation.
  296. | g. FCOM: Normal operation
  297. | h. MMUPEI: Record even parity. Normal operation.
  298. | i. FFF: Flush only as much data as necessary.
  299. | j. TCS: Timebase increments from CPU clock.
  300. +-----------------------------------------------------------------*/
  301. li r0,0
  302. mtspr SPRN_CCR1, r0
  303. /*----------------------------------------------------------------+
  304. | Reset the timebase.
  305. | The previous write to CCR1 sets the timebase source.
  306. +-----------------------------------------------------------------*/
  307. mtspr SPRN_TBWL, r0
  308. mtspr SPRN_TBWU, r0
  309. #endif
  310. /*----------------------------------------------------------------*/
  311. /* Setup interrupt vectors */
  312. /*----------------------------------------------------------------*/
  313. mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
  314. li r1,0x0100
  315. mtspr SPRN_IVOR0,r1 /* Critical input */
  316. li r1,0x0200
  317. mtspr SPRN_IVOR1,r1 /* Machine check */
  318. li r1,0x0300
  319. mtspr SPRN_IVOR2,r1 /* Data storage */
  320. li r1,0x0400
  321. mtspr SPRN_IVOR3,r1 /* Instruction storage */
  322. li r1,0x0500
  323. mtspr SPRN_IVOR4,r1 /* External interrupt */
  324. li r1,0x0600
  325. mtspr SPRN_IVOR5,r1 /* Alignment */
  326. li r1,0x0700
  327. mtspr SPRN_IVOR6,r1 /* Program check */
  328. li r1,0x0800
  329. mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
  330. li r1,0x0c00
  331. mtspr SPRN_IVOR8,r1 /* System call */
  332. li r1,0x0a00
  333. mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
  334. li r1,0x0900
  335. mtspr SPRN_IVOR10,r1 /* Decrementer */
  336. li r1,0x1300
  337. mtspr SPRN_IVOR13,r1 /* Data TLB error */
  338. li r1,0x1400
  339. mtspr SPRN_IVOR14,r1 /* Instr TLB error */
  340. li r1,0x2000
  341. mtspr SPRN_IVOR15,r1 /* Debug */
  342. /*----------------------------------------------------------------*/
  343. /* Configure cache regions */
  344. /*----------------------------------------------------------------*/
  345. mtspr SPRN_INV0,r0
  346. mtspr SPRN_INV1,r0
  347. mtspr SPRN_INV2,r0
  348. mtspr SPRN_INV3,r0
  349. mtspr SPRN_DNV0,r0
  350. mtspr SPRN_DNV1,r0
  351. mtspr SPRN_DNV2,r0
  352. mtspr SPRN_DNV3,r0
  353. mtspr SPRN_ITV0,r0
  354. mtspr SPRN_ITV1,r0
  355. mtspr SPRN_ITV2,r0
  356. mtspr SPRN_ITV3,r0
  357. mtspr SPRN_DTV0,r0
  358. mtspr SPRN_DTV1,r0
  359. mtspr SPRN_DTV2,r0
  360. mtspr SPRN_DTV3,r0
  361. /*----------------------------------------------------------------*/
  362. /* Cache victim limits */
  363. /*----------------------------------------------------------------*/
  364. /* floors 0, ceiling max to use the entire cache -- nothing locked
  365. */
  366. lis r1,0x0001
  367. ori r1,r1,0xf800
  368. mtspr SPRN_IVLIM,r1
  369. mtspr SPRN_DVLIM,r1
  370. /*----------------------------------------------------------------+
  371. |Initialize MMUCR[STID] = 0.
  372. +-----------------------------------------------------------------*/
  373. mfspr r0,SPRN_MMUCR
  374. addis r1,0,0xFFFF
  375. ori r1,r1,0xFF00
  376. and r0,r0,r1
  377. mtspr SPRN_MMUCR,r0
  378. /*----------------------------------------------------------------*/
  379. /* Clear all TLB entries -- TID = 0, TS = 0 */
  380. /*----------------------------------------------------------------*/
  381. addis r0,0,0x0000
  382. #ifdef CONFIG_SYS_RAMBOOT
  383. li r4,0 /* Start with TLB #0 */
  384. #else
  385. li r4,1 /* Start with TLB #1 */
  386. #endif
  387. li r1,64 /* 64 TLB entries */
  388. sub r1,r1,r4 /* calculate last TLB # */
  389. mtctr r1
  390. rsttlb:
  391. #ifdef CONFIG_SYS_RAMBOOT
  392. tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
  393. rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
  394. beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
  395. #endif
  396. tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
  397. tlbwe r0,r4,1
  398. tlbwe r0,r4,2
  399. tlbnxt: addi r4,r4,1 /* Next TLB */
  400. bdnz rsttlb
  401. /*----------------------------------------------------------------*/
  402. /* TLB entry setup -- step thru tlbtab */
  403. /*----------------------------------------------------------------*/
  404. #if defined(CONFIG_440SPE_REVA)
  405. /*----------------------------------------------------------------*/
  406. /* We have different TLB tables for revA and rev B of 440SPe */
  407. /*----------------------------------------------------------------*/
  408. mfspr r1, PVR
  409. lis r0,0x5342
  410. ori r0,r0,0x1891
  411. cmpw r7,r1,r0
  412. bne r7,..revA
  413. bl tlbtabB
  414. b ..goon
  415. ..revA:
  416. bl tlbtabA
  417. ..goon:
  418. #else
  419. bl tlbtab /* Get tlbtab pointer */
  420. #endif
  421. mr r5,r0
  422. li r1,0x003f /* 64 TLB entries max */
  423. mtctr r1
  424. li r4,0 /* TLB # */
  425. addi r5,r5,-4
  426. 1:
  427. #ifdef CONFIG_SYS_RAMBOOT
  428. tlbre r3,r4,0 /* Read contents from TLB word #0 */
  429. rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
  430. bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
  431. #endif
  432. lwzu r0,4(r5)
  433. cmpwi r0,0
  434. beq 2f /* 0 marks end */
  435. lwzu r1,4(r5)
  436. lwzu r2,4(r5)
  437. tlbwe r0,r4,0 /* TLB Word 0 */
  438. tlbwe r1,r4,1 /* TLB Word 1 */
  439. tlbwe r2,r4,2 /* TLB Word 2 */
  440. tlbnx2: addi r4,r4,1 /* Next TLB */
  441. bdnz 1b
  442. /*----------------------------------------------------------------*/
  443. /* Continue from 'normal' start */
  444. /*----------------------------------------------------------------*/
  445. 2:
  446. bl 3f
  447. b _start
  448. 3: li r0,0
  449. mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
  450. mflr r1
  451. mtspr SPRN_SRR0,r1
  452. rfi
  453. #endif /* CONFIG_440 */
  454. /*
  455. * r3 - 1st arg to board_init(): IMMP pointer
  456. * r4 - 2nd arg to board_init(): boot flag
  457. */
  458. #if !defined(CONFIG_SPL_BUILD)
  459. .text
  460. .long 0x27051956 /* U-Boot Magic Number */
  461. .globl version_string
  462. version_string:
  463. .ascii U_BOOT_VERSION_STRING, "\0"
  464. . = EXC_OFF_SYS_RESET
  465. .globl _start_of_vectors
  466. _start_of_vectors:
  467. /* Critical input. */
  468. CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
  469. #ifdef CONFIG_440
  470. /* Machine check */
  471. MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  472. #else
  473. CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  474. #endif /* CONFIG_440 */
  475. /* Data Storage exception. */
  476. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  477. /* Instruction Storage exception. */
  478. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  479. /* External Interrupt exception. */
  480. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  481. /* Alignment exception. */
  482. . = 0x600
  483. Alignment:
  484. EXCEPTION_PROLOG(SRR0, SRR1)
  485. mfspr r4,DAR
  486. stw r4,_DAR(r21)
  487. mfspr r5,DSISR
  488. stw r5,_DSISR(r21)
  489. addi r3,r1,STACK_FRAME_OVERHEAD
  490. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  491. /* Program check exception */
  492. . = 0x700
  493. ProgramCheck:
  494. EXCEPTION_PROLOG(SRR0, SRR1)
  495. addi r3,r1,STACK_FRAME_OVERHEAD
  496. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  497. MSR_KERNEL, COPY_EE)
  498. #ifdef CONFIG_440
  499. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  500. STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
  501. STD_EXCEPTION(0xa00, APU, UnknownException)
  502. #endif
  503. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  504. #ifdef CONFIG_440
  505. STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
  506. STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
  507. #else
  508. STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
  509. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  510. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  511. #endif
  512. CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
  513. .globl _end_of_vectors
  514. _end_of_vectors:
  515. . = _START_OFFSET
  516. #endif
  517. .globl _start
  518. _start:
  519. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  520. /*
  521. * This is the entry of the real U-Boot from a board port
  522. * that supports SPL booting on the PPC4xx. We only need
  523. * to call board_init_f() here. Everything else has already
  524. * been done in the SPL u-boot version.
  525. */
  526. GET_GOT /* initialize GOT access */
  527. bl board_init_f /* run 1st part of board init code (in Flash)*/
  528. /* NOTREACHED - board_init_f() does not return */
  529. #endif
  530. /*****************************************************************************/
  531. #if defined(CONFIG_440)
  532. /*----------------------------------------------------------------*/
  533. /* Clear and set up some registers. */
  534. /*----------------------------------------------------------------*/
  535. li r0,0x0000
  536. lis r1,0xffff
  537. mtspr SPRN_DEC,r0 /* prevent dec exceptions */
  538. mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
  539. mtspr SPRN_TBWU,r0
  540. mtspr SPRN_TSR,r1 /* clear all timer exception status */
  541. mtspr SPRN_TCR,r0 /* disable all */
  542. mtspr SPRN_ESR,r0 /* clear exception syndrome register */
  543. mtxer r0 /* clear integer exception register */
  544. /*----------------------------------------------------------------*/
  545. /* Debug setup -- some (not very good) ice's need an event*/
  546. /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
  547. /* value you need in this case 0x8cff 0000 should do the trick */
  548. /*----------------------------------------------------------------*/
  549. #if defined(CONFIG_SYS_INIT_DBCR)
  550. lis r1,0xffff
  551. ori r1,r1,0xffff
  552. mtspr SPRN_DBSR,r1 /* Clear all status bits */
  553. lis r0,CONFIG_SYS_INIT_DBCR@h
  554. ori r0,r0,CONFIG_SYS_INIT_DBCR@l
  555. mtspr SPRN_DBCR0,r0
  556. isync
  557. #endif
  558. /*----------------------------------------------------------------*/
  559. /* Setup the internal SRAM */
  560. /*----------------------------------------------------------------*/
  561. li r0,0
  562. #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  563. /* Clear Dcache to use as RAM */
  564. addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
  565. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  566. addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
  567. ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
  568. rlwinm. r5,r4,0,27,31
  569. rlwinm r5,r4,27,5,31
  570. beq ..d_ran
  571. addi r5,r5,0x0001
  572. ..d_ran:
  573. mtctr r5
  574. ..d_ag:
  575. dcbz r0,r3
  576. addi r3,r3,32
  577. bdnz ..d_ag
  578. /*
  579. * Lock the init-ram/stack in d-cache, so that other regions
  580. * may use d-cache as well
  581. * Note, that this current implementation locks exactly 4k
  582. * of d-cache, so please make sure that you don't define a
  583. * bigger init-ram area. Take a look at the lwmon5 440EPx
  584. * implementation as a reference.
  585. */
  586. msync
  587. isync
  588. /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
  589. lis r1,0x0201
  590. ori r1,r1,0xf808
  591. mtspr SPRN_DVLIM,r1
  592. lis r1,0x0808
  593. ori r1,r1,0x0808
  594. mtspr SPRN_DNV0,r1
  595. mtspr SPRN_DNV1,r1
  596. mtspr SPRN_DNV2,r1
  597. mtspr SPRN_DNV3,r1
  598. mtspr SPRN_DTV0,r1
  599. mtspr SPRN_DTV1,r1
  600. mtspr SPRN_DTV2,r1
  601. mtspr SPRN_DTV3,r1
  602. msync
  603. isync
  604. #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
  605. /* 440EP & 440GR are only 440er PPC's without internal SRAM */
  606. #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
  607. /* not all PPC's have internal SRAM usable as L2-cache */
  608. #if defined(CONFIG_440GX) || \
  609. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  610. defined(CONFIG_460SX)
  611. mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
  612. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  613. lis r1, 0x0000
  614. ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
  615. mtdcr L2_CACHE_CFG,r1
  616. #endif
  617. lis r2,0x7fff
  618. ori r2,r2,0xffff
  619. mfdcr r1,ISRAM0_DPC
  620. and r1,r1,r2 /* Disable parity check */
  621. mtdcr ISRAM0_DPC,r1
  622. mfdcr r1,ISRAM0_PMEG
  623. and r1,r1,r2 /* Disable pwr mgmt */
  624. mtdcr ISRAM0_PMEG,r1
  625. lis r1,0x8000 /* BAS = 8000_0000 */
  626. #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
  627. ori r1,r1,0x0980 /* first 64k */
  628. mtdcr ISRAM0_SB0CR,r1
  629. lis r1,0x8001
  630. ori r1,r1,0x0980 /* second 64k */
  631. mtdcr ISRAM0_SB1CR,r1
  632. lis r1, 0x8002
  633. ori r1,r1, 0x0980 /* third 64k */
  634. mtdcr ISRAM0_SB2CR,r1
  635. lis r1, 0x8003
  636. ori r1,r1, 0x0980 /* fourth 64k */
  637. mtdcr ISRAM0_SB3CR,r1
  638. #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
  639. defined(CONFIG_460GT)
  640. lis r1,0x0000 /* BAS = X_0000_0000 */
  641. ori r1,r1,0x0984 /* first 64k */
  642. mtdcr ISRAM0_SB0CR,r1
  643. lis r1,0x0001
  644. ori r1,r1,0x0984 /* second 64k */
  645. mtdcr ISRAM0_SB1CR,r1
  646. lis r1, 0x0002
  647. ori r1,r1, 0x0984 /* third 64k */
  648. mtdcr ISRAM0_SB2CR,r1
  649. lis r1, 0x0003
  650. ori r1,r1, 0x0984 /* fourth 64k */
  651. mtdcr ISRAM0_SB3CR,r1
  652. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  653. lis r2,0x7fff
  654. ori r2,r2,0xffff
  655. mfdcr r1,ISRAM1_DPC
  656. and r1,r1,r2 /* Disable parity check */
  657. mtdcr ISRAM1_DPC,r1
  658. mfdcr r1,ISRAM1_PMEG
  659. and r1,r1,r2 /* Disable pwr mgmt */
  660. mtdcr ISRAM1_PMEG,r1
  661. lis r1,0x0004 /* BAS = 4_0004_0000 */
  662. ori r1,r1,ISRAM1_SIZE /* ocm size */
  663. mtdcr ISRAM1_SB0CR,r1
  664. #endif
  665. #elif defined(CONFIG_460SX)
  666. lis r1,0x0000 /* BAS = 0000_0000 */
  667. ori r1,r1,0x0B84 /* first 128k */
  668. mtdcr ISRAM0_SB0CR,r1
  669. lis r1,0x0001
  670. ori r1,r1,0x0B84 /* second 128k */
  671. mtdcr ISRAM0_SB1CR,r1
  672. lis r1, 0x0002
  673. ori r1,r1, 0x0B84 /* third 128k */
  674. mtdcr ISRAM0_SB2CR,r1
  675. lis r1, 0x0003
  676. ori r1,r1, 0x0B84 /* fourth 128k */
  677. mtdcr ISRAM0_SB3CR,r1
  678. #elif defined(CONFIG_440GP)
  679. ori r1,r1,0x0380 /* 8k rw */
  680. mtdcr ISRAM0_SB0CR,r1
  681. mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
  682. #endif
  683. #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
  684. /*----------------------------------------------------------------*/
  685. /* Setup the stack in internal SRAM */
  686. /*----------------------------------------------------------------*/
  687. lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
  688. ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
  689. li r0,0
  690. stwu r0,-4(r1)
  691. stwu r0,-4(r1) /* Terminate call chain */
  692. stwu r1,-8(r1) /* Save back chain and move SP */
  693. lis r0,RESET_VECTOR@h /* Address of reset vector */
  694. ori r0,r0, RESET_VECTOR@l
  695. stwu r1,-8(r1) /* Save back chain and move SP */
  696. stw r0,+12(r1) /* Save return addr (underflow vect) */
  697. #ifndef CONFIG_SPL_BUILD
  698. GET_GOT
  699. #endif
  700. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  701. mr r3, r1
  702. bl board_init_f_alloc_reserve
  703. mr r1, r3
  704. bl board_init_f_init_reserve
  705. li r0,0
  706. stwu r0, -4(r1)
  707. stwu r0, -4(r1)
  708. li r3, 0
  709. bl board_init_f
  710. /* NOTREACHED - board_init_f() does not return */
  711. #endif /* CONFIG_440 */
  712. /*****************************************************************************/
  713. #if defined(CONFIG_405GP) || \
  714. defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  715. defined(CONFIG_405EX) || defined(CONFIG_405)
  716. /*----------------------------------------------------------------------- */
  717. /* Clear and set up some registers. */
  718. /*----------------------------------------------------------------------- */
  719. addi r4,r0,0x0000
  720. #if !defined(CONFIG_405EX)
  721. mtspr SPRN_SGR,r4
  722. #else
  723. /*
  724. * On 405EX, completely clearing the SGR leads to PPC hangup
  725. * upon PCIe configuration access. The PCIe memory regions
  726. * need to be guarded!
  727. */
  728. lis r3,0x0000
  729. ori r3,r3,0x7FFC
  730. mtspr SPRN_SGR,r3
  731. #endif
  732. mtspr SPRN_DCWR,r4
  733. mtesr r4 /* clear Exception Syndrome Reg */
  734. mttcr r4 /* clear Timer Control Reg */
  735. mtxer r4 /* clear Fixed-Point Exception Reg */
  736. mtevpr r4 /* clear Exception Vector Prefix Reg */
  737. addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
  738. /* dbsr is cleared by setting bits to 1) */
  739. mtdbsr r4 /* clear/reset the dbsr */
  740. /* Invalidate the i- and d-caches. */
  741. bl invalidate_icache
  742. bl invalidate_dcache
  743. /* Set-up icache cacheability. */
  744. lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
  745. ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
  746. mticcr r4
  747. isync
  748. /* Set-up dcache cacheability. */
  749. lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
  750. ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
  751. mtdccr r4
  752. #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
  753. && !defined (CONFIG_XILINX_405)
  754. /*----------------------------------------------------------------------- */
  755. /* Tune the speed and size for flash CS0 */
  756. /*----------------------------------------------------------------------- */
  757. bl ext_bus_cntlr_init
  758. #endif
  759. #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
  760. /*
  761. * For boards that don't have OCM and can't use the data cache
  762. * for their primordial stack, setup stack here directly after the
  763. * SDRAM is initialized in ext_bus_cntlr_init.
  764. */
  765. lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
  766. ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
  767. li r0, 0 /* Make room for stack frame header and */
  768. stwu r0, -4(r1) /* clear final stack frame so that */
  769. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  770. /*
  771. * Set up a dummy frame to store reset vector as return address.
  772. * this causes stack underflow to reset board.
  773. */
  774. stwu r1, -8(r1) /* Save back chain and move SP */
  775. lis r0, RESET_VECTOR@h /* Address of reset vector */
  776. ori r0, r0, RESET_VECTOR@l
  777. stwu r1, -8(r1) /* Save back chain and move SP */
  778. stw r0, +12(r1) /* Save return addr (underflow vect) */
  779. #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
  780. #if defined(CONFIG_405EP)
  781. /*----------------------------------------------------------------------- */
  782. /* DMA Status, clear to come up clean */
  783. /*----------------------------------------------------------------------- */
  784. addis r3,r0, 0xFFFF /* Clear all existing DMA status */
  785. ori r3,r3, 0xFFFF
  786. mtdcr DMASR, r3
  787. bl ppc405ep_init /* do ppc405ep specific init */
  788. #endif /* CONFIG_405EP */
  789. #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
  790. #if defined(CONFIG_405EZ)
  791. /********************************************************************
  792. * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
  793. *******************************************************************/
  794. /*
  795. * We can map the OCM on the PLB3, so map it at
  796. * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
  797. */
  798. lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
  799. ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
  800. ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
  801. mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
  802. ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
  803. mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
  804. isync
  805. lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
  806. ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
  807. ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
  808. mtdcr OCM0_DSRC1, r3 /* Set Data Side */
  809. mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
  810. ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
  811. mtdcr OCM0_DSRC2, r3 /* Set Data Side */
  812. mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
  813. addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
  814. mtdcr OCM0_DISDPC,r3
  815. isync
  816. #else /* CONFIG_405EZ */
  817. /********************************************************************
  818. * Setup OCM - On Chip Memory
  819. *******************************************************************/
  820. /* Setup OCM */
  821. lis r0, 0x7FFF
  822. ori r0, r0, 0xFFFF
  823. mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
  824. mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
  825. and r3, r3, r0 /* disable data-side IRAM */
  826. and r4, r4, r0 /* disable data-side IRAM */
  827. mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
  828. mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
  829. isync
  830. lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
  831. ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
  832. mtdcr OCM0_DSARC, r3
  833. addis r4, 0, 0xC000 /* OCM data area enabled */
  834. mtdcr OCM0_DSCNTL, r4
  835. isync
  836. #endif /* CONFIG_405EZ */
  837. #endif
  838. /*----------------------------------------------------------------------- */
  839. /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
  840. /*----------------------------------------------------------------------- */
  841. #ifdef CONFIG_SYS_INIT_DCACHE_CS
  842. li r4, PBxAP
  843. mtdcr EBC0_CFGADDR, r4
  844. lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
  845. ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
  846. mtdcr EBC0_CFGDATA, r4
  847. addi r4, 0, PBxCR
  848. mtdcr EBC0_CFGADDR, r4
  849. lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
  850. ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
  851. mtdcr EBC0_CFGDATA, r4
  852. /*
  853. * Enable the data cache for the 128MB storage access control region
  854. * at CONFIG_SYS_INIT_RAM_ADDR.
  855. */
  856. mfdccr r4
  857. oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
  858. ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
  859. mtdccr r4
  860. /*
  861. * Preallocate data cache lines to be used to avoid a subsequent
  862. * cache miss and an ensuing machine check exception when exceptions
  863. * are enabled.
  864. */
  865. li r0, 0
  866. lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
  867. ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
  868. lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
  869. ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
  870. /*
  871. * Convert the size, in bytes, to the number of cache lines/blocks
  872. * to preallocate.
  873. */
  874. clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
  875. srwi r5, r4, L1_CACHE_SHIFT
  876. beq ..load_counter
  877. addi r5, r5, 0x0001
  878. ..load_counter:
  879. mtctr r5
  880. /* Preallocate the computed number of cache blocks. */
  881. ..alloc_dcache_block:
  882. dcba r0, r3
  883. addi r3, r3, L1_CACHE_BYTES
  884. bdnz ..alloc_dcache_block
  885. sync
  886. /*
  887. * Load the initial stack pointer and data area and convert the size,
  888. * in bytes, to the number of words to initialize to a known value.
  889. */
  890. lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
  891. ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
  892. lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
  893. ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
  894. mtctr r4
  895. lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
  896. ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
  897. lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
  898. ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
  899. ..stackloop:
  900. stwu r4, -4(r2)
  901. bdnz ..stackloop
  902. /*
  903. * Make room for stack frame header and clear final stack frame so
  904. * that stack backtraces terminate cleanly.
  905. */
  906. stwu r0, -4(r1)
  907. stwu r0, -4(r1)
  908. /*
  909. * Set up a dummy frame to store reset vector as return address.
  910. * this causes stack underflow to reset board.
  911. */
  912. stwu r1, -8(r1) /* Save back chain and move SP */
  913. addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
  914. ori r0, r0, RESET_VECTOR@l
  915. stwu r1, -8(r1) /* Save back chain and move SP */
  916. stw r0, +12(r1) /* Save return addr (underflow vect) */
  917. #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
  918. (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
  919. /*
  920. * Stack in OCM.
  921. */
  922. /* Set up Stack at top of OCM */
  923. lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
  924. ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
  925. /* Set up a zeroized stack frame so that backtrace works right */
  926. li r0, 0
  927. stwu r0, -4(r1)
  928. stwu r0, -4(r1)
  929. /*
  930. * Set up a dummy frame to store reset vector as return address.
  931. * this causes stack underflow to reset board.
  932. */
  933. stwu r1, -8(r1) /* Save back chain and move SP */
  934. lis r0, RESET_VECTOR@h /* Address of reset vector */
  935. ori r0, r0, RESET_VECTOR@l
  936. stwu r1, -8(r1) /* Save back chain and move SP */
  937. stw r0, +12(r1) /* Save return addr (underflow vect) */
  938. #endif /* CONFIG_SYS_INIT_DCACHE_CS */
  939. GET_GOT /* initialize GOT access */
  940. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  941. mr r3, r1
  942. bl board_init_f_alloc_reserve
  943. mr r1, r3
  944. bl board_init_f_init_reserve
  945. stwu r0, -4(r1)
  946. stwu r0, -4(r1)
  947. li r3, 0
  948. bl board_init_f /* run first part of init code (from Flash) */
  949. /* NOTREACHED - board_init_f() does not return */
  950. #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
  951. /*----------------------------------------------------------------------- */
  952. #if !defined(CONFIG_SPL_BUILD)
  953. /*
  954. * This code finishes saving the registers to the exception frame
  955. * and jumps to the appropriate handler for the exception.
  956. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  957. */
  958. .globl transfer_to_handler
  959. transfer_to_handler:
  960. stw r22,_NIP(r21)
  961. lis r22,MSR_POW@h
  962. andc r23,r23,r22
  963. stw r23,_MSR(r21)
  964. SAVE_GPR(7, r21)
  965. SAVE_4GPRS(8, r21)
  966. SAVE_8GPRS(12, r21)
  967. SAVE_8GPRS(24, r21)
  968. mflr r23
  969. andi. r24,r23,0x3f00 /* get vector offset */
  970. stw r24,TRAP(r21)
  971. li r22,0
  972. stw r22,RESULT(r21)
  973. mtspr SPRG2,r22 /* r1 is now kernel sp */
  974. lwz r24,0(r23) /* virtual address of handler */
  975. lwz r23,4(r23) /* where to go when done */
  976. mtspr SRR0,r24
  977. mtspr SRR1,r20
  978. mtlr r23
  979. SYNC
  980. rfi /* jump to handler, enable MMU */
  981. int_return:
  982. mfmsr r28 /* Disable interrupts */
  983. li r4,0
  984. ori r4,r4,MSR_EE
  985. andc r28,r28,r4
  986. SYNC /* Some chip revs need this... */
  987. mtmsr r28
  988. SYNC
  989. lwz r2,_CTR(r1)
  990. lwz r0,_LINK(r1)
  991. mtctr r2
  992. mtlr r0
  993. lwz r2,_XER(r1)
  994. lwz r0,_CCR(r1)
  995. mtspr XER,r2
  996. mtcrf 0xFF,r0
  997. REST_10GPRS(3, r1)
  998. REST_10GPRS(13, r1)
  999. REST_8GPRS(23, r1)
  1000. REST_GPR(31, r1)
  1001. lwz r2,_NIP(r1) /* Restore environment */
  1002. lwz r0,_MSR(r1)
  1003. mtspr SRR0,r2
  1004. mtspr SRR1,r0
  1005. lwz r0,GPR0(r1)
  1006. lwz r2,GPR2(r1)
  1007. lwz r1,GPR1(r1)
  1008. SYNC
  1009. rfi
  1010. crit_return:
  1011. mfmsr r28 /* Disable interrupts */
  1012. li r4,0
  1013. ori r4,r4,MSR_EE
  1014. andc r28,r28,r4
  1015. SYNC /* Some chip revs need this... */
  1016. mtmsr r28
  1017. SYNC
  1018. lwz r2,_CTR(r1)
  1019. lwz r0,_LINK(r1)
  1020. mtctr r2
  1021. mtlr r0
  1022. lwz r2,_XER(r1)
  1023. lwz r0,_CCR(r1)
  1024. mtspr XER,r2
  1025. mtcrf 0xFF,r0
  1026. REST_10GPRS(3, r1)
  1027. REST_10GPRS(13, r1)
  1028. REST_8GPRS(23, r1)
  1029. REST_GPR(31, r1)
  1030. lwz r2,_NIP(r1) /* Restore environment */
  1031. lwz r0,_MSR(r1)
  1032. mtspr SPRN_CSRR0,r2
  1033. mtspr SPRN_CSRR1,r0
  1034. lwz r0,GPR0(r1)
  1035. lwz r2,GPR2(r1)
  1036. lwz r1,GPR1(r1)
  1037. SYNC
  1038. rfci
  1039. #ifdef CONFIG_440
  1040. mck_return:
  1041. mfmsr r28 /* Disable interrupts */
  1042. li r4,0
  1043. ori r4,r4,MSR_EE
  1044. andc r28,r28,r4
  1045. SYNC /* Some chip revs need this... */
  1046. mtmsr r28
  1047. SYNC
  1048. lwz r2,_CTR(r1)
  1049. lwz r0,_LINK(r1)
  1050. mtctr r2
  1051. mtlr r0
  1052. lwz r2,_XER(r1)
  1053. lwz r0,_CCR(r1)
  1054. mtspr XER,r2
  1055. mtcrf 0xFF,r0
  1056. REST_10GPRS(3, r1)
  1057. REST_10GPRS(13, r1)
  1058. REST_8GPRS(23, r1)
  1059. REST_GPR(31, r1)
  1060. lwz r2,_NIP(r1) /* Restore environment */
  1061. lwz r0,_MSR(r1)
  1062. mtspr SPRN_MCSRR0,r2
  1063. mtspr SPRN_MCSRR1,r0
  1064. lwz r0,GPR0(r1)
  1065. lwz r2,GPR2(r1)
  1066. lwz r1,GPR1(r1)
  1067. SYNC
  1068. rfmci
  1069. #endif /* CONFIG_440 */
  1070. .globl get_pvr
  1071. get_pvr:
  1072. mfspr r3, PVR
  1073. blr
  1074. /*------------------------------------------------------------------------------- */
  1075. /* Function: out16 */
  1076. /* Description: Output 16 bits */
  1077. /*------------------------------------------------------------------------------- */
  1078. .globl out16
  1079. out16:
  1080. sth r4,0x0000(r3)
  1081. blr
  1082. /*------------------------------------------------------------------------------- */
  1083. /* Function: out16r */
  1084. /* Description: Byte reverse and output 16 bits */
  1085. /*------------------------------------------------------------------------------- */
  1086. .globl out16r
  1087. out16r:
  1088. sthbrx r4,r0,r3
  1089. blr
  1090. /*------------------------------------------------------------------------------- */
  1091. /* Function: out32r */
  1092. /* Description: Byte reverse and output 32 bits */
  1093. /*------------------------------------------------------------------------------- */
  1094. .globl out32r
  1095. out32r:
  1096. stwbrx r4,r0,r3
  1097. blr
  1098. /*------------------------------------------------------------------------------- */
  1099. /* Function: in16 */
  1100. /* Description: Input 16 bits */
  1101. /*------------------------------------------------------------------------------- */
  1102. .globl in16
  1103. in16:
  1104. lhz r3,0x0000(r3)
  1105. blr
  1106. /*------------------------------------------------------------------------------- */
  1107. /* Function: in16r */
  1108. /* Description: Input 16 bits and byte reverse */
  1109. /*------------------------------------------------------------------------------- */
  1110. .globl in16r
  1111. in16r:
  1112. lhbrx r3,r0,r3
  1113. blr
  1114. /*------------------------------------------------------------------------------- */
  1115. /* Function: in32r */
  1116. /* Description: Input 32 bits and byte reverse */
  1117. /*------------------------------------------------------------------------------- */
  1118. .globl in32r
  1119. in32r:
  1120. lwbrx r3,r0,r3
  1121. blr
  1122. #if !defined(CONFIG_SPL_BUILD)
  1123. /*
  1124. * void relocate_code (addr_sp, gd, addr_moni)
  1125. *
  1126. * This "function" does not return, instead it continues in RAM
  1127. * after relocating the monitor code.
  1128. *
  1129. * r3 = Relocated stack pointer
  1130. * r4 = Relocated global data pointer
  1131. * r5 = Relocated text pointer
  1132. */
  1133. .globl relocate_code
  1134. relocate_code:
  1135. #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
  1136. /*
  1137. * We need to flush the initial global data (gd_t) and bd_info
  1138. * before the dcache will be invalidated.
  1139. */
  1140. /* Save registers */
  1141. mr r9, r3
  1142. mr r10, r4
  1143. mr r11, r5
  1144. /*
  1145. * Flush complete dcache, this is faster than flushing the
  1146. * ranges for global_data and bd_info instead.
  1147. */
  1148. bl flush_dcache
  1149. #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  1150. /*
  1151. * Undo the earlier data cache set-up for the primordial stack and
  1152. * data area. First, invalidate the data cache and then disable data
  1153. * cacheability for that area. Finally, restore the EBC values, if
  1154. * any.
  1155. */
  1156. /* Invalidate the primordial stack and data area in cache */
  1157. lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
  1158. ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
  1159. lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
  1160. ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
  1161. add r4, r4, r3
  1162. bl invalidate_dcache_range
  1163. /* Disable cacheability for the region */
  1164. mfdccr r3
  1165. lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
  1166. ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
  1167. and r3, r3, r4
  1168. mtdccr r3
  1169. /* Restore the EBC parameters */
  1170. li r3, PBxAP
  1171. mtdcr EBC0_CFGADDR, r3
  1172. lis r3, PBxAP_VAL@h
  1173. ori r3, r3, PBxAP_VAL@l
  1174. mtdcr EBC0_CFGDATA, r3
  1175. li r3, PBxCR
  1176. mtdcr EBC0_CFGADDR, r3
  1177. lis r3, PBxCR_VAL@h
  1178. ori r3, r3, PBxCR_VAL@l
  1179. mtdcr EBC0_CFGDATA, r3
  1180. #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  1181. /* Restore registers */
  1182. mr r3, r9
  1183. mr r4, r10
  1184. mr r5, r11
  1185. #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
  1186. #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  1187. /*
  1188. * Unlock the previously locked d-cache
  1189. */
  1190. msync
  1191. isync
  1192. /* set TFLOOR/NFLOOR to 0 again */
  1193. lis r6,0x0001
  1194. ori r6,r6,0xf800
  1195. mtspr SPRN_DVLIM,r6
  1196. lis r6,0x0000
  1197. ori r6,r6,0x0000
  1198. mtspr SPRN_DNV0,r6
  1199. mtspr SPRN_DNV1,r6
  1200. mtspr SPRN_DNV2,r6
  1201. mtspr SPRN_DNV3,r6
  1202. mtspr SPRN_DTV0,r6
  1203. mtspr SPRN_DTV1,r6
  1204. mtspr SPRN_DTV2,r6
  1205. mtspr SPRN_DTV3,r6
  1206. msync
  1207. isync
  1208. /* Invalidate data cache, now no longer our stack */
  1209. dccci 0,0
  1210. sync
  1211. isync
  1212. #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
  1213. /*
  1214. * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
  1215. * to speed up the boot process. Now this cache needs to be disabled.
  1216. */
  1217. #if defined(CONFIG_440)
  1218. /* Clear all potential pending exceptions */
  1219. mfspr r1,SPRN_MCSR
  1220. mtspr SPRN_MCSR,r1
  1221. addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
  1222. tlbre r0,r1,0x0002 /* Read contents */
  1223. ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
  1224. tlbwe r0,r1,0x0002 /* Save it out */
  1225. sync
  1226. isync
  1227. #endif /* defined(CONFIG_440) */
  1228. mr r1, r3 /* Set new stack pointer */
  1229. mr r9, r4 /* Save copy of Init Data pointer */
  1230. mr r10, r5 /* Save copy of Destination Address */
  1231. GET_GOT
  1232. mr r3, r5 /* Destination Address */
  1233. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  1234. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  1235. lwz r5, GOT(__init_end)
  1236. sub r5, r5, r4
  1237. li r6, L1_CACHE_BYTES /* Cache Line Size */
  1238. /*
  1239. * Fix GOT pointer:
  1240. *
  1241. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  1242. *
  1243. * Offset:
  1244. */
  1245. sub r15, r10, r4
  1246. /* First our own GOT */
  1247. add r12, r12, r15
  1248. /* then the one used by the C code */
  1249. add r30, r30, r15
  1250. /*
  1251. * Now relocate code
  1252. */
  1253. cmplw cr1,r3,r4
  1254. addi r0,r5,3
  1255. srwi. r0,r0,2
  1256. beq cr1,4f /* In place copy is not necessary */
  1257. beq 7f /* Protect against 0 count */
  1258. mtctr r0
  1259. bge cr1,2f
  1260. la r8,-4(r4)
  1261. la r7,-4(r3)
  1262. 1: lwzu r0,4(r8)
  1263. stwu r0,4(r7)
  1264. bdnz 1b
  1265. b 4f
  1266. 2: slwi r0,r0,2
  1267. add r8,r4,r0
  1268. add r7,r3,r0
  1269. 3: lwzu r0,-4(r8)
  1270. stwu r0,-4(r7)
  1271. bdnz 3b
  1272. /*
  1273. * Now flush the cache: note that we must start from a cache aligned
  1274. * address. Otherwise we might miss one cache line.
  1275. */
  1276. 4: cmpwi r6,0
  1277. add r5,r3,r5
  1278. beq 7f /* Always flush prefetch queue in any case */
  1279. subi r0,r6,1
  1280. andc r3,r3,r0
  1281. mr r4,r3
  1282. 5: dcbst 0,r4
  1283. add r4,r4,r6
  1284. cmplw r4,r5
  1285. blt 5b
  1286. sync /* Wait for all dcbst to complete on bus */
  1287. mr r4,r3
  1288. 6: icbi 0,r4
  1289. add r4,r4,r6
  1290. cmplw r4,r5
  1291. blt 6b
  1292. 7: sync /* Wait for all icbi to complete on bus */
  1293. isync
  1294. /*
  1295. * We are done. Do not return, instead branch to second part of board
  1296. * initialization, now running from RAM.
  1297. */
  1298. addi r0, r10, in_ram - _start + _START_OFFSET
  1299. mtlr r0
  1300. blr /* NEVER RETURNS! */
  1301. in_ram:
  1302. /*
  1303. * Relocation Function, r12 point to got2+0x8000
  1304. *
  1305. * Adjust got2 pointers, no need to check for 0, this code
  1306. * already puts a few entries in the table.
  1307. */
  1308. li r0,__got2_entries@sectoff@l
  1309. la r3,GOT(_GOT2_TABLE_)
  1310. lwz r11,GOT(_GOT2_TABLE_)
  1311. mtctr r0
  1312. sub r11,r3,r11
  1313. addi r3,r3,-4
  1314. 1: lwzu r0,4(r3)
  1315. cmpwi r0,0
  1316. beq- 2f
  1317. add r0,r0,r11
  1318. stw r0,0(r3)
  1319. 2: bdnz 1b
  1320. /*
  1321. * Now adjust the fixups and the pointers to the fixups
  1322. * in case we need to move ourselves again.
  1323. */
  1324. li r0,__fixup_entries@sectoff@l
  1325. lwz r3,GOT(_FIXUP_TABLE_)
  1326. cmpwi r0,0
  1327. mtctr r0
  1328. addi r3,r3,-4
  1329. beq 4f
  1330. 3: lwzu r4,4(r3)
  1331. lwzux r0,r4,r11
  1332. cmpwi r0,0
  1333. add r0,r0,r11
  1334. stw r4,0(r3)
  1335. beq- 5f
  1336. stw r0,0(r4)
  1337. 5: bdnz 3b
  1338. 4:
  1339. clear_bss:
  1340. /*
  1341. * Now clear BSS segment
  1342. */
  1343. lwz r3,GOT(__bss_start)
  1344. lwz r4,GOT(__bss_end)
  1345. cmplw 0, r3, r4
  1346. beq 7f
  1347. li r0, 0
  1348. andi. r5, r4, 3
  1349. beq 6f
  1350. sub r4, r4, r5
  1351. mtctr r5
  1352. mr r5, r4
  1353. 5: stb r0, 0(r5)
  1354. addi r5, r5, 1
  1355. bdnz 5b
  1356. 6:
  1357. stw r0, 0(r3)
  1358. addi r3, r3, 4
  1359. cmplw 0, r3, r4
  1360. bne 6b
  1361. 7:
  1362. mr r3, r9 /* Init Data pointer */
  1363. mr r4, r10 /* Destination Address */
  1364. bl board_init_r
  1365. /*
  1366. * Copy exception vector code to low memory
  1367. *
  1368. * r3: dest_addr
  1369. * r7: source address, r8: end address, r9: target address
  1370. */
  1371. .globl trap_init
  1372. trap_init:
  1373. mflr r4 /* save link register */
  1374. GET_GOT
  1375. lwz r7, GOT(_start_of_vectors)
  1376. lwz r8, GOT(_end_of_vectors)
  1377. li r9, 0x100 /* reset vector always at 0x100 */
  1378. cmplw 0, r7, r8
  1379. bgelr /* return if r7>=r8 - just in case */
  1380. 1:
  1381. lwz r0, 0(r7)
  1382. stw r0, 0(r9)
  1383. addi r7, r7, 4
  1384. addi r9, r9, 4
  1385. cmplw 0, r7, r8
  1386. bne 1b
  1387. /*
  1388. * relocate `hdlr' and `int_return' entries
  1389. */
  1390. li r7, .L_MachineCheck - _start + _START_OFFSET
  1391. li r8, Alignment - _start + _START_OFFSET
  1392. 2:
  1393. bl trap_reloc
  1394. addi r7, r7, 0x100 /* next exception vector */
  1395. cmplw 0, r7, r8
  1396. blt 2b
  1397. li r7, .L_Alignment - _start + _START_OFFSET
  1398. bl trap_reloc
  1399. li r7, .L_ProgramCheck - _start + _START_OFFSET
  1400. bl trap_reloc
  1401. #ifdef CONFIG_440
  1402. li r7, .L_FPUnavailable - _start + _START_OFFSET
  1403. bl trap_reloc
  1404. li r7, .L_Decrementer - _start + _START_OFFSET
  1405. bl trap_reloc
  1406. li r7, .L_APU - _start + _START_OFFSET
  1407. bl trap_reloc
  1408. li r7, .L_InstructionTLBError - _start + _START_OFFSET
  1409. bl trap_reloc
  1410. li r7, .L_DataTLBError - _start + _START_OFFSET
  1411. bl trap_reloc
  1412. #else /* CONFIG_440 */
  1413. li r7, .L_PIT - _start + _START_OFFSET
  1414. bl trap_reloc
  1415. li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
  1416. bl trap_reloc
  1417. li r7, .L_DataTLBMiss - _start + _START_OFFSET
  1418. bl trap_reloc
  1419. #endif /* CONFIG_440 */
  1420. li r7, .L_DebugBreakpoint - _start + _START_OFFSET
  1421. bl trap_reloc
  1422. #if !defined(CONFIG_440)
  1423. addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
  1424. oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
  1425. mtmsr r7 /* change MSR */
  1426. #else
  1427. bl __440_msr_set
  1428. b __440_msr_continue
  1429. __440_msr_set:
  1430. addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
  1431. oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
  1432. mtspr SPRN_SRR1,r7
  1433. mflr r7
  1434. mtspr SPRN_SRR0,r7
  1435. rfi
  1436. __440_msr_continue:
  1437. #endif
  1438. mtlr r4 /* restore link register */
  1439. blr
  1440. #endif /* CONFIG_SPL_BUILD */
  1441. #if defined(CONFIG_440)
  1442. /*----------------------------------------------------------------------------+
  1443. | dcbz_area.
  1444. +----------------------------------------------------------------------------*/
  1445. function_prolog(dcbz_area)
  1446. rlwinm. r5,r4,0,27,31
  1447. rlwinm r5,r4,27,5,31
  1448. beq ..d_ra2
  1449. addi r5,r5,0x0001
  1450. ..d_ra2:mtctr r5
  1451. ..d_ag2:dcbz r0,r3
  1452. addi r3,r3,32
  1453. bdnz ..d_ag2
  1454. sync
  1455. blr
  1456. function_epilog(dcbz_area)
  1457. #endif /* CONFIG_440 */
  1458. #endif /* CONFIG_SPL_BUILD */
  1459. /*------------------------------------------------------------------------------- */
  1460. /* Function: in8 */
  1461. /* Description: Input 8 bits */
  1462. /*------------------------------------------------------------------------------- */
  1463. .globl in8
  1464. in8:
  1465. lbz r3,0x0000(r3)
  1466. blr
  1467. /*------------------------------------------------------------------------------- */
  1468. /* Function: out8 */
  1469. /* Description: Output 8 bits */
  1470. /*------------------------------------------------------------------------------- */
  1471. .globl out8
  1472. out8:
  1473. stb r4,0x0000(r3)
  1474. blr
  1475. /*------------------------------------------------------------------------------- */
  1476. /* Function: out32 */
  1477. /* Description: Output 32 bits */
  1478. /*------------------------------------------------------------------------------- */
  1479. .globl out32
  1480. out32:
  1481. stw r4,0x0000(r3)
  1482. blr
  1483. /*------------------------------------------------------------------------------- */
  1484. /* Function: in32 */
  1485. /* Description: Input 32 bits */
  1486. /*------------------------------------------------------------------------------- */
  1487. .globl in32
  1488. in32:
  1489. lwz 3,0x0000(3)
  1490. blr
  1491. /**************************************************************************/
  1492. /* PPC405EP specific stuff */
  1493. /**************************************************************************/
  1494. #ifdef CONFIG_405EP
  1495. ppc405ep_init:
  1496. #ifdef CONFIG_BUBINGA
  1497. /*
  1498. * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
  1499. * function) to support FPGA and NVRAM accesses below.
  1500. */
  1501. lis r3,GPIO0_OSRH@h /* config GPIO output select */
  1502. ori r3,r3,GPIO0_OSRH@l
  1503. lis r4,CONFIG_SYS_GPIO0_OSRH@h
  1504. ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
  1505. stw r4,0(r3)
  1506. lis r3,GPIO0_OSRL@h
  1507. ori r3,r3,GPIO0_OSRL@l
  1508. lis r4,CONFIG_SYS_GPIO0_OSRL@h
  1509. ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
  1510. stw r4,0(r3)
  1511. lis r3,GPIO0_ISR1H@h /* config GPIO input select */
  1512. ori r3,r3,GPIO0_ISR1H@l
  1513. lis r4,CONFIG_SYS_GPIO0_ISR1H@h
  1514. ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
  1515. stw r4,0(r3)
  1516. lis r3,GPIO0_ISR1L@h
  1517. ori r3,r3,GPIO0_ISR1L@l
  1518. lis r4,CONFIG_SYS_GPIO0_ISR1L@h
  1519. ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
  1520. stw r4,0(r3)
  1521. lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
  1522. ori r3,r3,GPIO0_TSRH@l
  1523. lis r4,CONFIG_SYS_GPIO0_TSRH@h
  1524. ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
  1525. stw r4,0(r3)
  1526. lis r3,GPIO0_TSRL@h
  1527. ori r3,r3,GPIO0_TSRL@l
  1528. lis r4,CONFIG_SYS_GPIO0_TSRL@h
  1529. ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
  1530. stw r4,0(r3)
  1531. lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
  1532. ori r3,r3,GPIO0_TCR@l
  1533. lis r4,CONFIG_SYS_GPIO0_TCR@h
  1534. ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
  1535. stw r4,0(r3)
  1536. li r3,PB1AP /* program EBC bank 1 for RTC access */
  1537. mtdcr EBC0_CFGADDR,r3
  1538. lis r3,CONFIG_SYS_EBC_PB1AP@h
  1539. ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
  1540. mtdcr EBC0_CFGDATA,r3
  1541. li r3,PB1CR
  1542. mtdcr EBC0_CFGADDR,r3
  1543. lis r3,CONFIG_SYS_EBC_PB1CR@h
  1544. ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
  1545. mtdcr EBC0_CFGDATA,r3
  1546. li r3,PB1AP /* program EBC bank 1 for RTC access */
  1547. mtdcr EBC0_CFGADDR,r3
  1548. lis r3,CONFIG_SYS_EBC_PB1AP@h
  1549. ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
  1550. mtdcr EBC0_CFGDATA,r3
  1551. li r3,PB1CR
  1552. mtdcr EBC0_CFGADDR,r3
  1553. lis r3,CONFIG_SYS_EBC_PB1CR@h
  1554. ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
  1555. mtdcr EBC0_CFGDATA,r3
  1556. li r3,PB4AP /* program EBC bank 4 for FPGA access */
  1557. mtdcr EBC0_CFGADDR,r3
  1558. lis r3,CONFIG_SYS_EBC_PB4AP@h
  1559. ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
  1560. mtdcr EBC0_CFGDATA,r3
  1561. li r3,PB4CR
  1562. mtdcr EBC0_CFGADDR,r3
  1563. lis r3,CONFIG_SYS_EBC_PB4CR@h
  1564. ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
  1565. mtdcr EBC0_CFGDATA,r3
  1566. #endif
  1567. /*
  1568. !-----------------------------------------------------------------------
  1569. ! Check to see if chip is in bypass mode.
  1570. ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
  1571. ! CPU reset Otherwise, skip this step and keep going.
  1572. ! Note: Running BIOS in bypass mode is not supported since PLB speed
  1573. ! will not be fast enough for the SDRAM (min 66MHz)
  1574. !-----------------------------------------------------------------------
  1575. */
  1576. mfdcr r5, CPC0_PLLMR1
  1577. rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
  1578. cmpi cr0,0,r4,0x1
  1579. beq pll_done /* if SSCS =b'1' then PLL has */
  1580. /* already been set */
  1581. /* and CPU has been reset */
  1582. /* so skip to next section */
  1583. #ifdef CONFIG_BUBINGA
  1584. /*
  1585. !-----------------------------------------------------------------------
  1586. ! Read NVRAM to get value to write in PLLMR.
  1587. ! If value has not been correctly saved, write default value
  1588. ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
  1589. ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
  1590. !
  1591. ! WARNING: This code assumes the first three words in the nvram_t
  1592. ! structure in openbios.h. Changing the beginning of
  1593. ! the structure will break this code.
  1594. !
  1595. !-----------------------------------------------------------------------
  1596. */
  1597. addis r3,0,NVRAM_BASE@h
  1598. addi r3,r3,NVRAM_BASE@l
  1599. lwz r4, 0(r3)
  1600. addis r5,0,NVRVFY1@h
  1601. addi r5,r5,NVRVFY1@l
  1602. cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
  1603. bne ..no_pllset
  1604. addi r3,r3,4
  1605. lwz r4, 0(r3)
  1606. addis r5,0,NVRVFY2@h
  1607. addi r5,r5,NVRVFY2@l
  1608. cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
  1609. bne ..no_pllset
  1610. addi r3,r3,8 /* Skip over conf_size */
  1611. lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
  1612. lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
  1613. rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
  1614. cmpi cr0,0,r5,1 /* See if PLL is locked */
  1615. beq pll_write
  1616. ..no_pllset:
  1617. #endif /* CONFIG_BUBINGA */
  1618. addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
  1619. ori r3,r3,PLLMR0_DEFAULT@l /* */
  1620. addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
  1621. ori r4,r4,PLLMR1_DEFAULT@l /* */
  1622. 1:
  1623. b pll_write /* Write the CPC0_PLLMR with new value */
  1624. pll_done:
  1625. /*
  1626. !-----------------------------------------------------------------------
  1627. ! Clear Soft Reset Register
  1628. ! This is needed to enable PCI if not booting from serial EPROM
  1629. !-----------------------------------------------------------------------
  1630. */
  1631. addi r3, 0, 0x0
  1632. mtdcr CPC0_SRR, r3
  1633. addis r3,0,0x0010
  1634. mtctr r3
  1635. pci_wait:
  1636. bdnz pci_wait
  1637. blr /* return to main code */
  1638. /*
  1639. !-----------------------------------------------------------------------------
  1640. ! Function: pll_write
  1641. ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
  1642. ! That is:
  1643. ! 1. Pll is first disabled (de-activated by putting in bypass mode)
  1644. ! 2. PLL is reset
  1645. ! 3. Clock dividers are set while PLL is held in reset and bypassed
  1646. ! 4. PLL Reset is cleared
  1647. ! 5. Wait 100us for PLL to lock
  1648. ! 6. A core reset is performed
  1649. ! Input: r3 = Value to write to CPC0_PLLMR0
  1650. ! Input: r4 = Value to write to CPC0_PLLMR1
  1651. ! Output r3 = none
  1652. !-----------------------------------------------------------------------------
  1653. */
  1654. .globl pll_write
  1655. pll_write:
  1656. mfdcr r5, CPC0_UCR
  1657. andis. r5,r5,0xFFFF
  1658. ori r5,r5,0x0101 /* Stop the UART clocks */
  1659. mtdcr CPC0_UCR,r5 /* Before changing PLL */
  1660. mfdcr r5, CPC0_PLLMR1
  1661. rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
  1662. mtdcr CPC0_PLLMR1,r5
  1663. oris r5,r5,0x4000 /* Set PLL Reset */
  1664. mtdcr CPC0_PLLMR1,r5
  1665. mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
  1666. rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
  1667. oris r5,r5,0x4000 /* Set PLL Reset */
  1668. mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
  1669. rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
  1670. mtdcr CPC0_PLLMR1,r5
  1671. /*
  1672. ! Wait min of 100us for PLL to lock.
  1673. ! See CMOS 27E databook for more info.
  1674. ! At 200MHz, that means waiting 20,000 instructions
  1675. */
  1676. addi r3,0,20000 /* 2000 = 0x4e20 */
  1677. mtctr r3
  1678. pll_wait:
  1679. bdnz pll_wait
  1680. oris r5,r5,0x8000 /* Enable PLL */
  1681. mtdcr CPC0_PLLMR1,r5 /* Engage */
  1682. /*
  1683. * Reset CPU to guarantee timings are OK
  1684. * Not sure if this is needed...
  1685. */
  1686. addis r3,0,0x1000
  1687. mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
  1688. /* execution will continue from the poweron */
  1689. /* vector of 0xfffffffc */
  1690. #endif /* CONFIG_405EP */
  1691. #if defined(CONFIG_440)
  1692. /*----------------------------------------------------------------------------+
  1693. | mttlb3.
  1694. +----------------------------------------------------------------------------*/
  1695. function_prolog(mttlb3)
  1696. TLBWE(4,3,2)
  1697. blr
  1698. function_epilog(mttlb3)
  1699. /*----------------------------------------------------------------------------+
  1700. | mftlb3.
  1701. +----------------------------------------------------------------------------*/
  1702. function_prolog(mftlb3)
  1703. TLBRE(3,3,2)
  1704. blr
  1705. function_epilog(mftlb3)
  1706. /*----------------------------------------------------------------------------+
  1707. | mttlb2.
  1708. +----------------------------------------------------------------------------*/
  1709. function_prolog(mttlb2)
  1710. TLBWE(4,3,1)
  1711. blr
  1712. function_epilog(mttlb2)
  1713. /*----------------------------------------------------------------------------+
  1714. | mftlb2.
  1715. +----------------------------------------------------------------------------*/
  1716. function_prolog(mftlb2)
  1717. TLBRE(3,3,1)
  1718. blr
  1719. function_epilog(mftlb2)
  1720. /*----------------------------------------------------------------------------+
  1721. | mttlb1.
  1722. +----------------------------------------------------------------------------*/
  1723. function_prolog(mttlb1)
  1724. TLBWE(4,3,0)
  1725. blr
  1726. function_epilog(mttlb1)
  1727. /*----------------------------------------------------------------------------+
  1728. | mftlb1.
  1729. +----------------------------------------------------------------------------*/
  1730. function_prolog(mftlb1)
  1731. TLBRE(3,3,0)
  1732. blr
  1733. function_epilog(mftlb1)
  1734. #endif /* CONFIG_440 */