mp.c 11 KB

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  1. /*
  2. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/processor.h>
  8. #include <ioports.h>
  9. #include <lmb.h>
  10. #include <asm/io.h>
  11. #include <asm/mmu.h>
  12. #include <asm/fsl_law.h>
  13. #include <fsl_ddr_sdram.h>
  14. #include "mp.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. u32 fsl_ddr_get_intl3r(void);
  17. extern u32 __spin_table[];
  18. u32 get_my_id()
  19. {
  20. return mfspr(SPRN_PIR);
  21. }
  22. /*
  23. * Determine if U-Boot should keep secondary cores in reset, or let them out
  24. * of reset and hold them in a spinloop
  25. */
  26. int hold_cores_in_reset(int verbose)
  27. {
  28. /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
  29. if (getenv_yesno("mp_holdoff") == 1) {
  30. if (verbose) {
  31. puts("Secondary cores are being held in reset.\n");
  32. puts("See 'mp_holdoff' environment variable\n");
  33. }
  34. return 1;
  35. }
  36. return 0;
  37. }
  38. int cpu_reset(int nr)
  39. {
  40. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  41. out_be32(&pic->pir, 1 << nr);
  42. /* the dummy read works around an errata on early 85xx MP PICs */
  43. (void)in_be32(&pic->pir);
  44. out_be32(&pic->pir, 0x0);
  45. return 0;
  46. }
  47. int cpu_status(int nr)
  48. {
  49. u32 *table, id = get_my_id();
  50. if (hold_cores_in_reset(1))
  51. return 0;
  52. if (nr == id) {
  53. table = (u32 *)&__spin_table;
  54. printf("table base @ 0x%p\n", table);
  55. } else if (is_core_disabled(nr)) {
  56. puts("Disabled\n");
  57. } else {
  58. table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
  59. printf("Running on cpu %d\n", id);
  60. printf("\n");
  61. printf("table @ 0x%p\n", table);
  62. printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
  63. printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
  64. printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
  65. }
  66. return 0;
  67. }
  68. #ifdef CONFIG_FSL_CORENET
  69. int cpu_disable(int nr)
  70. {
  71. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  72. setbits_be32(&gur->coredisrl, 1 << nr);
  73. return 0;
  74. }
  75. int is_core_disabled(int nr) {
  76. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  77. u32 coredisrl = in_be32(&gur->coredisrl);
  78. return (coredisrl & (1 << nr));
  79. }
  80. #else
  81. int cpu_disable(int nr)
  82. {
  83. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  84. switch (nr) {
  85. case 0:
  86. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
  87. break;
  88. case 1:
  89. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
  90. break;
  91. default:
  92. printf("Invalid cpu number for disable %d\n", nr);
  93. return 1;
  94. }
  95. return 0;
  96. }
  97. int is_core_disabled(int nr) {
  98. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  99. u32 devdisr = in_be32(&gur->devdisr);
  100. switch (nr) {
  101. case 0:
  102. return (devdisr & MPC85xx_DEVDISR_CPU0);
  103. case 1:
  104. return (devdisr & MPC85xx_DEVDISR_CPU1);
  105. default:
  106. printf("Invalid cpu number for disable %d\n", nr);
  107. }
  108. return 0;
  109. }
  110. #endif
  111. static u8 boot_entry_map[4] = {
  112. 0,
  113. BOOT_ENTRY_PIR,
  114. BOOT_ENTRY_R3_LOWER,
  115. };
  116. int cpu_release(int nr, int argc, char * const argv[])
  117. {
  118. u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
  119. u64 boot_addr;
  120. if (hold_cores_in_reset(1))
  121. return 0;
  122. if (nr == get_my_id()) {
  123. printf("Invalid to release the boot core.\n\n");
  124. return 1;
  125. }
  126. if (argc != 4) {
  127. printf("Invalid number of arguments to release.\n\n");
  128. return 1;
  129. }
  130. boot_addr = simple_strtoull(argv[0], NULL, 16);
  131. /* handle pir, r3 */
  132. for (i = 1; i < 3; i++) {
  133. if (argv[i][0] != '-') {
  134. u8 entry = boot_entry_map[i];
  135. val = simple_strtoul(argv[i], NULL, 16);
  136. table[entry] = val;
  137. }
  138. }
  139. table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
  140. /* ensure all table updates complete before final address write */
  141. eieio();
  142. table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
  143. return 0;
  144. }
  145. u32 determine_mp_bootpg(unsigned int *pagesize)
  146. {
  147. u32 bootpg;
  148. #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
  149. u32 svr = get_svr();
  150. u32 granule_size, check;
  151. struct law_entry e;
  152. #endif
  153. /* use last 4K of mapped memory */
  154. bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
  155. CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
  156. CONFIG_SYS_SDRAM_BASE - 4096;
  157. if (pagesize)
  158. *pagesize = 4096;
  159. #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
  160. /*
  161. * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
  162. * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
  163. * the way boot page chosen in u-boot avoids hitting this erratum. So only
  164. * thw workaround for 3-way interleaving is needed.
  165. *
  166. * To make sure boot page translation works with 3-Way DDR interleaving
  167. * enforce a check for the following constrains
  168. * 8K granule size requires BRSIZE=8K and
  169. * bootpg >> log2(BRSIZE) %3 == 1
  170. * 4K and 1K granule size requires BRSIZE=4K and
  171. * bootpg >> log2(BRSIZE) %3 == 0
  172. */
  173. if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
  174. e = find_law(bootpg);
  175. switch (e.trgt_id) {
  176. case LAW_TRGT_IF_DDR_INTLV_123:
  177. granule_size = fsl_ddr_get_intl3r() & 0x1f;
  178. if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
  179. if (pagesize)
  180. *pagesize = 8192;
  181. bootpg &= 0xffffe000; /* align to 8KB */
  182. check = bootpg >> 13;
  183. while ((check % 3) != 1)
  184. check--;
  185. bootpg = check << 13;
  186. debug("Boot page (8K) at 0x%08x\n", bootpg);
  187. break;
  188. } else {
  189. bootpg &= 0xfffff000; /* align to 4KB */
  190. check = bootpg >> 12;
  191. while ((check % 3) != 0)
  192. check--;
  193. bootpg = check << 12;
  194. debug("Boot page (4K) at 0x%08x\n", bootpg);
  195. }
  196. break;
  197. default:
  198. break;
  199. }
  200. }
  201. #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
  202. return bootpg;
  203. }
  204. phys_addr_t get_spin_phys_addr(void)
  205. {
  206. return virt_to_phys(&__spin_table);
  207. }
  208. #ifdef CONFIG_FSL_CORENET
  209. static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
  210. {
  211. u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
  212. u32 *table = (u32 *)&__spin_table;
  213. volatile ccsr_gur_t *gur;
  214. volatile ccsr_local_t *ccm;
  215. volatile ccsr_rcpm_t *rcpm;
  216. volatile ccsr_pic_t *pic;
  217. int timeout = 10;
  218. u32 mask = cpu_mask();
  219. struct law_entry e;
  220. gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  221. ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
  222. rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  223. pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  224. whoami = in_be32(&pic->whoami);
  225. cpu_up_mask = 1 << whoami;
  226. out_be32(&ccm->bstrl, bootpg);
  227. e = find_law(bootpg);
  228. /* pagesize is only 4K or 8K */
  229. if (pagesize == 8192)
  230. brsize = LAW_SIZE_8K;
  231. out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
  232. debug("BRSIZE is 0x%x\n", brsize);
  233. /* readback to sync write */
  234. in_be32(&ccm->bstrar);
  235. /* disable time base at the platform */
  236. out_be32(&rcpm->ctbenrl, cpu_up_mask);
  237. out_be32(&gur->brrl, mask);
  238. /* wait for everyone */
  239. while (timeout) {
  240. unsigned int i, cpu, nr_cpus = cpu_numcores();
  241. for_each_cpu(i, cpu, nr_cpus, mask) {
  242. if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
  243. cpu_up_mask |= (1 << cpu);
  244. }
  245. if ((cpu_up_mask & mask) == mask)
  246. break;
  247. udelay(100);
  248. timeout--;
  249. }
  250. if (timeout == 0)
  251. printf("CPU up timeout. CPU up mask is %x should be %x\n",
  252. cpu_up_mask, mask);
  253. /* enable time base at the platform */
  254. out_be32(&rcpm->ctbenrl, 0);
  255. /* readback to sync write */
  256. in_be32(&rcpm->ctbenrl);
  257. mtspr(SPRN_TBWU, 0);
  258. mtspr(SPRN_TBWL, 0);
  259. out_be32(&rcpm->ctbenrl, mask);
  260. #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  261. /*
  262. * Disabling Boot Page Translation allows the memory region 0xfffff000
  263. * to 0xffffffff to be used normally. Leaving Boot Page Translation
  264. * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  265. * unusable for normal operation but it does allow OSes to easily
  266. * reset a processor core to put it back into U-Boot's spinloop.
  267. */
  268. clrbits_be32(&ccm->bstrar, LAW_EN);
  269. #endif
  270. }
  271. #else
  272. static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
  273. {
  274. u32 up, cpu_up_mask, whoami;
  275. u32 *table = (u32 *)&__spin_table;
  276. volatile u32 bpcr;
  277. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  278. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  279. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  280. u32 devdisr;
  281. int timeout = 10;
  282. whoami = in_be32(&pic->whoami);
  283. out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
  284. /* disable time base at the platform */
  285. devdisr = in_be32(&gur->devdisr);
  286. if (whoami)
  287. devdisr |= MPC85xx_DEVDISR_TB0;
  288. else
  289. devdisr |= MPC85xx_DEVDISR_TB1;
  290. out_be32(&gur->devdisr, devdisr);
  291. /* release the hounds */
  292. up = ((1 << cpu_numcores()) - 1);
  293. bpcr = in_be32(&ecm->eebpcr);
  294. bpcr |= (up << 24);
  295. out_be32(&ecm->eebpcr, bpcr);
  296. asm("sync; isync; msync");
  297. cpu_up_mask = 1 << whoami;
  298. /* wait for everyone */
  299. while (timeout) {
  300. int i;
  301. for (i = 0; i < cpu_numcores(); i++) {
  302. if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
  303. cpu_up_mask |= (1 << i);
  304. };
  305. if ((cpu_up_mask & up) == up)
  306. break;
  307. udelay(100);
  308. timeout--;
  309. }
  310. if (timeout == 0)
  311. printf("CPU up timeout. CPU up mask is %x should be %x\n",
  312. cpu_up_mask, up);
  313. /* enable time base at the platform */
  314. if (whoami)
  315. devdisr |= MPC85xx_DEVDISR_TB1;
  316. else
  317. devdisr |= MPC85xx_DEVDISR_TB0;
  318. out_be32(&gur->devdisr, devdisr);
  319. /* readback to sync write */
  320. in_be32(&gur->devdisr);
  321. mtspr(SPRN_TBWU, 0);
  322. mtspr(SPRN_TBWL, 0);
  323. devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
  324. out_be32(&gur->devdisr, devdisr);
  325. #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  326. /*
  327. * Disabling Boot Page Translation allows the memory region 0xfffff000
  328. * to 0xffffffff to be used normally. Leaving Boot Page Translation
  329. * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  330. * unusable for normal operation but it does allow OSes to easily
  331. * reset a processor core to put it back into U-Boot's spinloop.
  332. */
  333. clrbits_be32(&ecm->bptr, 0x80000000);
  334. #endif
  335. }
  336. #endif
  337. void cpu_mp_lmb_reserve(struct lmb *lmb)
  338. {
  339. u32 bootpg = determine_mp_bootpg(NULL);
  340. lmb_reserve(lmb, bootpg, 4096);
  341. }
  342. void setup_mp(void)
  343. {
  344. extern u32 __secondary_start_page;
  345. extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
  346. int i;
  347. ulong fixup = (u32)&__secondary_start_page;
  348. u32 bootpg, bootpg_map, pagesize;
  349. bootpg = determine_mp_bootpg(&pagesize);
  350. /*
  351. * pagesize is only 4K or 8K
  352. * we only use the last 4K of boot page
  353. * bootpg_map saves the address for the boot page
  354. * 8K is used for the workaround of 3-way DDR interleaving
  355. */
  356. bootpg_map = bootpg;
  357. if (pagesize == 8192)
  358. bootpg += 4096; /* use 2nd half */
  359. /* Some OSes expect secondary cores to be held in reset */
  360. if (hold_cores_in_reset(0))
  361. return;
  362. /*
  363. * Store the bootpg's cache-able half address for use by secondary
  364. * CPU cores to continue to boot
  365. */
  366. __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
  367. /* Store spin table's physical address for use by secondary cores */
  368. __spin_table_addr = (u32)get_spin_phys_addr();
  369. /* flush bootpg it before copying invalidate any staled cacheline */
  370. flush_cache(bootpg, 4096);
  371. /* look for the tlb covering the reset page, there better be one */
  372. i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
  373. /* we found a match */
  374. if (i != -1) {
  375. /* map reset page to bootpg so we can copy code there */
  376. disable_tlb(i);
  377. set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
  378. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  379. 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
  380. memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
  381. plat_mp_up(bootpg_map, pagesize);
  382. } else {
  383. puts("WARNING: No reset page TLB. "
  384. "Skipping secondary core setup\n");
  385. }
  386. }