clock.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741
  1. /*
  2. * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. /* Tegra SoC common clock control functions */
  7. #include <common.h>
  8. #include <errno.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/tegra.h>
  12. #include <asm/arch-tegra/ap.h>
  13. #include <asm/arch-tegra/clk_rst.h>
  14. #include <asm/arch-tegra/pmc.h>
  15. #include <asm/arch-tegra/timer.h>
  16. #include <div64.h>
  17. #include <fdtdec.h>
  18. /*
  19. * This is our record of the current clock rate of each clock. We don't
  20. * fill all of these in since we are only really interested in clocks which
  21. * we use as parents.
  22. */
  23. static unsigned pll_rate[CLOCK_ID_COUNT];
  24. /*
  25. * The oscillator frequency is fixed to one of four set values. Based on this
  26. * the other clocks are set up appropriately.
  27. */
  28. static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
  29. 13000000,
  30. 19200000,
  31. 12000000,
  32. 26000000,
  33. 38400000,
  34. 48000000,
  35. };
  36. /* return 1 if a peripheral ID is in range */
  37. #define clock_type_id_isvalid(id) ((id) >= 0 && \
  38. (id) < CLOCK_TYPE_COUNT)
  39. char pllp_valid = 1; /* PLLP is set up correctly */
  40. /* return 1 if a periphc_internal_id is in range */
  41. #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
  42. (id) < PERIPHC_COUNT)
  43. /* number of clock outputs of a PLL */
  44. static const u8 pll_num_clkouts[] = {
  45. 1, /* PLLC */
  46. 1, /* PLLM */
  47. 4, /* PLLP */
  48. 1, /* PLLA */
  49. 0, /* PLLU */
  50. 0, /* PLLD */
  51. };
  52. int clock_get_osc_bypass(void)
  53. {
  54. struct clk_rst_ctlr *clkrst =
  55. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  56. u32 reg;
  57. reg = readl(&clkrst->crc_osc_ctrl);
  58. return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
  59. }
  60. /* Returns a pointer to the registers of the given pll */
  61. static struct clk_pll *get_pll(enum clock_id clkid)
  62. {
  63. struct clk_rst_ctlr *clkrst =
  64. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  65. assert(clock_id_is_pll(clkid));
  66. if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
  67. debug("%s: Invalid PLL %d\n", __func__, clkid);
  68. return NULL;
  69. }
  70. return &clkrst->crc_pll[clkid];
  71. }
  72. __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
  73. {
  74. return NULL;
  75. }
  76. int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
  77. u32 *divp, u32 *cpcon, u32 *lfcon)
  78. {
  79. struct clk_pll *pll = get_pll(clkid);
  80. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  81. u32 data;
  82. assert(clkid != CLOCK_ID_USB);
  83. /* Safety check, adds to code size but is small */
  84. if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
  85. return -1;
  86. data = readl(&pll->pll_base);
  87. *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
  88. *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
  89. *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
  90. data = readl(&pll->pll_misc);
  91. /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
  92. *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
  93. *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
  94. return 0;
  95. }
  96. unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
  97. u32 divp, u32 cpcon, u32 lfcon)
  98. {
  99. struct clk_pll *pll = NULL;
  100. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  101. struct clk_pll_simple *simple_pll = NULL;
  102. u32 misc_data, data;
  103. if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
  104. pll = get_pll(clkid);
  105. } else {
  106. simple_pll = clock_get_simple_pll(clkid);
  107. if (!simple_pll) {
  108. debug("%s: Uknown simple PLL %d\n", __func__, clkid);
  109. return 0;
  110. }
  111. }
  112. /*
  113. * pllinfo has the m/n/p and kcp/kvco mask and shift
  114. * values for all of the PLLs used in U-Boot, with any
  115. * SoC differences accounted for.
  116. *
  117. * Preserve EN_LOCKDET, etc.
  118. */
  119. if (pll)
  120. misc_data = readl(&pll->pll_misc);
  121. else
  122. misc_data = readl(&simple_pll->pll_misc);
  123. misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
  124. misc_data |= cpcon << pllinfo->kcp_shift;
  125. misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
  126. misc_data |= lfcon << pllinfo->kvco_shift;
  127. data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
  128. data |= divp << pllinfo->p_shift;
  129. data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
  130. if (pll) {
  131. writel(misc_data, &pll->pll_misc);
  132. writel(data, &pll->pll_base);
  133. } else {
  134. writel(misc_data, &simple_pll->pll_misc);
  135. writel(data, &simple_pll->pll_base);
  136. }
  137. /* calculate the stable time */
  138. return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
  139. }
  140. void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
  141. unsigned divisor)
  142. {
  143. u32 *reg = get_periph_source_reg(periph_id);
  144. u32 value;
  145. value = readl(reg);
  146. value &= ~OUT_CLK_SOURCE_31_30_MASK;
  147. value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
  148. value &= ~OUT_CLK_DIVISOR_MASK;
  149. value |= divisor << OUT_CLK_DIVISOR_SHIFT;
  150. writel(value, reg);
  151. }
  152. int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
  153. unsigned source)
  154. {
  155. u32 *reg = get_periph_source_reg(periph_id);
  156. switch (mux_bits) {
  157. case MASK_BITS_31_30:
  158. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
  159. source << OUT_CLK_SOURCE_31_30_SHIFT);
  160. break;
  161. case MASK_BITS_31_29:
  162. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
  163. source << OUT_CLK_SOURCE_31_29_SHIFT);
  164. break;
  165. case MASK_BITS_31_28:
  166. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
  167. source << OUT_CLK_SOURCE_31_28_SHIFT);
  168. break;
  169. default:
  170. return -1;
  171. }
  172. return 0;
  173. }
  174. void clock_ll_set_source(enum periph_id periph_id, unsigned source)
  175. {
  176. clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
  177. }
  178. /**
  179. * Given the parent's rate and the required rate for the children, this works
  180. * out the peripheral clock divider to use, in 7.1 binary format.
  181. *
  182. * @param divider_bits number of divider bits (8 or 16)
  183. * @param parent_rate clock rate of parent clock in Hz
  184. * @param rate required clock rate for this clock
  185. * @return divider which should be used
  186. */
  187. static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
  188. unsigned long rate)
  189. {
  190. u64 divider = parent_rate * 2;
  191. unsigned max_divider = 1 << divider_bits;
  192. divider += rate - 1;
  193. do_div(divider, rate);
  194. if ((s64)divider - 2 < 0)
  195. return 0;
  196. if ((s64)divider - 2 >= max_divider)
  197. return -1;
  198. return divider - 2;
  199. }
  200. int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
  201. {
  202. struct clk_pll *pll = get_pll(clkid);
  203. int data = 0, div = 0, offset = 0;
  204. if (!clock_id_is_pll(clkid))
  205. return -1;
  206. if (pllout + 1 > pll_num_clkouts[clkid])
  207. return -1;
  208. div = clk_get_divider(8, pll_rate[clkid], rate);
  209. if (div < 0)
  210. return -1;
  211. /* out2 and out4 are in the high part of the register */
  212. if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
  213. offset = 16;
  214. data = (div << PLL_OUT_RATIO_SHIFT) |
  215. PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
  216. clrsetbits_le32(&pll->pll_out[pllout >> 1],
  217. PLL_OUT_RATIO_MASK << offset, data << offset);
  218. return 0;
  219. }
  220. /**
  221. * Given the parent's rate and the divider in 7.1 format, this works out the
  222. * resulting peripheral clock rate.
  223. *
  224. * @param parent_rate clock rate of parent clock in Hz
  225. * @param divider which should be used in 7.1 format
  226. * @return effective clock rate of peripheral
  227. */
  228. static unsigned long get_rate_from_divider(unsigned long parent_rate,
  229. int divider)
  230. {
  231. u64 rate;
  232. rate = (u64)parent_rate * 2;
  233. do_div(rate, divider + 2);
  234. return rate;
  235. }
  236. unsigned long clock_get_periph_rate(enum periph_id periph_id,
  237. enum clock_id parent)
  238. {
  239. u32 *reg = get_periph_source_reg(periph_id);
  240. return get_rate_from_divider(pll_rate[parent],
  241. (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
  242. }
  243. /**
  244. * Find the best available 7.1 format divisor given a parent clock rate and
  245. * required child clock rate. This function assumes that a second-stage
  246. * divisor is available which can divide by powers of 2 from 1 to 256.
  247. *
  248. * @param divider_bits number of divider bits (8 or 16)
  249. * @param parent_rate clock rate of parent clock in Hz
  250. * @param rate required clock rate for this clock
  251. * @param extra_div value for the second-stage divisor (not set if this
  252. * function returns -1.
  253. * @return divider which should be used, or -1 if nothing is valid
  254. *
  255. */
  256. static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
  257. unsigned long rate, int *extra_div)
  258. {
  259. int shift;
  260. int best_divider = -1;
  261. int best_error = rate;
  262. /* try dividers from 1 to 256 and find closest match */
  263. for (shift = 0; shift <= 8 && best_error > 0; shift++) {
  264. unsigned divided_parent = parent_rate >> shift;
  265. int divider = clk_get_divider(divider_bits, divided_parent,
  266. rate);
  267. unsigned effective_rate = get_rate_from_divider(divided_parent,
  268. divider);
  269. int error = rate - effective_rate;
  270. /* Given a valid divider, look for the lowest error */
  271. if (divider != -1 && error < best_error) {
  272. best_error = error;
  273. *extra_div = 1 << shift;
  274. best_divider = divider;
  275. }
  276. }
  277. /* return what we found - *extra_div will already be set */
  278. return best_divider;
  279. }
  280. /**
  281. * Adjust peripheral PLL to use the given divider and source.
  282. *
  283. * @param periph_id peripheral to adjust
  284. * @param source Source number (0-3 or 0-7)
  285. * @param mux_bits Number of mux bits (2 or 4)
  286. * @param divider Required divider in 7.1 or 15.1 format
  287. * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
  288. * for this peripheral)
  289. */
  290. static int adjust_periph_pll(enum periph_id periph_id, int source,
  291. int mux_bits, unsigned divider)
  292. {
  293. u32 *reg = get_periph_source_reg(periph_id);
  294. clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
  295. divider << OUT_CLK_DIVISOR_SHIFT);
  296. udelay(1);
  297. /* work out the source clock and set it */
  298. if (source < 0)
  299. return -1;
  300. clock_ll_set_source_bits(periph_id, mux_bits, source);
  301. udelay(2);
  302. return 0;
  303. }
  304. unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
  305. enum clock_id parent, unsigned rate, int *extra_div)
  306. {
  307. unsigned effective_rate;
  308. int mux_bits, divider_bits, source;
  309. int divider;
  310. int xdiv = 0;
  311. /* work out the source clock and set it */
  312. source = get_periph_clock_source(periph_id, parent, &mux_bits,
  313. &divider_bits);
  314. divider = find_best_divider(divider_bits, pll_rate[parent],
  315. rate, &xdiv);
  316. if (extra_div)
  317. *extra_div = xdiv;
  318. assert(divider >= 0);
  319. if (adjust_periph_pll(periph_id, source, mux_bits, divider))
  320. return -1U;
  321. debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
  322. get_periph_source_reg(periph_id),
  323. readl(get_periph_source_reg(periph_id)));
  324. /* Check what we ended up with. This shouldn't matter though */
  325. effective_rate = clock_get_periph_rate(periph_id, parent);
  326. if (extra_div)
  327. effective_rate /= *extra_div;
  328. if (rate != effective_rate)
  329. debug("Requested clock rate %u not honored (got %u)\n",
  330. rate, effective_rate);
  331. return effective_rate;
  332. }
  333. unsigned clock_start_periph_pll(enum periph_id periph_id,
  334. enum clock_id parent, unsigned rate)
  335. {
  336. unsigned effective_rate;
  337. reset_set_enable(periph_id, 1);
  338. clock_enable(periph_id);
  339. effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
  340. NULL);
  341. reset_set_enable(periph_id, 0);
  342. return effective_rate;
  343. }
  344. void clock_enable(enum periph_id clkid)
  345. {
  346. clock_set_enable(clkid, 1);
  347. }
  348. void clock_disable(enum periph_id clkid)
  349. {
  350. clock_set_enable(clkid, 0);
  351. }
  352. void reset_periph(enum periph_id periph_id, int us_delay)
  353. {
  354. /* Put peripheral into reset */
  355. reset_set_enable(periph_id, 1);
  356. udelay(us_delay);
  357. /* Remove reset */
  358. reset_set_enable(periph_id, 0);
  359. udelay(us_delay);
  360. }
  361. void reset_cmplx_set_enable(int cpu, int which, int reset)
  362. {
  363. struct clk_rst_ctlr *clkrst =
  364. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  365. u32 mask;
  366. /* Form the mask, which depends on the cpu chosen (2 or 4) */
  367. assert(cpu >= 0 && cpu < MAX_NUM_CPU);
  368. mask = which << cpu;
  369. /* either enable or disable those reset for that CPU */
  370. if (reset)
  371. writel(mask, &clkrst->crc_cpu_cmplx_set);
  372. else
  373. writel(mask, &clkrst->crc_cpu_cmplx_clr);
  374. }
  375. unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
  376. {
  377. return parent_rate;
  378. }
  379. unsigned clock_get_rate(enum clock_id clkid)
  380. {
  381. struct clk_pll *pll;
  382. u32 base, divm;
  383. u64 parent_rate, rate;
  384. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  385. parent_rate = osc_freq[clock_get_osc_freq()];
  386. if (clkid == CLOCK_ID_OSC)
  387. return parent_rate;
  388. if (clkid == CLOCK_ID_CLK_M)
  389. return clk_m_get_rate(parent_rate);
  390. pll = get_pll(clkid);
  391. if (!pll)
  392. return 0;
  393. base = readl(&pll->pll_base);
  394. rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
  395. divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
  396. /*
  397. * PLLU uses p_mask/p_shift for VCO on all but T210,
  398. * T210 uses normal DIVP. Handled in pllinfo table.
  399. */
  400. #ifdef CONFIG_TEGRA210
  401. /*
  402. * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
  403. * not applied. pllP_out2 does have divp applied. All other pllP_outN
  404. * are divided down from pllP_out0. We only support pllP_out0 in
  405. * U-Boot at the time of writing this comment.
  406. */
  407. if (clkid != CLOCK_ID_PERIPH)
  408. #endif
  409. divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
  410. do_div(rate, divm);
  411. return rate;
  412. }
  413. /**
  414. * Set the output frequency you want for each PLL clock.
  415. * PLL output frequencies are programmed by setting their N, M and P values.
  416. * The governing equations are:
  417. * VCO = (Fi / m) * n, Fo = VCO / (2^p)
  418. * where Fo is the output frequency from the PLL.
  419. * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
  420. * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
  421. * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
  422. *
  423. * @param n PLL feedback divider(DIVN)
  424. * @param m PLL input divider(DIVN)
  425. * @param p post divider(DIVP)
  426. * @param cpcon base PLL charge pump(CPCON)
  427. * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
  428. * be overridden), 1 if PLL is already correct
  429. */
  430. int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
  431. {
  432. u32 base_reg, misc_reg;
  433. struct clk_pll *pll;
  434. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  435. pll = get_pll(clkid);
  436. base_reg = readl(&pll->pll_base);
  437. /* Set BYPASS, m, n and p to PLL_BASE */
  438. base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
  439. base_reg |= m << pllinfo->m_shift;
  440. base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
  441. base_reg |= n << pllinfo->n_shift;
  442. base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
  443. base_reg |= p << pllinfo->p_shift;
  444. if (clkid == CLOCK_ID_PERIPH) {
  445. /*
  446. * If the PLL is already set up, check that it is correct
  447. * and record this info for clock_verify() to check.
  448. */
  449. if (base_reg & PLL_BASE_OVRRIDE_MASK) {
  450. base_reg |= PLL_ENABLE_MASK;
  451. if (base_reg != readl(&pll->pll_base))
  452. pllp_valid = 0;
  453. return pllp_valid ? 1 : -1;
  454. }
  455. base_reg |= PLL_BASE_OVRRIDE_MASK;
  456. }
  457. base_reg |= PLL_BYPASS_MASK;
  458. writel(base_reg, &pll->pll_base);
  459. /* Set cpcon (KCP) to PLL_MISC */
  460. misc_reg = readl(&pll->pll_misc);
  461. misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
  462. misc_reg |= cpcon << pllinfo->kcp_shift;
  463. writel(misc_reg, &pll->pll_misc);
  464. /* Enable PLL */
  465. base_reg |= PLL_ENABLE_MASK;
  466. writel(base_reg, &pll->pll_base);
  467. /* Disable BYPASS */
  468. base_reg &= ~PLL_BYPASS_MASK;
  469. writel(base_reg, &pll->pll_base);
  470. return 0;
  471. }
  472. void clock_ll_start_uart(enum periph_id periph_id)
  473. {
  474. /* Assert UART reset and enable clock */
  475. reset_set_enable(periph_id, 1);
  476. clock_enable(periph_id);
  477. clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
  478. /* wait for 2us */
  479. udelay(2);
  480. /* De-assert reset to UART */
  481. reset_set_enable(periph_id, 0);
  482. }
  483. #if CONFIG_IS_ENABLED(OF_CONTROL)
  484. int clock_decode_periph_id(const void *blob, int node)
  485. {
  486. enum periph_id id;
  487. u32 cell[2];
  488. int err;
  489. err = fdtdec_get_int_array(blob, node, "clocks", cell,
  490. ARRAY_SIZE(cell));
  491. if (err)
  492. return -1;
  493. id = clk_id_to_periph_id(cell[1]);
  494. assert(clock_periph_id_isvalid(id));
  495. return id;
  496. }
  497. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  498. int clock_verify(void)
  499. {
  500. struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
  501. u32 reg = readl(&pll->pll_base);
  502. if (!pllp_valid) {
  503. printf("Warning: PLLP %x is not correct\n", reg);
  504. return -1;
  505. }
  506. debug("PLLP %x is correct\n", reg);
  507. return 0;
  508. }
  509. void clock_init(void)
  510. {
  511. pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
  512. pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
  513. pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
  514. pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
  515. pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
  516. pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
  517. pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
  518. pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
  519. pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
  520. debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
  521. debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
  522. debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
  523. debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
  524. debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
  525. debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
  526. debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
  527. debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
  528. }
  529. static void set_avp_clock_source(u32 src)
  530. {
  531. struct clk_rst_ctlr *clkrst =
  532. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  533. u32 val;
  534. val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
  535. (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
  536. (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
  537. (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
  538. (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
  539. writel(val, &clkrst->crc_sclk_brst_pol);
  540. udelay(3);
  541. }
  542. /*
  543. * This function is useful on Tegra30, and any later SoCs that have compatible
  544. * PLLP configuration registers.
  545. * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
  546. */
  547. void tegra30_set_up_pllp(void)
  548. {
  549. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  550. u32 reg;
  551. /*
  552. * Based on the Tegra TRM, the system clock (which is the AVP clock) can
  553. * run up to 275MHz. On power on, the default sytem clock source is set
  554. * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
  555. * 408MHz which is beyond system clock's upper limit.
  556. *
  557. * The fix is to set the system clock to CLK_M before initializing PLLP,
  558. * and then switch back to PLLP_OUT4, which has an appropriate divider
  559. * configured, after PLLP has been configured
  560. */
  561. set_avp_clock_source(SCLK_SOURCE_CLKM);
  562. /*
  563. * PLLP output frequency set to 408Mhz
  564. * PLLC output frequency set to 228Mhz
  565. */
  566. switch (clock_get_osc_freq()) {
  567. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  568. clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
  569. clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
  570. break;
  571. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  572. clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
  573. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  574. break;
  575. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  576. clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
  577. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  578. break;
  579. case CLOCK_OSC_FREQ_19_2:
  580. default:
  581. /*
  582. * These are not supported. It is too early to print a
  583. * message and the UART likely won't work anyway due to the
  584. * oscillator being wrong.
  585. */
  586. break;
  587. }
  588. /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
  589. /* OUT1, 2 */
  590. /* Assert RSTN before enable */
  591. reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
  592. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  593. /* Set divisor and reenable */
  594. reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
  595. | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
  596. | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
  597. | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
  598. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  599. /* OUT3, 4 */
  600. /* Assert RSTN before enable */
  601. reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
  602. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  603. /* Set divisor and reenable */
  604. reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
  605. | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
  606. | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
  607. | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
  608. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  609. set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
  610. }
  611. int clock_external_output(int clk_id)
  612. {
  613. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  614. if (clk_id >= 1 && clk_id <= 3) {
  615. setbits_le32(&pmc->pmc_clk_out_cntrl,
  616. 1 << (2 + (clk_id - 1) * 8));
  617. } else {
  618. printf("%s: Unknown output clock id %d\n", __func__, clk_id);
  619. return -EINVAL;
  620. }
  621. return 0;
  622. }