clock.h 11 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /* Tegra clock control functions */
  7. #ifndef _TEGRA_CLOCK_H_
  8. #define _TEGRA_CLOCK_H_
  9. /* Set of oscillator frequencies supported in the internal API. */
  10. enum clock_osc_freq {
  11. /* All in MHz, so 13_0 is 13.0MHz */
  12. CLOCK_OSC_FREQ_13_0,
  13. CLOCK_OSC_FREQ_19_2,
  14. CLOCK_OSC_FREQ_12_0,
  15. CLOCK_OSC_FREQ_26_0,
  16. CLOCK_OSC_FREQ_38_4,
  17. CLOCK_OSC_FREQ_48_0,
  18. CLOCK_OSC_FREQ_COUNT,
  19. };
  20. /*
  21. * Note that no Tegra clock register actually uses all of bits 31:28 as
  22. * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
  23. * those cases, nothing is stored in the bits about the mux field, so it's
  24. * safe to pretend that the mux field extends all the way to the end of the
  25. * register. As such, the U-Boot clock driver is currently a bit lazy, and
  26. * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
  27. * them all together and pretends they're all 31:28.
  28. */
  29. enum {
  30. MASK_BITS_31_30,
  31. MASK_BITS_31_29,
  32. MASK_BITS_31_28,
  33. };
  34. #include <asm/arch/clock-tables.h>
  35. /* PLL stabilization delay in usec */
  36. #define CLOCK_PLL_STABLE_DELAY_US 300
  37. /* return the current oscillator clock frequency */
  38. enum clock_osc_freq clock_get_osc_freq(void);
  39. /* return the clk_m frequency */
  40. unsigned int clk_m_get_rate(unsigned int parent_rate);
  41. /**
  42. * Start PLL using the provided configuration parameters.
  43. *
  44. * @param id clock id
  45. * @param divm input divider
  46. * @param divn feedback divider
  47. * @param divp post divider 2^n
  48. * @param cpcon charge pump setup control
  49. * @param lfcon loop filter setup control
  50. *
  51. * @returns monotonic time in us that the PLL will be stable
  52. */
  53. unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
  54. u32 divp, u32 cpcon, u32 lfcon);
  55. /**
  56. * Set PLL output frequency
  57. *
  58. * @param clkid clock id
  59. * @param pllout pll output id
  60. * @param rate desired output rate
  61. *
  62. * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
  63. */
  64. int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
  65. unsigned rate);
  66. /**
  67. * Read low-level parameters of a PLL.
  68. *
  69. * @param id clock id to read (note: USB is not supported)
  70. * @param divm returns input divider
  71. * @param divn returns feedback divider
  72. * @param divp returns post divider 2^n
  73. * @param cpcon returns charge pump setup control
  74. * @param lfcon returns loop filter setup control
  75. *
  76. * @returns 0 if ok, -1 on error (invalid clock id)
  77. */
  78. int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
  79. u32 *divp, u32 *cpcon, u32 *lfcon);
  80. /*
  81. * Enable a clock
  82. *
  83. * @param id clock id
  84. */
  85. void clock_enable(enum periph_id clkid);
  86. /*
  87. * Disable a clock
  88. *
  89. * @param id clock id
  90. */
  91. void clock_disable(enum periph_id clkid);
  92. /*
  93. * Set whether a clock is enabled or disabled.
  94. *
  95. * @param id clock id
  96. * @param enable 1 to enable, 0 to disable
  97. */
  98. void clock_set_enable(enum periph_id clkid, int enable);
  99. /**
  100. * Reset a peripheral. This puts it in reset, waits for a delay, then takes
  101. * it out of reset and waits for th delay again.
  102. *
  103. * @param periph_id peripheral to reset
  104. * @param us_delay time to delay in microseconds
  105. */
  106. void reset_periph(enum periph_id periph_id, int us_delay);
  107. /**
  108. * Put a peripheral into or out of reset.
  109. *
  110. * @param periph_id peripheral to reset
  111. * @param enable 1 to put into reset, 0 to take out of reset
  112. */
  113. void reset_set_enable(enum periph_id periph_id, int enable);
  114. /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
  115. enum crc_reset_id {
  116. /* Things we can hold in reset for each CPU */
  117. crc_rst_cpu = 1,
  118. crc_rst_de = 1 << 4, /* What is de? */
  119. crc_rst_watchdog = 1 << 8,
  120. crc_rst_debug = 1 << 12,
  121. };
  122. /**
  123. * Put parts of the CPU complex into or out of reset.\
  124. *
  125. * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
  126. * @param which which parts of the complex to affect (OR of crc_reset_id)
  127. * @param reset 1 to assert reset, 0 to de-assert
  128. */
  129. void reset_cmplx_set_enable(int cpu, int which, int reset);
  130. /**
  131. * Set the source for a peripheral clock. This plus the divisor sets the
  132. * clock rate. You need to look up the datasheet to see the meaning of the
  133. * source parameter as it changes for each peripheral.
  134. *
  135. * Warning: This function is only for use pre-relocation. Please use
  136. * clock_start_periph_pll() instead.
  137. *
  138. * @param periph_id peripheral to adjust
  139. * @param source source clock (0, 1, 2 or 3)
  140. */
  141. void clock_ll_set_source(enum periph_id periph_id, unsigned source);
  142. /**
  143. * This function is similar to clock_ll_set_source() except that it can be
  144. * used for clocks with more than 2 mux bits.
  145. *
  146. * @param periph_id peripheral to adjust
  147. * @param mux_bits number of mux bits for the clock
  148. * @param source source clock (0-15 depending on mux_bits)
  149. */
  150. int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
  151. unsigned source);
  152. /**
  153. * Set the source and divisor for a peripheral clock. This sets the
  154. * clock rate. You need to look up the datasheet to see the meaning of the
  155. * source parameter as it changes for each peripheral.
  156. *
  157. * Warning: This function is only for use pre-relocation. Please use
  158. * clock_start_periph_pll() instead.
  159. *
  160. * @param periph_id peripheral to adjust
  161. * @param source source clock (0, 1, 2 or 3)
  162. * @param divisor divisor value to use
  163. */
  164. void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
  165. unsigned divisor);
  166. /**
  167. * Start a peripheral PLL clock at the given rate. This also resets the
  168. * peripheral.
  169. *
  170. * @param periph_id peripheral to start
  171. * @param parent PLL id of required parent clock
  172. * @param rate Required clock rate in Hz
  173. * @return rate selected in Hz, or -1U if something went wrong
  174. */
  175. unsigned clock_start_periph_pll(enum periph_id periph_id,
  176. enum clock_id parent, unsigned rate);
  177. /**
  178. * Returns the rate of a peripheral clock in Hz. Since the caller almost
  179. * certainly knows the parent clock (having just set it) we require that
  180. * this be passed in so we don't need to work it out.
  181. *
  182. * @param periph_id peripheral to start
  183. * @param parent PLL id of parent clock (used to calculate rate, you
  184. * must know this!)
  185. * @return clock rate of peripheral in Hz
  186. */
  187. unsigned long clock_get_periph_rate(enum periph_id periph_id,
  188. enum clock_id parent);
  189. /**
  190. * Adjust peripheral PLL clock to the given rate. This does not reset the
  191. * peripheral. If a second stage divisor is not available, pass NULL for
  192. * extra_div. If it is available, then this parameter will return the
  193. * divisor selected (which will be a power of 2 from 1 to 256).
  194. *
  195. * @param periph_id peripheral to start
  196. * @param parent PLL id of required parent clock
  197. * @param rate Required clock rate in Hz
  198. * @param extra_div value for the second-stage divisor (NULL if one is
  199. not available)
  200. * @return rate selected in Hz, or -1U if something went wrong
  201. */
  202. unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
  203. enum clock_id parent, unsigned rate, int *extra_div);
  204. /**
  205. * Returns the clock rate of a specified clock, in Hz.
  206. *
  207. * @param parent PLL id of clock to check
  208. * @return rate of clock in Hz
  209. */
  210. unsigned clock_get_rate(enum clock_id clkid);
  211. /**
  212. * Start up a UART using low-level calls
  213. *
  214. * Prior to relocation clock_start_periph_pll() cannot be called. This
  215. * function provides a way to set up a UART using low-level calls which
  216. * do not require BSS.
  217. *
  218. * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
  219. */
  220. void clock_ll_start_uart(enum periph_id periph_id);
  221. /**
  222. * Decode a peripheral ID from a device tree node.
  223. *
  224. * This works by looking up the peripheral's 'clocks' node and reading out
  225. * the second cell, which is the clock number / peripheral ID.
  226. *
  227. * @param blob FDT blob to use
  228. * @param node Node to look at
  229. * @return peripheral ID, or PERIPH_ID_NONE if none
  230. */
  231. enum periph_id clock_decode_periph_id(const void *blob, int node);
  232. /**
  233. * Checks if the oscillator bypass is enabled (XOBP bit)
  234. *
  235. * @return 1 if bypass is enabled, 0 if not
  236. */
  237. int clock_get_osc_bypass(void);
  238. /*
  239. * Checks that clocks are valid and prints a warning if not
  240. *
  241. * @return 0 if ok, -1 on error
  242. */
  243. int clock_verify(void);
  244. /* Initialize the clocks */
  245. void clock_init(void);
  246. /* Initialize the PLLs */
  247. void clock_early_init(void);
  248. /* Returns a pointer to the clock source register for a peripheral */
  249. u32 *get_periph_source_reg(enum periph_id periph_id);
  250. /* Returns a pointer to the given 'simple' PLL */
  251. struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
  252. /**
  253. * Given a peripheral ID and the required source clock, this returns which
  254. * value should be programmed into the source mux for that peripheral.
  255. *
  256. * There is special code here to handle the one source type with 5 sources.
  257. *
  258. * @param periph_id peripheral to start
  259. * @param source PLL id of required parent clock
  260. * @param mux_bits Set to number of bits in mux register: 2 or 4
  261. * @param divider_bits Set to number of divider bits (8 or 16)
  262. * @return mux value (0-4, or -1 if not found)
  263. */
  264. int get_periph_clock_source(enum periph_id periph_id,
  265. enum clock_id parent, int *mux_bits, int *divider_bits);
  266. /*
  267. * Convert a device tree clock ID to our peripheral ID. They are mostly
  268. * the same but we are very cautious so we check that a valid clock ID is
  269. * provided.
  270. *
  271. * @param clk_id Clock ID according to tegra30 device tree binding
  272. * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  273. */
  274. enum periph_id clk_id_to_periph_id(int clk_id);
  275. /**
  276. * Set the output frequency you want for each PLL clock.
  277. * PLL output frequencies are programmed by setting their N, M and P values.
  278. * The governing equations are:
  279. * VCO = (Fi / m) * n, Fo = VCO / (2^p)
  280. * where Fo is the output frequency from the PLL.
  281. * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
  282. * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
  283. * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
  284. *
  285. * @param n PLL feedback divider(DIVN)
  286. * @param m PLL input divider(DIVN)
  287. * @param p post divider(DIVP)
  288. * @param cpcon base PLL charge pump(CPCON)
  289. * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
  290. * be overridden), 1 if PLL is already correct
  291. */
  292. int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
  293. /* return 1 if a peripheral ID is in range */
  294. #define clock_type_id_isvalid(id) ((id) >= 0 && \
  295. (id) < CLOCK_TYPE_COUNT)
  296. /* return 1 if a periphc_internal_id is in range */
  297. #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
  298. (id) < PERIPHC_COUNT)
  299. /* SoC-specific TSC init */
  300. void arch_timer_init(void);
  301. void tegra30_set_up_pllp(void);
  302. /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
  303. #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3)
  304. struct clk_pll_info {
  305. u32 m_shift:5; /* DIVM_SHIFT */
  306. u32 n_shift:5; /* DIVN_SHIFT */
  307. u32 p_shift:5; /* DIVP_SHIFT */
  308. u32 kcp_shift:5; /* KCP/cpcon SHIFT */
  309. u32 kvco_shift:5; /* KVCO/lfcon SHIFT */
  310. u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */
  311. u32 rsvd:1;
  312. u32 m_mask:10; /* DIVM_MASK */
  313. u32 n_mask:12; /* DIVN_MASK */
  314. u32 p_mask:10; /* DIVP_MASK or VCO_MASK */
  315. u32 kcp_mask:10; /* KCP/CPCON MASK */
  316. u32 kvco_mask:10; /* KVCO/LFCON MASK */
  317. u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */
  318. u32 rsvd2:6;
  319. };
  320. extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
  321. /**
  322. * Enable output clock for external peripherals
  323. *
  324. * @param clk_id Clock ID to output (1, 2 or 3)
  325. * @return 0 if OK. -ve on error
  326. */
  327. int clock_external_output(int clk_id);
  328. #endif /* _TEGRA_CLOCK_H_ */