sunxi_nand.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
  4. * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
  5. *
  6. * Derived from:
  7. * https://github.com/yuq/sunxi-nfc-mtd
  8. * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
  9. *
  10. * https://github.com/hno/Allwinner-Info
  11. * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  12. *
  13. * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  14. * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. */
  26. #include <common.h>
  27. #include <fdtdec.h>
  28. #include <memalign.h>
  29. #include <nand.h>
  30. #include <dm/devres.h>
  31. #include <linux/err.h>
  32. #include <linux/kernel.h>
  33. #include <linux/mtd/mtd.h>
  34. #include <linux/mtd/rawnand.h>
  35. #include <linux/mtd/partitions.h>
  36. #include <linux/io.h>
  37. #include <asm/gpio.h>
  38. #include <asm/arch/clock.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #define NFC_REG_CTL 0x0000
  41. #define NFC_REG_ST 0x0004
  42. #define NFC_REG_INT 0x0008
  43. #define NFC_REG_TIMING_CTL 0x000C
  44. #define NFC_REG_TIMING_CFG 0x0010
  45. #define NFC_REG_ADDR_LOW 0x0014
  46. #define NFC_REG_ADDR_HIGH 0x0018
  47. #define NFC_REG_SECTOR_NUM 0x001C
  48. #define NFC_REG_CNT 0x0020
  49. #define NFC_REG_CMD 0x0024
  50. #define NFC_REG_RCMD_SET 0x0028
  51. #define NFC_REG_WCMD_SET 0x002C
  52. #define NFC_REG_IO_DATA 0x0030
  53. #define NFC_REG_ECC_CTL 0x0034
  54. #define NFC_REG_ECC_ST 0x0038
  55. #define NFC_REG_DEBUG 0x003C
  56. #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
  57. #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
  58. #define NFC_REG_SPARE_AREA 0x00A0
  59. #define NFC_REG_PAT_ID 0x00A4
  60. #define NFC_RAM0_BASE 0x0400
  61. #define NFC_RAM1_BASE 0x0800
  62. /* define bit use in NFC_CTL */
  63. #define NFC_EN BIT(0)
  64. #define NFC_RESET BIT(1)
  65. #define NFC_BUS_WIDTH_MSK BIT(2)
  66. #define NFC_BUS_WIDTH_8 (0 << 2)
  67. #define NFC_BUS_WIDTH_16 (1 << 2)
  68. #define NFC_RB_SEL_MSK BIT(3)
  69. #define NFC_RB_SEL(x) ((x) << 3)
  70. #define NFC_CE_SEL_MSK (0x7 << 24)
  71. #define NFC_CE_SEL(x) ((x) << 24)
  72. #define NFC_CE_CTL BIT(6)
  73. #define NFC_PAGE_SHIFT_MSK (0xf << 8)
  74. #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
  75. #define NFC_SAM BIT(12)
  76. #define NFC_RAM_METHOD BIT(14)
  77. #define NFC_DEBUG_CTL BIT(31)
  78. /* define bit use in NFC_ST */
  79. #define NFC_RB_B2R BIT(0)
  80. #define NFC_CMD_INT_FLAG BIT(1)
  81. #define NFC_DMA_INT_FLAG BIT(2)
  82. #define NFC_CMD_FIFO_STATUS BIT(3)
  83. #define NFC_STA BIT(4)
  84. #define NFC_NATCH_INT_FLAG BIT(5)
  85. #define NFC_RB_STATE(x) BIT(x + 8)
  86. /* define bit use in NFC_INT */
  87. #define NFC_B2R_INT_ENABLE BIT(0)
  88. #define NFC_CMD_INT_ENABLE BIT(1)
  89. #define NFC_DMA_INT_ENABLE BIT(2)
  90. #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
  91. NFC_CMD_INT_ENABLE | \
  92. NFC_DMA_INT_ENABLE)
  93. /* define bit use in NFC_TIMING_CTL */
  94. #define NFC_TIMING_CTL_EDO BIT(8)
  95. /* define NFC_TIMING_CFG register layout */
  96. #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
  97. (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
  98. (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
  99. (((tCAD) & 0x7) << 8))
  100. /* define bit use in NFC_CMD */
  101. #define NFC_CMD_LOW_BYTE_MSK 0xff
  102. #define NFC_CMD_HIGH_BYTE_MSK (0xff << 8)
  103. #define NFC_CMD(x) (x)
  104. #define NFC_ADR_NUM_MSK (0x7 << 16)
  105. #define NFC_ADR_NUM(x) (((x) - 1) << 16)
  106. #define NFC_SEND_ADR BIT(19)
  107. #define NFC_ACCESS_DIR BIT(20)
  108. #define NFC_DATA_TRANS BIT(21)
  109. #define NFC_SEND_CMD1 BIT(22)
  110. #define NFC_WAIT_FLAG BIT(23)
  111. #define NFC_SEND_CMD2 BIT(24)
  112. #define NFC_SEQ BIT(25)
  113. #define NFC_DATA_SWAP_METHOD BIT(26)
  114. #define NFC_ROW_AUTO_INC BIT(27)
  115. #define NFC_SEND_CMD3 BIT(28)
  116. #define NFC_SEND_CMD4 BIT(29)
  117. #define NFC_CMD_TYPE_MSK (0x3 << 30)
  118. #define NFC_NORMAL_OP (0 << 30)
  119. #define NFC_ECC_OP (1 << 30)
  120. #define NFC_PAGE_OP (2 << 30)
  121. /* define bit use in NFC_RCMD_SET */
  122. #define NFC_READ_CMD_MSK 0xff
  123. #define NFC_RND_READ_CMD0_MSK (0xff << 8)
  124. #define NFC_RND_READ_CMD1_MSK (0xff << 16)
  125. /* define bit use in NFC_WCMD_SET */
  126. #define NFC_PROGRAM_CMD_MSK 0xff
  127. #define NFC_RND_WRITE_CMD_MSK (0xff << 8)
  128. #define NFC_READ_CMD0_MSK (0xff << 16)
  129. #define NFC_READ_CMD1_MSK (0xff << 24)
  130. /* define bit use in NFC_ECC_CTL */
  131. #define NFC_ECC_EN BIT(0)
  132. #define NFC_ECC_PIPELINE BIT(3)
  133. #define NFC_ECC_EXCEPTION BIT(4)
  134. #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
  135. #define NFC_ECC_BLOCK_512 (1 << 5)
  136. #define NFC_RANDOM_EN BIT(9)
  137. #define NFC_RANDOM_DIRECTION BIT(10)
  138. #define NFC_ECC_MODE_MSK (0xf << 12)
  139. #define NFC_ECC_MODE(x) ((x) << 12)
  140. #define NFC_RANDOM_SEED_MSK (0x7fff << 16)
  141. #define NFC_RANDOM_SEED(x) ((x) << 16)
  142. /* define bit use in NFC_ECC_ST */
  143. #define NFC_ECC_ERR(x) BIT(x)
  144. #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
  145. #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
  146. #define NFC_DEFAULT_TIMEOUT_MS 1000
  147. #define NFC_SRAM_SIZE 1024
  148. #define NFC_MAX_CS 7
  149. /*
  150. * Ready/Busy detection type: describes the Ready/Busy detection modes
  151. *
  152. * @RB_NONE: no external detection available, rely on STATUS command
  153. * and software timeouts
  154. * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
  155. * pin of the NAND flash chip must be connected to one of the
  156. * native NAND R/B pins (those which can be muxed to the NAND
  157. * Controller)
  158. * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
  159. * pin of the NAND flash chip must be connected to a GPIO capable
  160. * pin.
  161. */
  162. enum sunxi_nand_rb_type {
  163. RB_NONE,
  164. RB_NATIVE,
  165. RB_GPIO,
  166. };
  167. /*
  168. * Ready/Busy structure: stores information related to Ready/Busy detection
  169. *
  170. * @type: the Ready/Busy detection mode
  171. * @info: information related to the R/B detection mode. Either a gpio
  172. * id or a native R/B id (those supported by the NAND controller).
  173. */
  174. struct sunxi_nand_rb {
  175. enum sunxi_nand_rb_type type;
  176. union {
  177. struct gpio_desc gpio;
  178. int nativeid;
  179. } info;
  180. };
  181. /*
  182. * Chip Select structure: stores information related to NAND Chip Select
  183. *
  184. * @cs: the NAND CS id used to communicate with a NAND Chip
  185. * @rb: the Ready/Busy description
  186. */
  187. struct sunxi_nand_chip_sel {
  188. u8 cs;
  189. struct sunxi_nand_rb rb;
  190. };
  191. /*
  192. * sunxi HW ECC infos: stores information related to HW ECC support
  193. *
  194. * @mode: the sunxi ECC mode field deduced from ECC requirements
  195. * @layout: the OOB layout depending on the ECC requirements and the
  196. * selected ECC mode
  197. */
  198. struct sunxi_nand_hw_ecc {
  199. int mode;
  200. struct nand_ecclayout layout;
  201. };
  202. /*
  203. * NAND chip structure: stores NAND chip device related information
  204. *
  205. * @node: used to store NAND chips into a list
  206. * @nand: base NAND chip structure
  207. * @mtd: base MTD structure
  208. * @clk_rate: clk_rate required for this NAND chip
  209. * @timing_cfg TIMING_CFG register value for this NAND chip
  210. * @selected: current active CS
  211. * @nsels: number of CS lines required by the NAND chip
  212. * @sels: array of CS lines descriptions
  213. */
  214. struct sunxi_nand_chip {
  215. struct list_head node;
  216. struct nand_chip nand;
  217. unsigned long clk_rate;
  218. u32 timing_cfg;
  219. u32 timing_ctl;
  220. int selected;
  221. int addr_cycles;
  222. u32 addr[2];
  223. int cmd_cycles;
  224. u8 cmd[2];
  225. int nsels;
  226. struct sunxi_nand_chip_sel sels[0];
  227. };
  228. static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
  229. {
  230. return container_of(nand, struct sunxi_nand_chip, nand);
  231. }
  232. /*
  233. * NAND Controller structure: stores sunxi NAND controller information
  234. *
  235. * @controller: base controller structure
  236. * @dev: parent device (used to print error messages)
  237. * @regs: NAND controller registers
  238. * @ahb_clk: NAND Controller AHB clock
  239. * @mod_clk: NAND Controller mod clock
  240. * @assigned_cs: bitmask describing already assigned CS lines
  241. * @clk_rate: NAND controller current clock rate
  242. * @chips: a list containing all the NAND chips attached to
  243. * this NAND controller
  244. * @complete: a completion object used to wait for NAND
  245. * controller events
  246. */
  247. struct sunxi_nfc {
  248. struct nand_hw_control controller;
  249. struct device *dev;
  250. void __iomem *regs;
  251. struct clk *ahb_clk;
  252. struct clk *mod_clk;
  253. unsigned long assigned_cs;
  254. unsigned long clk_rate;
  255. struct list_head chips;
  256. };
  257. static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
  258. {
  259. return container_of(ctrl, struct sunxi_nfc, controller);
  260. }
  261. static void sunxi_nfc_set_clk_rate(unsigned long hz)
  262. {
  263. struct sunxi_ccm_reg *const ccm =
  264. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  265. int div_m, div_n;
  266. div_m = (clock_get_pll6() + hz - 1) / hz;
  267. for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
  268. if (div_m % 2)
  269. div_m++;
  270. div_m >>= 1;
  271. }
  272. if (div_m > 16)
  273. div_m = 16;
  274. /* config mod clock */
  275. writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
  276. CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
  277. &ccm->nand0_clk_cfg);
  278. /* gate on nand clock */
  279. setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
  280. #ifdef CONFIG_MACH_SUN9I
  281. setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
  282. #else
  283. setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
  284. #endif
  285. }
  286. static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
  287. unsigned int timeout_ms)
  288. {
  289. unsigned int timeout_ticks;
  290. u32 time_start, status;
  291. int ret = -ETIMEDOUT;
  292. if (!timeout_ms)
  293. timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
  294. timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
  295. time_start = get_timer(0);
  296. do {
  297. status = readl(nfc->regs + NFC_REG_ST);
  298. if ((status & flags) == flags) {
  299. ret = 0;
  300. break;
  301. }
  302. udelay(1);
  303. } while (get_timer(time_start) < timeout_ticks);
  304. writel(status & flags, nfc->regs + NFC_REG_ST);
  305. return ret;
  306. }
  307. static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
  308. {
  309. unsigned long timeout = (CONFIG_SYS_HZ *
  310. NFC_DEFAULT_TIMEOUT_MS) / 1000;
  311. u32 time_start;
  312. time_start = get_timer(0);
  313. do {
  314. if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
  315. return 0;
  316. } while (get_timer(time_start) < timeout);
  317. dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
  318. return -ETIMEDOUT;
  319. }
  320. static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
  321. {
  322. unsigned long timeout = (CONFIG_SYS_HZ *
  323. NFC_DEFAULT_TIMEOUT_MS) / 1000;
  324. u32 time_start;
  325. writel(0, nfc->regs + NFC_REG_ECC_CTL);
  326. writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
  327. time_start = get_timer(0);
  328. do {
  329. if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
  330. return 0;
  331. } while (get_timer(time_start) < timeout);
  332. dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
  333. return -ETIMEDOUT;
  334. }
  335. static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
  336. {
  337. struct nand_chip *nand = mtd_to_nand(mtd);
  338. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  339. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  340. struct sunxi_nand_rb *rb;
  341. unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
  342. int ret;
  343. if (sunxi_nand->selected < 0)
  344. return 0;
  345. rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
  346. switch (rb->type) {
  347. case RB_NATIVE:
  348. ret = !!(readl(nfc->regs + NFC_REG_ST) &
  349. NFC_RB_STATE(rb->info.nativeid));
  350. if (ret)
  351. break;
  352. sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
  353. ret = !!(readl(nfc->regs + NFC_REG_ST) &
  354. NFC_RB_STATE(rb->info.nativeid));
  355. break;
  356. case RB_GPIO:
  357. ret = dm_gpio_get_value(&rb->info.gpio);
  358. break;
  359. case RB_NONE:
  360. default:
  361. ret = 0;
  362. dev_err(nfc->dev, "cannot check R/B NAND status!\n");
  363. break;
  364. }
  365. return ret;
  366. }
  367. static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
  368. {
  369. struct nand_chip *nand = mtd_to_nand(mtd);
  370. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  371. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  372. struct sunxi_nand_chip_sel *sel;
  373. u32 ctl;
  374. if (chip > 0 && chip >= sunxi_nand->nsels)
  375. return;
  376. if (chip == sunxi_nand->selected)
  377. return;
  378. ctl = readl(nfc->regs + NFC_REG_CTL) &
  379. ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
  380. if (chip >= 0) {
  381. sel = &sunxi_nand->sels[chip];
  382. ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
  383. NFC_PAGE_SHIFT(nand->page_shift - 10);
  384. if (sel->rb.type == RB_NONE) {
  385. nand->dev_ready = NULL;
  386. } else {
  387. nand->dev_ready = sunxi_nfc_dev_ready;
  388. if (sel->rb.type == RB_NATIVE)
  389. ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
  390. }
  391. writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
  392. if (nfc->clk_rate != sunxi_nand->clk_rate) {
  393. sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
  394. nfc->clk_rate = sunxi_nand->clk_rate;
  395. }
  396. }
  397. writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
  398. writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
  399. writel(ctl, nfc->regs + NFC_REG_CTL);
  400. sunxi_nand->selected = chip;
  401. }
  402. static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  403. {
  404. struct nand_chip *nand = mtd_to_nand(mtd);
  405. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  406. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  407. int ret;
  408. int cnt;
  409. int offs = 0;
  410. u32 tmp;
  411. while (len > offs) {
  412. cnt = min(len - offs, NFC_SRAM_SIZE);
  413. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  414. if (ret)
  415. break;
  416. writel(cnt, nfc->regs + NFC_REG_CNT);
  417. tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
  418. writel(tmp, nfc->regs + NFC_REG_CMD);
  419. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  420. if (ret)
  421. break;
  422. if (buf)
  423. memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
  424. cnt);
  425. offs += cnt;
  426. }
  427. }
  428. static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  429. int len)
  430. {
  431. struct nand_chip *nand = mtd_to_nand(mtd);
  432. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  433. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  434. int ret;
  435. int cnt;
  436. int offs = 0;
  437. u32 tmp;
  438. while (len > offs) {
  439. cnt = min(len - offs, NFC_SRAM_SIZE);
  440. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  441. if (ret)
  442. break;
  443. writel(cnt, nfc->regs + NFC_REG_CNT);
  444. memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
  445. tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
  446. NFC_ACCESS_DIR;
  447. writel(tmp, nfc->regs + NFC_REG_CMD);
  448. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  449. if (ret)
  450. break;
  451. offs += cnt;
  452. }
  453. }
  454. static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
  455. {
  456. uint8_t ret;
  457. sunxi_nfc_read_buf(mtd, &ret, 1);
  458. return ret;
  459. }
  460. static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
  461. unsigned int ctrl)
  462. {
  463. struct nand_chip *nand = mtd_to_nand(mtd);
  464. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  465. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  466. int ret;
  467. u32 tmp;
  468. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  469. if (ret)
  470. return;
  471. if (ctrl & NAND_CTRL_CHANGE) {
  472. tmp = readl(nfc->regs + NFC_REG_CTL);
  473. if (ctrl & NAND_NCE)
  474. tmp |= NFC_CE_CTL;
  475. else
  476. tmp &= ~NFC_CE_CTL;
  477. writel(tmp, nfc->regs + NFC_REG_CTL);
  478. }
  479. if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
  480. !(ctrl & (NAND_CLE | NAND_ALE))) {
  481. u32 cmd = 0;
  482. if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
  483. return;
  484. if (sunxi_nand->cmd_cycles--)
  485. cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
  486. if (sunxi_nand->cmd_cycles--) {
  487. cmd |= NFC_SEND_CMD2;
  488. writel(sunxi_nand->cmd[1],
  489. nfc->regs + NFC_REG_RCMD_SET);
  490. }
  491. sunxi_nand->cmd_cycles = 0;
  492. if (sunxi_nand->addr_cycles) {
  493. cmd |= NFC_SEND_ADR |
  494. NFC_ADR_NUM(sunxi_nand->addr_cycles);
  495. writel(sunxi_nand->addr[0],
  496. nfc->regs + NFC_REG_ADDR_LOW);
  497. }
  498. if (sunxi_nand->addr_cycles > 4)
  499. writel(sunxi_nand->addr[1],
  500. nfc->regs + NFC_REG_ADDR_HIGH);
  501. writel(cmd, nfc->regs + NFC_REG_CMD);
  502. sunxi_nand->addr[0] = 0;
  503. sunxi_nand->addr[1] = 0;
  504. sunxi_nand->addr_cycles = 0;
  505. sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  506. }
  507. if (ctrl & NAND_CLE) {
  508. sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
  509. } else if (ctrl & NAND_ALE) {
  510. sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
  511. dat << ((sunxi_nand->addr_cycles % 4) * 8);
  512. sunxi_nand->addr_cycles++;
  513. }
  514. }
  515. /* These seed values have been extracted from Allwinner's BSP */
  516. static const u16 sunxi_nfc_randomizer_page_seeds[] = {
  517. 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
  518. 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
  519. 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
  520. 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
  521. 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
  522. 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
  523. 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
  524. 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
  525. 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
  526. 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
  527. 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
  528. 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
  529. 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
  530. 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
  531. 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
  532. 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
  533. };
  534. /*
  535. * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
  536. * have been generated using
  537. * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
  538. * the randomizer engine does internally before de/scrambling OOB data.
  539. *
  540. * Those tables are statically defined to avoid calculating randomizer state
  541. * at runtime.
  542. */
  543. static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
  544. 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
  545. 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
  546. 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
  547. 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
  548. 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
  549. 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
  550. 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
  551. 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
  552. 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
  553. 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
  554. 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
  555. 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
  556. 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
  557. 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
  558. 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
  559. 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
  560. };
  561. static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
  562. 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
  563. 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
  564. 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
  565. 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
  566. 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
  567. 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
  568. 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
  569. 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
  570. 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
  571. 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
  572. 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
  573. 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
  574. 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
  575. 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
  576. 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
  577. 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
  578. };
  579. static u16 sunxi_nfc_randomizer_step(u16 state, int count)
  580. {
  581. state &= 0x7fff;
  582. /*
  583. * This loop is just a simple implementation of a Fibonacci LFSR using
  584. * the x16 + x15 + 1 polynomial.
  585. */
  586. while (count--)
  587. state = ((state >> 1) |
  588. (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
  589. return state;
  590. }
  591. static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
  592. {
  593. const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
  594. int mod = mtd->erasesize / mtd->writesize;
  595. if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
  596. mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
  597. if (ecc) {
  598. if (mtd->ecc_step_size == 512)
  599. seeds = sunxi_nfc_randomizer_ecc512_seeds;
  600. else
  601. seeds = sunxi_nfc_randomizer_ecc1024_seeds;
  602. }
  603. return seeds[page % mod];
  604. }
  605. static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
  606. int page, bool ecc)
  607. {
  608. struct nand_chip *nand = mtd_to_nand(mtd);
  609. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  610. u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  611. u16 state;
  612. if (!(nand->options & NAND_NEED_SCRAMBLING))
  613. return;
  614. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  615. state = sunxi_nfc_randomizer_state(mtd, page, ecc);
  616. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
  617. writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
  618. }
  619. static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
  620. {
  621. struct nand_chip *nand = mtd_to_nand(mtd);
  622. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  623. if (!(nand->options & NAND_NEED_SCRAMBLING))
  624. return;
  625. writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
  626. nfc->regs + NFC_REG_ECC_CTL);
  627. }
  628. static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
  629. {
  630. struct nand_chip *nand = mtd_to_nand(mtd);
  631. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  632. if (!(nand->options & NAND_NEED_SCRAMBLING))
  633. return;
  634. writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
  635. nfc->regs + NFC_REG_ECC_CTL);
  636. }
  637. static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
  638. {
  639. u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
  640. bbm[0] ^= state;
  641. bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
  642. }
  643. static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
  644. const uint8_t *buf, int len,
  645. bool ecc, int page)
  646. {
  647. sunxi_nfc_randomizer_config(mtd, page, ecc);
  648. sunxi_nfc_randomizer_enable(mtd);
  649. sunxi_nfc_write_buf(mtd, buf, len);
  650. sunxi_nfc_randomizer_disable(mtd);
  651. }
  652. static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
  653. int len, bool ecc, int page)
  654. {
  655. sunxi_nfc_randomizer_config(mtd, page, ecc);
  656. sunxi_nfc_randomizer_enable(mtd);
  657. sunxi_nfc_read_buf(mtd, buf, len);
  658. sunxi_nfc_randomizer_disable(mtd);
  659. }
  660. static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
  661. {
  662. struct nand_chip *nand = mtd_to_nand(mtd);
  663. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  664. struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
  665. u32 ecc_ctl;
  666. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  667. ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
  668. NFC_ECC_BLOCK_SIZE_MSK);
  669. ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
  670. if (nand->ecc.size == 512)
  671. ecc_ctl |= NFC_ECC_BLOCK_512;
  672. writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
  673. }
  674. static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
  675. {
  676. struct nand_chip *nand = mtd_to_nand(mtd);
  677. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  678. writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
  679. nfc->regs + NFC_REG_ECC_CTL);
  680. }
  681. static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
  682. {
  683. buf[0] = user_data;
  684. buf[1] = user_data >> 8;
  685. buf[2] = user_data >> 16;
  686. buf[3] = user_data >> 24;
  687. }
  688. static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
  689. u8 *data, int data_off,
  690. u8 *oob, int oob_off,
  691. int *cur_off,
  692. unsigned int *max_bitflips,
  693. bool bbm, int page)
  694. {
  695. struct nand_chip *nand = mtd_to_nand(mtd);
  696. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  697. struct nand_ecc_ctrl *ecc = &nand->ecc;
  698. int raw_mode = 0;
  699. u32 status;
  700. int ret;
  701. if (*cur_off != data_off)
  702. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
  703. sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
  704. if (data_off + ecc->size != oob_off)
  705. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  706. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  707. if (ret)
  708. return ret;
  709. sunxi_nfc_randomizer_enable(mtd);
  710. writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
  711. nfc->regs + NFC_REG_CMD);
  712. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  713. sunxi_nfc_randomizer_disable(mtd);
  714. if (ret)
  715. return ret;
  716. *cur_off = oob_off + ecc->bytes + 4;
  717. status = readl(nfc->regs + NFC_REG_ECC_ST);
  718. if (status & NFC_ECC_PAT_FOUND(0)) {
  719. u8 pattern = 0xff;
  720. if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
  721. pattern = 0x0;
  722. memset(data, pattern, ecc->size);
  723. memset(oob, pattern, ecc->bytes + 4);
  724. return 1;
  725. }
  726. ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
  727. memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
  728. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  729. sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
  730. if (status & NFC_ECC_ERR(0)) {
  731. /*
  732. * Re-read the data with the randomizer disabled to identify
  733. * bitflips in erased pages.
  734. */
  735. if (nand->options & NAND_NEED_SCRAMBLING) {
  736. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
  737. nand->read_buf(mtd, data, ecc->size);
  738. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  739. nand->read_buf(mtd, oob, ecc->bytes + 4);
  740. }
  741. ret = nand_check_erased_ecc_chunk(data, ecc->size,
  742. oob, ecc->bytes + 4,
  743. NULL, 0, ecc->strength);
  744. if (ret >= 0)
  745. raw_mode = 1;
  746. } else {
  747. /*
  748. * The engine protects 4 bytes of OOB data per chunk.
  749. * Retrieve the corrected OOB bytes.
  750. */
  751. sunxi_nfc_user_data_to_buf(readl(nfc->regs +
  752. NFC_REG_USER_DATA(0)),
  753. oob);
  754. /* De-randomize the Bad Block Marker. */
  755. if (bbm && nand->options & NAND_NEED_SCRAMBLING)
  756. sunxi_nfc_randomize_bbm(mtd, page, oob);
  757. }
  758. if (ret < 0) {
  759. mtd->ecc_stats.failed++;
  760. } else {
  761. mtd->ecc_stats.corrected += ret;
  762. *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
  763. }
  764. return raw_mode;
  765. }
  766. static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
  767. u8 *oob, int *cur_off,
  768. bool randomize, int page)
  769. {
  770. struct nand_chip *nand = mtd_to_nand(mtd);
  771. struct nand_ecc_ctrl *ecc = &nand->ecc;
  772. int offset = ((ecc->bytes + 4) * ecc->steps);
  773. int len = mtd->oobsize - offset;
  774. if (len <= 0)
  775. return;
  776. if (*cur_off != offset)
  777. nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
  778. offset + mtd->writesize, -1);
  779. if (!randomize)
  780. sunxi_nfc_read_buf(mtd, oob + offset, len);
  781. else
  782. sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
  783. false, page);
  784. *cur_off = mtd->oobsize + mtd->writesize;
  785. }
  786. static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
  787. {
  788. return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
  789. }
  790. static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
  791. const u8 *data, int data_off,
  792. const u8 *oob, int oob_off,
  793. int *cur_off, bool bbm,
  794. int page)
  795. {
  796. struct nand_chip *nand = mtd_to_nand(mtd);
  797. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  798. struct nand_ecc_ctrl *ecc = &nand->ecc;
  799. int ret;
  800. if (data_off != *cur_off)
  801. nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
  802. sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
  803. /* Fill OOB data in */
  804. if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
  805. u8 user_data[4];
  806. memcpy(user_data, oob, 4);
  807. sunxi_nfc_randomize_bbm(mtd, page, user_data);
  808. writel(sunxi_nfc_buf_to_user_data(user_data),
  809. nfc->regs + NFC_REG_USER_DATA(0));
  810. } else {
  811. writel(sunxi_nfc_buf_to_user_data(oob),
  812. nfc->regs + NFC_REG_USER_DATA(0));
  813. }
  814. if (data_off + ecc->size != oob_off)
  815. nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
  816. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  817. if (ret)
  818. return ret;
  819. sunxi_nfc_randomizer_enable(mtd);
  820. writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
  821. NFC_ACCESS_DIR | NFC_ECC_OP,
  822. nfc->regs + NFC_REG_CMD);
  823. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  824. sunxi_nfc_randomizer_disable(mtd);
  825. if (ret)
  826. return ret;
  827. *cur_off = oob_off + ecc->bytes + 4;
  828. return 0;
  829. }
  830. static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
  831. u8 *oob, int *cur_off,
  832. int page)
  833. {
  834. struct nand_chip *nand = mtd_to_nand(mtd);
  835. struct nand_ecc_ctrl *ecc = &nand->ecc;
  836. int offset = ((ecc->bytes + 4) * ecc->steps);
  837. int len = mtd->oobsize - offset;
  838. if (len <= 0)
  839. return;
  840. if (*cur_off != offset)
  841. nand->cmdfunc(mtd, NAND_CMD_RNDIN,
  842. offset + mtd->writesize, -1);
  843. sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
  844. *cur_off = mtd->oobsize + mtd->writesize;
  845. }
  846. static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
  847. struct nand_chip *chip, uint8_t *buf,
  848. int oob_required, int page)
  849. {
  850. struct nand_ecc_ctrl *ecc = &chip->ecc;
  851. unsigned int max_bitflips = 0;
  852. int ret, i, cur_off = 0;
  853. bool raw_mode = false;
  854. sunxi_nfc_hw_ecc_enable(mtd);
  855. for (i = 0; i < ecc->steps; i++) {
  856. int data_off = i * ecc->size;
  857. int oob_off = i * (ecc->bytes + 4);
  858. u8 *data = buf + data_off;
  859. u8 *oob = chip->oob_poi + oob_off;
  860. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
  861. oob_off + mtd->writesize,
  862. &cur_off, &max_bitflips,
  863. !i, page);
  864. if (ret < 0)
  865. return ret;
  866. else if (ret)
  867. raw_mode = true;
  868. }
  869. if (oob_required)
  870. sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
  871. !raw_mode, page);
  872. sunxi_nfc_hw_ecc_disable(mtd);
  873. return max_bitflips;
  874. }
  875. static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
  876. struct nand_chip *chip,
  877. uint32_t data_offs, uint32_t readlen,
  878. uint8_t *bufpoi, int page)
  879. {
  880. struct nand_ecc_ctrl *ecc = &chip->ecc;
  881. int ret, i, cur_off = 0;
  882. unsigned int max_bitflips = 0;
  883. sunxi_nfc_hw_ecc_enable(mtd);
  884. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  885. for (i = data_offs / ecc->size;
  886. i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
  887. int data_off = i * ecc->size;
  888. int oob_off = i * (ecc->bytes + 4);
  889. u8 *data = bufpoi + data_off;
  890. u8 *oob = chip->oob_poi + oob_off;
  891. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
  892. oob, oob_off + mtd->writesize,
  893. &cur_off, &max_bitflips, !i, page);
  894. if (ret < 0)
  895. return ret;
  896. }
  897. sunxi_nfc_hw_ecc_disable(mtd);
  898. return max_bitflips;
  899. }
  900. static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
  901. struct nand_chip *chip,
  902. const uint8_t *buf, int oob_required,
  903. int page)
  904. {
  905. struct nand_ecc_ctrl *ecc = &chip->ecc;
  906. int ret, i, cur_off = 0;
  907. sunxi_nfc_hw_ecc_enable(mtd);
  908. for (i = 0; i < ecc->steps; i++) {
  909. int data_off = i * ecc->size;
  910. int oob_off = i * (ecc->bytes + 4);
  911. const u8 *data = buf + data_off;
  912. const u8 *oob = chip->oob_poi + oob_off;
  913. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
  914. oob_off + mtd->writesize,
  915. &cur_off, !i, page);
  916. if (ret)
  917. return ret;
  918. }
  919. if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
  920. sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
  921. &cur_off, page);
  922. sunxi_nfc_hw_ecc_disable(mtd);
  923. return 0;
  924. }
  925. static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
  926. struct nand_chip *chip,
  927. u32 data_offs, u32 data_len,
  928. const u8 *buf, int oob_required,
  929. int page)
  930. {
  931. struct nand_ecc_ctrl *ecc = &chip->ecc;
  932. int ret, i, cur_off = 0;
  933. sunxi_nfc_hw_ecc_enable(mtd);
  934. for (i = data_offs / ecc->size;
  935. i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
  936. int data_off = i * ecc->size;
  937. int oob_off = i * (ecc->bytes + 4);
  938. const u8 *data = buf + data_off;
  939. const u8 *oob = chip->oob_poi + oob_off;
  940. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
  941. oob_off + mtd->writesize,
  942. &cur_off, !i, page);
  943. if (ret)
  944. return ret;
  945. }
  946. sunxi_nfc_hw_ecc_disable(mtd);
  947. return 0;
  948. }
  949. static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
  950. struct nand_chip *chip,
  951. uint8_t *buf, int oob_required,
  952. int page)
  953. {
  954. struct nand_ecc_ctrl *ecc = &chip->ecc;
  955. unsigned int max_bitflips = 0;
  956. int ret, i, cur_off = 0;
  957. bool raw_mode = false;
  958. sunxi_nfc_hw_ecc_enable(mtd);
  959. for (i = 0; i < ecc->steps; i++) {
  960. int data_off = i * (ecc->size + ecc->bytes + 4);
  961. int oob_off = data_off + ecc->size;
  962. u8 *data = buf + (i * ecc->size);
  963. u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
  964. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
  965. oob_off, &cur_off,
  966. &max_bitflips, !i, page);
  967. if (ret < 0)
  968. return ret;
  969. else if (ret)
  970. raw_mode = true;
  971. }
  972. if (oob_required)
  973. sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
  974. !raw_mode, page);
  975. sunxi_nfc_hw_ecc_disable(mtd);
  976. return max_bitflips;
  977. }
  978. static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
  979. struct nand_chip *chip,
  980. const uint8_t *buf,
  981. int oob_required, int page)
  982. {
  983. struct nand_ecc_ctrl *ecc = &chip->ecc;
  984. int ret, i, cur_off = 0;
  985. sunxi_nfc_hw_ecc_enable(mtd);
  986. for (i = 0; i < ecc->steps; i++) {
  987. int data_off = i * (ecc->size + ecc->bytes + 4);
  988. int oob_off = data_off + ecc->size;
  989. const u8 *data = buf + (i * ecc->size);
  990. const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
  991. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
  992. oob, oob_off, &cur_off,
  993. false, page);
  994. if (ret)
  995. return ret;
  996. }
  997. if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
  998. sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
  999. &cur_off, page);
  1000. sunxi_nfc_hw_ecc_disable(mtd);
  1001. return 0;
  1002. }
  1003. static const s32 tWB_lut[] = {6, 12, 16, 20};
  1004. static const s32 tRHW_lut[] = {4, 8, 12, 20};
  1005. static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
  1006. u32 clk_period)
  1007. {
  1008. u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
  1009. int i;
  1010. for (i = 0; i < lut_size; i++) {
  1011. if (clk_cycles <= lut[i])
  1012. return i;
  1013. }
  1014. /* Doesn't fit */
  1015. return -EINVAL;
  1016. }
  1017. #define sunxi_nand_lookup_timing(l, p, c) \
  1018. _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
  1019. static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
  1020. const struct nand_sdr_timings *timings)
  1021. {
  1022. u32 min_clk_period = 0;
  1023. s32 tWB, tADL, tWHR, tRHW, tCAD;
  1024. /* T1 <=> tCLS */
  1025. if (timings->tCLS_min > min_clk_period)
  1026. min_clk_period = timings->tCLS_min;
  1027. /* T2 <=> tCLH */
  1028. if (timings->tCLH_min > min_clk_period)
  1029. min_clk_period = timings->tCLH_min;
  1030. /* T3 <=> tCS */
  1031. if (timings->tCS_min > min_clk_period)
  1032. min_clk_period = timings->tCS_min;
  1033. /* T4 <=> tCH */
  1034. if (timings->tCH_min > min_clk_period)
  1035. min_clk_period = timings->tCH_min;
  1036. /* T5 <=> tWP */
  1037. if (timings->tWP_min > min_clk_period)
  1038. min_clk_period = timings->tWP_min;
  1039. /* T6 <=> tWH */
  1040. if (timings->tWH_min > min_clk_period)
  1041. min_clk_period = timings->tWH_min;
  1042. /* T7 <=> tALS */
  1043. if (timings->tALS_min > min_clk_period)
  1044. min_clk_period = timings->tALS_min;
  1045. /* T8 <=> tDS */
  1046. if (timings->tDS_min > min_clk_period)
  1047. min_clk_period = timings->tDS_min;
  1048. /* T9 <=> tDH */
  1049. if (timings->tDH_min > min_clk_period)
  1050. min_clk_period = timings->tDH_min;
  1051. /* T10 <=> tRR */
  1052. if (timings->tRR_min > (min_clk_period * 3))
  1053. min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
  1054. /* T11 <=> tALH */
  1055. if (timings->tALH_min > min_clk_period)
  1056. min_clk_period = timings->tALH_min;
  1057. /* T12 <=> tRP */
  1058. if (timings->tRP_min > min_clk_period)
  1059. min_clk_period = timings->tRP_min;
  1060. /* T13 <=> tREH */
  1061. if (timings->tREH_min > min_clk_period)
  1062. min_clk_period = timings->tREH_min;
  1063. /* T14 <=> tRC */
  1064. if (timings->tRC_min > (min_clk_period * 2))
  1065. min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
  1066. /* T15 <=> tWC */
  1067. if (timings->tWC_min > (min_clk_period * 2))
  1068. min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
  1069. /* T16 - T19 + tCAD */
  1070. tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
  1071. min_clk_period);
  1072. if (tWB < 0) {
  1073. dev_err(nfc->dev, "unsupported tWB\n");
  1074. return tWB;
  1075. }
  1076. tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
  1077. if (tADL > 3) {
  1078. dev_err(nfc->dev, "unsupported tADL\n");
  1079. return -EINVAL;
  1080. }
  1081. tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
  1082. if (tWHR > 3) {
  1083. dev_err(nfc->dev, "unsupported tWHR\n");
  1084. return -EINVAL;
  1085. }
  1086. tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
  1087. min_clk_period);
  1088. if (tRHW < 0) {
  1089. dev_err(nfc->dev, "unsupported tRHW\n");
  1090. return tRHW;
  1091. }
  1092. /*
  1093. * TODO: according to ONFI specs this value only applies for DDR NAND,
  1094. * but Allwinner seems to set this to 0x7. Mimic them for now.
  1095. */
  1096. tCAD = 0x7;
  1097. /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
  1098. chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
  1099. /*
  1100. * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
  1101. * output cycle timings shall be used if the host drives tRC less than
  1102. * 30 ns.
  1103. */
  1104. chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
  1105. /* Convert min_clk_period from picoseconds to nanoseconds */
  1106. min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
  1107. /*
  1108. * Convert min_clk_period into a clk frequency, then get the
  1109. * appropriate rate for the NAND controller IP given this formula
  1110. * (specified in the datasheet):
  1111. * nand clk_rate = min_clk_rate
  1112. */
  1113. chip->clk_rate = 1000000000L / min_clk_period;
  1114. return 0;
  1115. }
  1116. static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
  1117. {
  1118. struct mtd_info *mtd = nand_to_mtd(&chip->nand);
  1119. const struct nand_sdr_timings *timings;
  1120. int ret;
  1121. int mode;
  1122. mode = onfi_get_async_timing_mode(&chip->nand);
  1123. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  1124. mode = chip->nand.onfi_timing_mode_default;
  1125. } else {
  1126. uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
  1127. int i;
  1128. mode = fls(mode) - 1;
  1129. if (mode < 0)
  1130. mode = 0;
  1131. feature[0] = mode;
  1132. for (i = 0; i < chip->nsels; i++) {
  1133. chip->nand.select_chip(mtd, i);
  1134. ret = chip->nand.onfi_set_features(mtd,
  1135. &chip->nand,
  1136. ONFI_FEATURE_ADDR_TIMING_MODE,
  1137. feature);
  1138. chip->nand.select_chip(mtd, -1);
  1139. if (ret && ret != -ENOTSUPP)
  1140. return ret;
  1141. }
  1142. }
  1143. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  1144. if (IS_ERR(timings))
  1145. return PTR_ERR(timings);
  1146. return sunxi_nand_chip_set_timings(chip, timings);
  1147. }
  1148. static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
  1149. struct nand_ecc_ctrl *ecc)
  1150. {
  1151. static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
  1152. struct sunxi_nand_hw_ecc *data;
  1153. struct nand_ecclayout *layout;
  1154. int nsectors;
  1155. int ret;
  1156. int i;
  1157. data = kzalloc(sizeof(*data), GFP_KERNEL);
  1158. if (!data)
  1159. return -ENOMEM;
  1160. if (ecc->size != 512 && ecc->size != 1024)
  1161. return -EINVAL;
  1162. /* Prefer 1k ECC chunk over 512 ones */
  1163. if (ecc->size == 512 && mtd->writesize > 512) {
  1164. ecc->size = 1024;
  1165. ecc->strength *= 2;
  1166. }
  1167. /* Add ECC info retrieval from DT */
  1168. for (i = 0; i < ARRAY_SIZE(strengths); i++) {
  1169. if (ecc->strength <= strengths[i]) {
  1170. /*
  1171. * Update ecc->strength value with the actual strength
  1172. * that will be used by the ECC engine.
  1173. */
  1174. ecc->strength = strengths[i];
  1175. break;
  1176. }
  1177. }
  1178. if (i >= ARRAY_SIZE(strengths)) {
  1179. dev_err(nfc->dev, "unsupported strength\n");
  1180. ret = -ENOTSUPP;
  1181. goto err;
  1182. }
  1183. data->mode = i;
  1184. /* HW ECC always request ECC bytes for 1024 bytes blocks */
  1185. ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
  1186. /* HW ECC always work with even numbers of ECC bytes */
  1187. ecc->bytes = ALIGN(ecc->bytes, 2);
  1188. layout = &data->layout;
  1189. nsectors = mtd->writesize / ecc->size;
  1190. if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
  1191. ret = -EINVAL;
  1192. goto err;
  1193. }
  1194. layout->eccbytes = (ecc->bytes * nsectors);
  1195. ecc->layout = layout;
  1196. ecc->priv = data;
  1197. return 0;
  1198. err:
  1199. kfree(data);
  1200. return ret;
  1201. }
  1202. #ifndef __UBOOT__
  1203. static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
  1204. {
  1205. kfree(ecc->priv);
  1206. }
  1207. #endif /* __UBOOT__ */
  1208. static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
  1209. struct nand_ecc_ctrl *ecc)
  1210. {
  1211. struct nand_ecclayout *layout;
  1212. int nsectors;
  1213. int i, j;
  1214. int ret;
  1215. ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
  1216. if (ret)
  1217. return ret;
  1218. ecc->read_page = sunxi_nfc_hw_ecc_read_page;
  1219. ecc->write_page = sunxi_nfc_hw_ecc_write_page;
  1220. ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
  1221. ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
  1222. layout = ecc->layout;
  1223. nsectors = mtd->writesize / ecc->size;
  1224. for (i = 0; i < nsectors; i++) {
  1225. if (i) {
  1226. layout->oobfree[i].offset =
  1227. layout->oobfree[i - 1].offset +
  1228. layout->oobfree[i - 1].length +
  1229. ecc->bytes;
  1230. layout->oobfree[i].length = 4;
  1231. } else {
  1232. /*
  1233. * The first 2 bytes are used for BB markers, hence we
  1234. * only have 2 bytes available in the first user data
  1235. * section.
  1236. */
  1237. layout->oobfree[i].length = 2;
  1238. layout->oobfree[i].offset = 2;
  1239. }
  1240. for (j = 0; j < ecc->bytes; j++)
  1241. layout->eccpos[(ecc->bytes * i) + j] =
  1242. layout->oobfree[i].offset +
  1243. layout->oobfree[i].length + j;
  1244. }
  1245. if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
  1246. layout->oobfree[nsectors].offset =
  1247. layout->oobfree[nsectors - 1].offset +
  1248. layout->oobfree[nsectors - 1].length +
  1249. ecc->bytes;
  1250. layout->oobfree[nsectors].length = mtd->oobsize -
  1251. ((ecc->bytes + 4) * nsectors);
  1252. }
  1253. return 0;
  1254. }
  1255. static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
  1256. struct nand_ecc_ctrl *ecc)
  1257. {
  1258. struct nand_ecclayout *layout;
  1259. int nsectors;
  1260. int i;
  1261. int ret;
  1262. ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
  1263. if (ret)
  1264. return ret;
  1265. ecc->prepad = 4;
  1266. ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
  1267. ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
  1268. layout = ecc->layout;
  1269. nsectors = mtd->writesize / ecc->size;
  1270. for (i = 0; i < (ecc->bytes * nsectors); i++)
  1271. layout->eccpos[i] = i;
  1272. layout->oobfree[0].length = mtd->oobsize - i;
  1273. layout->oobfree[0].offset = i;
  1274. return 0;
  1275. }
  1276. #ifndef __UBOOT__
  1277. static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
  1278. {
  1279. switch (ecc->mode) {
  1280. case NAND_ECC_HW:
  1281. case NAND_ECC_HW_SYNDROME:
  1282. sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
  1283. break;
  1284. case NAND_ECC_NONE:
  1285. kfree(ecc->layout);
  1286. default:
  1287. break;
  1288. }
  1289. }
  1290. #endif /* __UBOOT__ */
  1291. static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
  1292. {
  1293. struct nand_chip *nand = mtd_to_nand(mtd);
  1294. int ret;
  1295. if (!ecc->size) {
  1296. ecc->size = nand->ecc_step_ds;
  1297. ecc->strength = nand->ecc_strength_ds;
  1298. }
  1299. if (!ecc->size || !ecc->strength)
  1300. return -EINVAL;
  1301. switch (ecc->mode) {
  1302. case NAND_ECC_SOFT_BCH:
  1303. break;
  1304. case NAND_ECC_HW:
  1305. ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
  1306. if (ret)
  1307. return ret;
  1308. break;
  1309. case NAND_ECC_HW_SYNDROME:
  1310. ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
  1311. if (ret)
  1312. return ret;
  1313. break;
  1314. case NAND_ECC_NONE:
  1315. ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
  1316. if (!ecc->layout)
  1317. return -ENOMEM;
  1318. ecc->layout->oobfree[0].length = mtd->oobsize;
  1319. case NAND_ECC_SOFT:
  1320. break;
  1321. default:
  1322. return -EINVAL;
  1323. }
  1324. return 0;
  1325. }
  1326. static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
  1327. {
  1328. const struct nand_sdr_timings *timings;
  1329. const void *blob = gd->fdt_blob;
  1330. struct sunxi_nand_chip *chip;
  1331. struct mtd_info *mtd;
  1332. struct nand_chip *nand;
  1333. int nsels;
  1334. int ret;
  1335. int i;
  1336. u32 cs[8], rb[8];
  1337. if (!fdt_getprop(blob, node, "reg", &nsels))
  1338. return -EINVAL;
  1339. nsels /= sizeof(u32);
  1340. if (!nsels || nsels > 8) {
  1341. dev_err(dev, "invalid reg property size\n");
  1342. return -EINVAL;
  1343. }
  1344. chip = kzalloc(sizeof(*chip) +
  1345. (nsels * sizeof(struct sunxi_nand_chip_sel)),
  1346. GFP_KERNEL);
  1347. if (!chip) {
  1348. dev_err(dev, "could not allocate chip\n");
  1349. return -ENOMEM;
  1350. }
  1351. chip->nsels = nsels;
  1352. chip->selected = -1;
  1353. for (i = 0; i < nsels; i++) {
  1354. cs[i] = -1;
  1355. rb[i] = -1;
  1356. }
  1357. ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
  1358. if (ret) {
  1359. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  1360. return ret;
  1361. }
  1362. ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
  1363. nsels);
  1364. if (ret) {
  1365. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  1366. return ret;
  1367. }
  1368. for (i = 0; i < nsels; i++) {
  1369. int tmp = cs[i];
  1370. if (tmp > NFC_MAX_CS) {
  1371. dev_err(dev,
  1372. "invalid reg value: %u (max CS = 7)\n",
  1373. tmp);
  1374. return -EINVAL;
  1375. }
  1376. if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
  1377. dev_err(dev, "CS %d already assigned\n", tmp);
  1378. return -EINVAL;
  1379. }
  1380. chip->sels[i].cs = tmp;
  1381. tmp = rb[i];
  1382. if (tmp >= 0 && tmp < 2) {
  1383. chip->sels[i].rb.type = RB_NATIVE;
  1384. chip->sels[i].rb.info.nativeid = tmp;
  1385. } else {
  1386. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  1387. "rb-gpios", i,
  1388. &chip->sels[i].rb.info.gpio,
  1389. GPIOD_IS_IN);
  1390. if (ret)
  1391. chip->sels[i].rb.type = RB_GPIO;
  1392. else
  1393. chip->sels[i].rb.type = RB_NONE;
  1394. }
  1395. }
  1396. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1397. if (IS_ERR(timings)) {
  1398. ret = PTR_ERR(timings);
  1399. dev_err(dev,
  1400. "could not retrieve timings for ONFI mode 0: %d\n",
  1401. ret);
  1402. return ret;
  1403. }
  1404. ret = sunxi_nand_chip_set_timings(chip, timings);
  1405. if (ret) {
  1406. dev_err(dev, "could not configure chip timings: %d\n", ret);
  1407. return ret;
  1408. }
  1409. nand = &chip->nand;
  1410. /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
  1411. nand->chip_delay = 200;
  1412. nand->controller = &nfc->controller;
  1413. /*
  1414. * Set the ECC mode to the default value in case nothing is specified
  1415. * in the DT.
  1416. */
  1417. nand->ecc.mode = NAND_ECC_HW;
  1418. nand->flash_node = node;
  1419. nand->select_chip = sunxi_nfc_select_chip;
  1420. nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
  1421. nand->read_buf = sunxi_nfc_read_buf;
  1422. nand->write_buf = sunxi_nfc_write_buf;
  1423. nand->read_byte = sunxi_nfc_read_byte;
  1424. mtd = nand_to_mtd(nand);
  1425. ret = nand_scan_ident(mtd, nsels, NULL);
  1426. if (ret)
  1427. return ret;
  1428. if (nand->bbt_options & NAND_BBT_USE_FLASH)
  1429. nand->bbt_options |= NAND_BBT_NO_OOB;
  1430. if (nand->options & NAND_NEED_SCRAMBLING)
  1431. nand->options |= NAND_NO_SUBPAGE_WRITE;
  1432. nand->options |= NAND_SUBPAGE_READ;
  1433. ret = sunxi_nand_chip_init_timings(chip);
  1434. if (ret) {
  1435. dev_err(dev, "could not configure chip timings: %d\n", ret);
  1436. return ret;
  1437. }
  1438. ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
  1439. if (ret) {
  1440. dev_err(dev, "ECC init failed: %d\n", ret);
  1441. return ret;
  1442. }
  1443. ret = nand_scan_tail(mtd);
  1444. if (ret) {
  1445. dev_err(dev, "nand_scan_tail failed: %d\n", ret);
  1446. return ret;
  1447. }
  1448. ret = nand_register(devnum, mtd);
  1449. if (ret) {
  1450. dev_err(dev, "failed to register mtd device: %d\n", ret);
  1451. return ret;
  1452. }
  1453. list_add_tail(&chip->node, &nfc->chips);
  1454. return 0;
  1455. }
  1456. static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
  1457. {
  1458. const void *blob = gd->fdt_blob;
  1459. int nand_node;
  1460. int ret, i = 0;
  1461. for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
  1462. nand_node = fdt_next_subnode(blob, nand_node))
  1463. i++;
  1464. if (i > 8) {
  1465. dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
  1466. return -EINVAL;
  1467. }
  1468. i = 0;
  1469. for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
  1470. nand_node = fdt_next_subnode(blob, nand_node)) {
  1471. ret = sunxi_nand_chip_init(nand_node, nfc, i++);
  1472. if (ret)
  1473. return ret;
  1474. }
  1475. return 0;
  1476. }
  1477. #ifndef __UBOOT__
  1478. static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
  1479. {
  1480. struct sunxi_nand_chip *chip;
  1481. while (!list_empty(&nfc->chips)) {
  1482. chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
  1483. node);
  1484. nand_release(&chip->mtd);
  1485. sunxi_nand_ecc_cleanup(&chip->nand.ecc);
  1486. list_del(&chip->node);
  1487. kfree(chip);
  1488. }
  1489. }
  1490. #endif /* __UBOOT__ */
  1491. void sunxi_nand_init(void)
  1492. {
  1493. const void *blob = gd->fdt_blob;
  1494. struct sunxi_nfc *nfc;
  1495. fdt_addr_t regs;
  1496. int node;
  1497. int ret;
  1498. nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
  1499. if (!nfc)
  1500. return;
  1501. spin_lock_init(&nfc->controller.lock);
  1502. init_waitqueue_head(&nfc->controller.wq);
  1503. INIT_LIST_HEAD(&nfc->chips);
  1504. node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
  1505. if (node < 0) {
  1506. pr_err("unable to find nfc node in device tree\n");
  1507. goto err;
  1508. }
  1509. if (!fdtdec_get_is_enabled(blob, node)) {
  1510. pr_err("nfc disabled in device tree\n");
  1511. goto err;
  1512. }
  1513. regs = fdtdec_get_addr(blob, node, "reg");
  1514. if (regs == FDT_ADDR_T_NONE) {
  1515. pr_err("unable to find nfc address in device tree\n");
  1516. goto err;
  1517. }
  1518. nfc->regs = (void *)regs;
  1519. ret = sunxi_nfc_rst(nfc);
  1520. if (ret)
  1521. goto err;
  1522. ret = sunxi_nand_chips_init(node, nfc);
  1523. if (ret) {
  1524. dev_err(dev, "failed to init nand chips\n");
  1525. goto err;
  1526. }
  1527. return;
  1528. err:
  1529. kfree(nfc);
  1530. }
  1531. MODULE_LICENSE("GPL v2");
  1532. MODULE_AUTHOR("Boris BREZILLON");
  1533. MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");