pxa3xx_nand.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/mtd/nand/raw/pxa3xx_nand.c
  4. *
  5. * Copyright © 2005 Intel Corporation
  6. * Copyright © 2006 Marvell International Ltd.
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <fdtdec.h>
  11. #include <nand.h>
  12. #include <dm/devres.h>
  13. #include <linux/err.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/rawnand.h>
  19. #include <linux/types.h>
  20. #include "pxa3xx_nand.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
  23. #define CHIP_DELAY_TIMEOUT 200
  24. #define NAND_STOP_DELAY 40
  25. /*
  26. * Define a buffer size for the initial command that detects the flash device:
  27. * STATUS, READID and PARAM.
  28. * ONFI param page is 256 bytes, and there are three redundant copies
  29. * to be read. JEDEC param page is 512 bytes, and there are also three
  30. * redundant copies to be read.
  31. * Hence this buffer should be at least 512 x 3. Let's pick 2048.
  32. */
  33. #define INIT_BUFFER_SIZE 2048
  34. /* registers and bit definitions */
  35. #define NDCR (0x00) /* Control register */
  36. #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
  37. #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
  38. #define NDSR (0x14) /* Status Register */
  39. #define NDPCR (0x18) /* Page Count Register */
  40. #define NDBDR0 (0x1C) /* Bad Block Register 0 */
  41. #define NDBDR1 (0x20) /* Bad Block Register 1 */
  42. #define NDECCCTRL (0x28) /* ECC control */
  43. #define NDDB (0x40) /* Data Buffer */
  44. #define NDCB0 (0x48) /* Command Buffer0 */
  45. #define NDCB1 (0x4C) /* Command Buffer1 */
  46. #define NDCB2 (0x50) /* Command Buffer2 */
  47. #define NDCR_SPARE_EN (0x1 << 31)
  48. #define NDCR_ECC_EN (0x1 << 30)
  49. #define NDCR_DMA_EN (0x1 << 29)
  50. #define NDCR_ND_RUN (0x1 << 28)
  51. #define NDCR_DWIDTH_C (0x1 << 27)
  52. #define NDCR_DWIDTH_M (0x1 << 26)
  53. #define NDCR_PAGE_SZ (0x1 << 24)
  54. #define NDCR_NCSX (0x1 << 23)
  55. #define NDCR_ND_MODE (0x3 << 21)
  56. #define NDCR_NAND_MODE (0x0)
  57. #define NDCR_CLR_PG_CNT (0x1 << 20)
  58. #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
  59. #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
  60. #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  61. #define NDCR_RA_START (0x1 << 15)
  62. #define NDCR_PG_PER_BLK (0x1 << 14)
  63. #define NDCR_ND_ARB_EN (0x1 << 12)
  64. #define NDCR_INT_MASK (0xFFF)
  65. #define NDSR_MASK (0xfff)
  66. #define NDSR_ERR_CNT_OFF (16)
  67. #define NDSR_ERR_CNT_MASK (0x1f)
  68. #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
  69. #define NDSR_RDY (0x1 << 12)
  70. #define NDSR_FLASH_RDY (0x1 << 11)
  71. #define NDSR_CS0_PAGED (0x1 << 10)
  72. #define NDSR_CS1_PAGED (0x1 << 9)
  73. #define NDSR_CS0_CMDD (0x1 << 8)
  74. #define NDSR_CS1_CMDD (0x1 << 7)
  75. #define NDSR_CS0_BBD (0x1 << 6)
  76. #define NDSR_CS1_BBD (0x1 << 5)
  77. #define NDSR_UNCORERR (0x1 << 4)
  78. #define NDSR_CORERR (0x1 << 3)
  79. #define NDSR_WRDREQ (0x1 << 2)
  80. #define NDSR_RDDREQ (0x1 << 1)
  81. #define NDSR_WRCMDREQ (0x1)
  82. #define NDCB0_LEN_OVRD (0x1 << 28)
  83. #define NDCB0_ST_ROW_EN (0x1 << 26)
  84. #define NDCB0_AUTO_RS (0x1 << 25)
  85. #define NDCB0_CSEL (0x1 << 24)
  86. #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
  87. #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
  88. #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
  89. #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  90. #define NDCB0_NC (0x1 << 20)
  91. #define NDCB0_DBC (0x1 << 19)
  92. #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
  93. #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  94. #define NDCB0_CMD2_MASK (0xff << 8)
  95. #define NDCB0_CMD1_MASK (0xff)
  96. #define NDCB0_ADDR_CYC_SHIFT (16)
  97. #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
  98. #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
  99. #define EXT_CMD_TYPE_READ 4 /* Read */
  100. #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
  101. #define EXT_CMD_TYPE_FINAL 3 /* Final command */
  102. #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
  103. #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
  104. /*
  105. * This should be large enough to read 'ONFI' and 'JEDEC'.
  106. * Let's use 7 bytes, which is the maximum ID count supported
  107. * by the controller (see NDCR_RD_ID_CNT_MASK).
  108. */
  109. #define READ_ID_BYTES 7
  110. /* macros for registers read/write */
  111. #define nand_writel(info, off, val) \
  112. writel((val), (info)->mmio_base + (off))
  113. #define nand_readl(info, off) \
  114. readl((info)->mmio_base + (off))
  115. /* error code and state */
  116. enum {
  117. ERR_NONE = 0,
  118. ERR_DMABUSERR = -1,
  119. ERR_SENDCMD = -2,
  120. ERR_UNCORERR = -3,
  121. ERR_BBERR = -4,
  122. ERR_CORERR = -5,
  123. };
  124. enum {
  125. STATE_IDLE = 0,
  126. STATE_PREPARED,
  127. STATE_CMD_HANDLE,
  128. STATE_DMA_READING,
  129. STATE_DMA_WRITING,
  130. STATE_DMA_DONE,
  131. STATE_PIO_READING,
  132. STATE_PIO_WRITING,
  133. STATE_CMD_DONE,
  134. STATE_READY,
  135. };
  136. enum pxa3xx_nand_variant {
  137. PXA3XX_NAND_VARIANT_PXA,
  138. PXA3XX_NAND_VARIANT_ARMADA370,
  139. };
  140. struct pxa3xx_nand_host {
  141. struct nand_chip chip;
  142. void *info_data;
  143. /* page size of attached chip */
  144. int use_ecc;
  145. int cs;
  146. /* calculated from pxa3xx_nand_flash data */
  147. unsigned int col_addr_cycles;
  148. unsigned int row_addr_cycles;
  149. };
  150. struct pxa3xx_nand_info {
  151. struct nand_hw_control controller;
  152. struct pxa3xx_nand_platform_data *pdata;
  153. struct clk *clk;
  154. void __iomem *mmio_base;
  155. unsigned long mmio_phys;
  156. int cmd_complete, dev_ready;
  157. unsigned int buf_start;
  158. unsigned int buf_count;
  159. unsigned int buf_size;
  160. unsigned int data_buff_pos;
  161. unsigned int oob_buff_pos;
  162. unsigned char *data_buff;
  163. unsigned char *oob_buff;
  164. struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
  165. unsigned int state;
  166. /*
  167. * This driver supports NFCv1 (as found in PXA SoC)
  168. * and NFCv2 (as found in Armada 370/XP SoC).
  169. */
  170. enum pxa3xx_nand_variant variant;
  171. int cs;
  172. int use_ecc; /* use HW ECC ? */
  173. int force_raw; /* prevent use_ecc to be set */
  174. int ecc_bch; /* using BCH ECC? */
  175. int use_spare; /* use spare ? */
  176. int need_wait;
  177. /* Amount of real data per full chunk */
  178. unsigned int chunk_size;
  179. /* Amount of spare data per full chunk */
  180. unsigned int spare_size;
  181. /* Number of full chunks (i.e chunk_size + spare_size) */
  182. unsigned int nfullchunks;
  183. /*
  184. * Total number of chunks. If equal to nfullchunks, then there
  185. * are only full chunks. Otherwise, there is one last chunk of
  186. * size (last_chunk_size + last_spare_size)
  187. */
  188. unsigned int ntotalchunks;
  189. /* Amount of real data in the last chunk */
  190. unsigned int last_chunk_size;
  191. /* Amount of spare data in the last chunk */
  192. unsigned int last_spare_size;
  193. unsigned int ecc_size;
  194. unsigned int ecc_err_cnt;
  195. unsigned int max_bitflips;
  196. int retcode;
  197. /*
  198. * Variables only valid during command
  199. * execution. step_chunk_size and step_spare_size is the
  200. * amount of real data and spare data in the current
  201. * chunk. cur_chunk is the current chunk being
  202. * read/programmed.
  203. */
  204. unsigned int step_chunk_size;
  205. unsigned int step_spare_size;
  206. unsigned int cur_chunk;
  207. /* cached register value */
  208. uint32_t reg_ndcr;
  209. uint32_t ndtr0cs0;
  210. uint32_t ndtr1cs0;
  211. /* generated NDCBx register values */
  212. uint32_t ndcb0;
  213. uint32_t ndcb1;
  214. uint32_t ndcb2;
  215. uint32_t ndcb3;
  216. };
  217. static struct pxa3xx_nand_timing timing[] = {
  218. /*
  219. * tCH Enable signal hold time
  220. * tCS Enable signal setup time
  221. * tWH ND_nWE high duration
  222. * tWP ND_nWE pulse time
  223. * tRH ND_nRE high duration
  224. * tRP ND_nRE pulse width
  225. * tR ND_nWE high to ND_nRE low for read
  226. * tWHR ND_nWE high to ND_nRE low for status read
  227. * tAR ND_ALE low to ND_nRE low delay
  228. */
  229. /*ch cs wh wp rh rp r whr ar */
  230. { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
  231. { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
  232. { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
  233. { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
  234. { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
  235. };
  236. static struct pxa3xx_nand_flash builtin_flash_types[] = {
  237. /*
  238. * chip_id
  239. * flash_width Width of Flash memory (DWIDTH_M)
  240. * dfc_width Width of flash controller(DWIDTH_C)
  241. * *timing
  242. * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
  243. */
  244. { 0x46ec, 16, 16, &timing[1] },
  245. { 0xdaec, 8, 8, &timing[1] },
  246. { 0xd7ec, 8, 8, &timing[1] },
  247. { 0xa12c, 8, 8, &timing[2] },
  248. { 0xb12c, 16, 16, &timing[2] },
  249. { 0xdc2c, 8, 8, &timing[2] },
  250. { 0xcc2c, 16, 16, &timing[2] },
  251. { 0xba20, 16, 16, &timing[3] },
  252. { 0xda98, 8, 8, &timing[4] },
  253. };
  254. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  255. static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
  256. static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
  257. static struct nand_bbt_descr bbt_main_descr = {
  258. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  259. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  260. .offs = 8,
  261. .len = 6,
  262. .veroffs = 14,
  263. .maxblocks = 8, /* Last 8 blocks in each chip */
  264. .pattern = bbt_pattern
  265. };
  266. static struct nand_bbt_descr bbt_mirror_descr = {
  267. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  268. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  269. .offs = 8,
  270. .len = 6,
  271. .veroffs = 14,
  272. .maxblocks = 8, /* Last 8 blocks in each chip */
  273. .pattern = bbt_mirror_pattern
  274. };
  275. #endif
  276. static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
  277. .eccbytes = 32,
  278. .eccpos = {
  279. 32, 33, 34, 35, 36, 37, 38, 39,
  280. 40, 41, 42, 43, 44, 45, 46, 47,
  281. 48, 49, 50, 51, 52, 53, 54, 55,
  282. 56, 57, 58, 59, 60, 61, 62, 63},
  283. .oobfree = { {2, 30} }
  284. };
  285. static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
  286. .eccbytes = 64,
  287. .eccpos = {
  288. 32, 33, 34, 35, 36, 37, 38, 39,
  289. 40, 41, 42, 43, 44, 45, 46, 47,
  290. 48, 49, 50, 51, 52, 53, 54, 55,
  291. 56, 57, 58, 59, 60, 61, 62, 63,
  292. 64, 65, 66, 67, 68, 69, 70, 71,
  293. 72, 73, 74, 75, 76, 77, 78, 79,
  294. 80, 81, 82, 83, 84, 85, 86, 87,
  295. 88, 89, 90, 91, 92, 93, 94, 95},
  296. .oobfree = { {1, 4}, {6, 26} }
  297. };
  298. static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
  299. .eccbytes = 64,
  300. .eccpos = {
  301. 32, 33, 34, 35, 36, 37, 38, 39,
  302. 40, 41, 42, 43, 44, 45, 46, 47,
  303. 48, 49, 50, 51, 52, 53, 54, 55,
  304. 56, 57, 58, 59, 60, 61, 62, 63,
  305. 96, 97, 98, 99, 100, 101, 102, 103,
  306. 104, 105, 106, 107, 108, 109, 110, 111,
  307. 112, 113, 114, 115, 116, 117, 118, 119,
  308. 120, 121, 122, 123, 124, 125, 126, 127},
  309. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  310. .oobfree = { {6, 26}, { 64, 32} }
  311. };
  312. static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
  313. .eccbytes = 128,
  314. .eccpos = {
  315. 32, 33, 34, 35, 36, 37, 38, 39,
  316. 40, 41, 42, 43, 44, 45, 46, 47,
  317. 48, 49, 50, 51, 52, 53, 54, 55,
  318. 56, 57, 58, 59, 60, 61, 62, 63,
  319. 96, 97, 98, 99, 100, 101, 102, 103,
  320. 104, 105, 106, 107, 108, 109, 110, 111,
  321. 112, 113, 114, 115, 116, 117, 118, 119,
  322. 120, 121, 122, 123, 124, 125, 126, 127,
  323. 160, 161, 162, 163, 164, 165, 166, 167,
  324. 168, 169, 170, 171, 172, 173, 174, 175,
  325. 176, 177, 178, 179, 180, 181, 182, 183,
  326. 184, 185, 186, 187, 188, 189, 190, 191,
  327. 224, 225, 226, 227, 228, 229, 230, 231,
  328. 232, 233, 234, 235, 236, 237, 238, 239,
  329. 240, 241, 242, 243, 244, 245, 246, 247,
  330. 248, 249, 250, 251, 252, 253, 254, 255},
  331. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  332. .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
  333. };
  334. static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
  335. .eccbytes = 128,
  336. .eccpos = {
  337. 32, 33, 34, 35, 36, 37, 38, 39,
  338. 40, 41, 42, 43, 44, 45, 46, 47,
  339. 48, 49, 50, 51, 52, 53, 54, 55,
  340. 56, 57, 58, 59, 60, 61, 62, 63},
  341. .oobfree = { }
  342. };
  343. static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
  344. .eccbytes = 256,
  345. .eccpos = {},
  346. /* HW ECC handles all ECC data and all spare area is free for OOB */
  347. .oobfree = {{0, 160} }
  348. };
  349. #define NDTR0_tCH(c) (min((c), 7) << 19)
  350. #define NDTR0_tCS(c) (min((c), 7) << 16)
  351. #define NDTR0_tWH(c) (min((c), 7) << 11)
  352. #define NDTR0_tWP(c) (min((c), 7) << 8)
  353. #define NDTR0_tRH(c) (min((c), 7) << 3)
  354. #define NDTR0_tRP(c) (min((c), 7) << 0)
  355. #define NDTR1_tR(c) (min((c), 65535) << 16)
  356. #define NDTR1_tWHR(c) (min((c), 15) << 4)
  357. #define NDTR1_tAR(c) (min((c), 15) << 0)
  358. /* convert nano-seconds to nand flash controller clock cycles */
  359. #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
  360. static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
  361. {
  362. /* We only support the Armada 370/XP/38x for now */
  363. return PXA3XX_NAND_VARIANT_ARMADA370;
  364. }
  365. static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
  366. const struct pxa3xx_nand_timing *t)
  367. {
  368. struct pxa3xx_nand_info *info = host->info_data;
  369. unsigned long nand_clk = mvebu_get_nand_clock();
  370. uint32_t ndtr0, ndtr1;
  371. ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
  372. NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
  373. NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
  374. NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
  375. NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
  376. NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
  377. ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
  378. NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  379. NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  380. info->ndtr0cs0 = ndtr0;
  381. info->ndtr1cs0 = ndtr1;
  382. nand_writel(info, NDTR0CS0, ndtr0);
  383. nand_writel(info, NDTR1CS0, ndtr1);
  384. }
  385. static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
  386. const struct nand_sdr_timings *t)
  387. {
  388. struct pxa3xx_nand_info *info = host->info_data;
  389. struct nand_chip *chip = &host->chip;
  390. unsigned long nand_clk = mvebu_get_nand_clock();
  391. uint32_t ndtr0, ndtr1;
  392. u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
  393. u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
  394. u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
  395. u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
  396. u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
  397. u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
  398. u32 tR = chip->chip_delay * 1000;
  399. u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
  400. u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
  401. /* fallback to a default value if tR = 0 */
  402. if (!tR)
  403. tR = 20000;
  404. ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
  405. NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
  406. NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
  407. NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
  408. NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
  409. NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
  410. ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
  411. NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
  412. NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
  413. info->ndtr0cs0 = ndtr0;
  414. info->ndtr1cs0 = ndtr1;
  415. nand_writel(info, NDTR0CS0, ndtr0);
  416. nand_writel(info, NDTR1CS0, ndtr1);
  417. }
  418. static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
  419. {
  420. const struct nand_sdr_timings *timings;
  421. struct nand_chip *chip = &host->chip;
  422. struct pxa3xx_nand_info *info = host->info_data;
  423. const struct pxa3xx_nand_flash *f = NULL;
  424. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  425. int mode, id, ntypes, i;
  426. mode = onfi_get_async_timing_mode(chip);
  427. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  428. ntypes = ARRAY_SIZE(builtin_flash_types);
  429. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  430. id = chip->read_byte(mtd);
  431. id |= chip->read_byte(mtd) << 0x8;
  432. for (i = 0; i < ntypes; i++) {
  433. f = &builtin_flash_types[i];
  434. if (f->chip_id == id)
  435. break;
  436. }
  437. if (i == ntypes) {
  438. dev_err(&info->pdev->dev, "Error: timings not found\n");
  439. return -EINVAL;
  440. }
  441. pxa3xx_nand_set_timing(host, f->timing);
  442. if (f->flash_width == 16) {
  443. info->reg_ndcr |= NDCR_DWIDTH_M;
  444. chip->options |= NAND_BUSWIDTH_16;
  445. }
  446. info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
  447. } else {
  448. mode = fls(mode) - 1;
  449. if (mode < 0)
  450. mode = 0;
  451. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  452. if (IS_ERR(timings))
  453. return PTR_ERR(timings);
  454. pxa3xx_nand_set_sdr_timing(host, timings);
  455. }
  456. return 0;
  457. }
  458. /**
  459. * NOTE: it is a must to set ND_RUN first, then write
  460. * command buffer, otherwise, it does not work.
  461. * We enable all the interrupt at the same time, and
  462. * let pxa3xx_nand_irq to handle all logic.
  463. */
  464. static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  465. {
  466. uint32_t ndcr;
  467. ndcr = info->reg_ndcr;
  468. if (info->use_ecc) {
  469. ndcr |= NDCR_ECC_EN;
  470. if (info->ecc_bch)
  471. nand_writel(info, NDECCCTRL, 0x1);
  472. } else {
  473. ndcr &= ~NDCR_ECC_EN;
  474. if (info->ecc_bch)
  475. nand_writel(info, NDECCCTRL, 0x0);
  476. }
  477. ndcr &= ~NDCR_DMA_EN;
  478. if (info->use_spare)
  479. ndcr |= NDCR_SPARE_EN;
  480. else
  481. ndcr &= ~NDCR_SPARE_EN;
  482. ndcr |= NDCR_ND_RUN;
  483. /* clear status bits and run */
  484. nand_writel(info, NDSR, NDSR_MASK);
  485. nand_writel(info, NDCR, 0);
  486. nand_writel(info, NDCR, ndcr);
  487. }
  488. static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
  489. {
  490. uint32_t ndcr;
  491. ndcr = nand_readl(info, NDCR);
  492. nand_writel(info, NDCR, ndcr | int_mask);
  493. }
  494. static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
  495. {
  496. if (info->ecc_bch && !info->force_raw) {
  497. u32 ts;
  498. /*
  499. * According to the datasheet, when reading from NDDB
  500. * with BCH enabled, after each 32 bytes reads, we
  501. * have to make sure that the NDSR.RDDREQ bit is set.
  502. *
  503. * Drain the FIFO 8 32 bits reads at a time, and skip
  504. * the polling on the last read.
  505. */
  506. while (len > 8) {
  507. readsl(info->mmio_base + NDDB, data, 8);
  508. ts = get_timer(0);
  509. while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
  510. if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
  511. dev_err(&info->pdev->dev,
  512. "Timeout on RDDREQ while draining the FIFO\n");
  513. return;
  514. }
  515. }
  516. data += 32;
  517. len -= 8;
  518. }
  519. }
  520. readsl(info->mmio_base + NDDB, data, len);
  521. }
  522. static void handle_data_pio(struct pxa3xx_nand_info *info)
  523. {
  524. int data_len = info->step_chunk_size;
  525. /*
  526. * In raw mode, include the spare area and the ECC bytes that are not
  527. * consumed by the controller in the data section. Do not reorganize
  528. * here, do it in the ->read_page_raw() handler instead.
  529. */
  530. if (info->force_raw)
  531. data_len += info->step_spare_size + info->ecc_size;
  532. switch (info->state) {
  533. case STATE_PIO_WRITING:
  534. if (info->step_chunk_size)
  535. writesl(info->mmio_base + NDDB,
  536. info->data_buff + info->data_buff_pos,
  537. DIV_ROUND_UP(data_len, 4));
  538. if (info->step_spare_size)
  539. writesl(info->mmio_base + NDDB,
  540. info->oob_buff + info->oob_buff_pos,
  541. DIV_ROUND_UP(info->step_spare_size, 4));
  542. break;
  543. case STATE_PIO_READING:
  544. if (info->step_chunk_size)
  545. drain_fifo(info,
  546. info->data_buff + info->data_buff_pos,
  547. DIV_ROUND_UP(data_len, 4));
  548. if (info->force_raw)
  549. break;
  550. if (info->step_spare_size)
  551. drain_fifo(info,
  552. info->oob_buff + info->oob_buff_pos,
  553. DIV_ROUND_UP(info->step_spare_size, 4));
  554. break;
  555. default:
  556. dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
  557. info->state);
  558. BUG();
  559. }
  560. /* Update buffer pointers for multi-page read/write */
  561. info->data_buff_pos += data_len;
  562. info->oob_buff_pos += info->step_spare_size;
  563. }
  564. static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
  565. {
  566. handle_data_pio(info);
  567. info->state = STATE_CMD_DONE;
  568. nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
  569. }
  570. static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
  571. {
  572. unsigned int status, is_completed = 0, is_ready = 0;
  573. unsigned int ready, cmd_done;
  574. irqreturn_t ret = IRQ_HANDLED;
  575. if (info->cs == 0) {
  576. ready = NDSR_FLASH_RDY;
  577. cmd_done = NDSR_CS0_CMDD;
  578. } else {
  579. ready = NDSR_RDY;
  580. cmd_done = NDSR_CS1_CMDD;
  581. }
  582. /* TODO - find out why we need the delay during write operation. */
  583. ndelay(1);
  584. status = nand_readl(info, NDSR);
  585. if (status & NDSR_UNCORERR)
  586. info->retcode = ERR_UNCORERR;
  587. if (status & NDSR_CORERR) {
  588. info->retcode = ERR_CORERR;
  589. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
  590. info->ecc_bch)
  591. info->ecc_err_cnt = NDSR_ERR_CNT(status);
  592. else
  593. info->ecc_err_cnt = 1;
  594. /*
  595. * Each chunk composing a page is corrected independently,
  596. * and we need to store maximum number of corrected bitflips
  597. * to return it to the MTD layer in ecc.read_page().
  598. */
  599. info->max_bitflips = max_t(unsigned int,
  600. info->max_bitflips,
  601. info->ecc_err_cnt);
  602. }
  603. if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
  604. info->state = (status & NDSR_RDDREQ) ?
  605. STATE_PIO_READING : STATE_PIO_WRITING;
  606. /* Call the IRQ thread in U-Boot directly */
  607. pxa3xx_nand_irq_thread(info);
  608. return 0;
  609. }
  610. if (status & cmd_done) {
  611. info->state = STATE_CMD_DONE;
  612. is_completed = 1;
  613. }
  614. if (status & ready) {
  615. info->state = STATE_READY;
  616. is_ready = 1;
  617. }
  618. /*
  619. * Clear all status bit before issuing the next command, which
  620. * can and will alter the status bits and will deserve a new
  621. * interrupt on its own. This lets the controller exit the IRQ
  622. */
  623. nand_writel(info, NDSR, status);
  624. if (status & NDSR_WRCMDREQ) {
  625. status &= ~NDSR_WRCMDREQ;
  626. info->state = STATE_CMD_HANDLE;
  627. /*
  628. * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  629. * must be loaded by writing directly either 12 or 16
  630. * bytes directly to NDCB0, four bytes at a time.
  631. *
  632. * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  633. * but each NDCBx register can be read.
  634. */
  635. nand_writel(info, NDCB0, info->ndcb0);
  636. nand_writel(info, NDCB0, info->ndcb1);
  637. nand_writel(info, NDCB0, info->ndcb2);
  638. /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  639. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  640. nand_writel(info, NDCB0, info->ndcb3);
  641. }
  642. if (is_completed)
  643. info->cmd_complete = 1;
  644. if (is_ready)
  645. info->dev_ready = 1;
  646. return ret;
  647. }
  648. static inline int is_buf_blank(uint8_t *buf, size_t len)
  649. {
  650. for (; len > 0; len--)
  651. if (*buf++ != 0xff)
  652. return 0;
  653. return 1;
  654. }
  655. static void set_command_address(struct pxa3xx_nand_info *info,
  656. unsigned int page_size, uint16_t column, int page_addr)
  657. {
  658. /* small page addr setting */
  659. if (page_size < info->chunk_size) {
  660. info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  661. | (column & 0xFF);
  662. info->ndcb2 = 0;
  663. } else {
  664. info->ndcb1 = ((page_addr & 0xFFFF) << 16)
  665. | (column & 0xFFFF);
  666. if (page_addr & 0xFF0000)
  667. info->ndcb2 = (page_addr & 0xFF0000) >> 16;
  668. else
  669. info->ndcb2 = 0;
  670. }
  671. }
  672. static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  673. {
  674. struct pxa3xx_nand_host *host = info->host[info->cs];
  675. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  676. /* reset data and oob column point to handle data */
  677. info->buf_start = 0;
  678. info->buf_count = 0;
  679. info->data_buff_pos = 0;
  680. info->oob_buff_pos = 0;
  681. info->step_chunk_size = 0;
  682. info->step_spare_size = 0;
  683. info->cur_chunk = 0;
  684. info->use_ecc = 0;
  685. info->use_spare = 1;
  686. info->retcode = ERR_NONE;
  687. info->ecc_err_cnt = 0;
  688. info->ndcb3 = 0;
  689. info->need_wait = 0;
  690. switch (command) {
  691. case NAND_CMD_READ0:
  692. case NAND_CMD_READOOB:
  693. case NAND_CMD_PAGEPROG:
  694. if (!info->force_raw)
  695. info->use_ecc = 1;
  696. break;
  697. case NAND_CMD_PARAM:
  698. info->use_spare = 0;
  699. break;
  700. default:
  701. info->ndcb1 = 0;
  702. info->ndcb2 = 0;
  703. break;
  704. }
  705. /*
  706. * If we are about to issue a read command, or about to set
  707. * the write address, then clean the data buffer.
  708. */
  709. if (command == NAND_CMD_READ0 ||
  710. command == NAND_CMD_READOOB ||
  711. command == NAND_CMD_SEQIN) {
  712. info->buf_count = mtd->writesize + mtd->oobsize;
  713. memset(info->data_buff, 0xFF, info->buf_count);
  714. }
  715. }
  716. static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  717. int ext_cmd_type, uint16_t column, int page_addr)
  718. {
  719. int addr_cycle, exec_cmd;
  720. struct pxa3xx_nand_host *host;
  721. struct mtd_info *mtd;
  722. host = info->host[info->cs];
  723. mtd = nand_to_mtd(&host->chip);
  724. addr_cycle = 0;
  725. exec_cmd = 1;
  726. if (info->cs != 0)
  727. info->ndcb0 = NDCB0_CSEL;
  728. else
  729. info->ndcb0 = 0;
  730. if (command == NAND_CMD_SEQIN)
  731. exec_cmd = 0;
  732. addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  733. + host->col_addr_cycles);
  734. switch (command) {
  735. case NAND_CMD_READOOB:
  736. case NAND_CMD_READ0:
  737. info->buf_start = column;
  738. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  739. | addr_cycle
  740. | NAND_CMD_READ0;
  741. if (command == NAND_CMD_READOOB)
  742. info->buf_start += mtd->writesize;
  743. if (info->cur_chunk < info->nfullchunks) {
  744. info->step_chunk_size = info->chunk_size;
  745. info->step_spare_size = info->spare_size;
  746. } else {
  747. info->step_chunk_size = info->last_chunk_size;
  748. info->step_spare_size = info->last_spare_size;
  749. }
  750. /*
  751. * Multiple page read needs an 'extended command type' field,
  752. * which is either naked-read or last-read according to the
  753. * state.
  754. */
  755. if (info->force_raw) {
  756. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) |
  757. NDCB0_LEN_OVRD |
  758. NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  759. info->ndcb3 = info->step_chunk_size +
  760. info->step_spare_size + info->ecc_size;
  761. } else if (mtd->writesize == info->chunk_size) {
  762. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  763. } else if (mtd->writesize > info->chunk_size) {
  764. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
  765. | NDCB0_LEN_OVRD
  766. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  767. info->ndcb3 = info->step_chunk_size +
  768. info->step_spare_size;
  769. }
  770. set_command_address(info, mtd->writesize, column, page_addr);
  771. break;
  772. case NAND_CMD_SEQIN:
  773. info->buf_start = column;
  774. set_command_address(info, mtd->writesize, 0, page_addr);
  775. /*
  776. * Multiple page programming needs to execute the initial
  777. * SEQIN command that sets the page address.
  778. */
  779. if (mtd->writesize > info->chunk_size) {
  780. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  781. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  782. | addr_cycle
  783. | command;
  784. exec_cmd = 1;
  785. }
  786. break;
  787. case NAND_CMD_PAGEPROG:
  788. if (is_buf_blank(info->data_buff,
  789. (mtd->writesize + mtd->oobsize))) {
  790. exec_cmd = 0;
  791. break;
  792. }
  793. if (info->cur_chunk < info->nfullchunks) {
  794. info->step_chunk_size = info->chunk_size;
  795. info->step_spare_size = info->spare_size;
  796. } else {
  797. info->step_chunk_size = info->last_chunk_size;
  798. info->step_spare_size = info->last_spare_size;
  799. }
  800. /* Second command setting for large pages */
  801. if (mtd->writesize > info->chunk_size) {
  802. /*
  803. * Multiple page write uses the 'extended command'
  804. * field. This can be used to issue a command dispatch
  805. * or a naked-write depending on the current stage.
  806. */
  807. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  808. | NDCB0_LEN_OVRD
  809. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  810. info->ndcb3 = info->step_chunk_size +
  811. info->step_spare_size;
  812. /*
  813. * This is the command dispatch that completes a chunked
  814. * page program operation.
  815. */
  816. if (info->cur_chunk == info->ntotalchunks) {
  817. info->ndcb0 = NDCB0_CMD_TYPE(0x1)
  818. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  819. | command;
  820. info->ndcb1 = 0;
  821. info->ndcb2 = 0;
  822. info->ndcb3 = 0;
  823. }
  824. } else {
  825. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  826. | NDCB0_AUTO_RS
  827. | NDCB0_ST_ROW_EN
  828. | NDCB0_DBC
  829. | (NAND_CMD_PAGEPROG << 8)
  830. | NAND_CMD_SEQIN
  831. | addr_cycle;
  832. }
  833. break;
  834. case NAND_CMD_PARAM:
  835. info->buf_count = INIT_BUFFER_SIZE;
  836. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  837. | NDCB0_ADDR_CYC(1)
  838. | NDCB0_LEN_OVRD
  839. | command;
  840. info->ndcb1 = (column & 0xFF);
  841. info->ndcb3 = INIT_BUFFER_SIZE;
  842. info->step_chunk_size = INIT_BUFFER_SIZE;
  843. break;
  844. case NAND_CMD_READID:
  845. info->buf_count = READ_ID_BYTES;
  846. info->ndcb0 |= NDCB0_CMD_TYPE(3)
  847. | NDCB0_ADDR_CYC(1)
  848. | command;
  849. info->ndcb1 = (column & 0xFF);
  850. info->step_chunk_size = 8;
  851. break;
  852. case NAND_CMD_STATUS:
  853. info->buf_count = 1;
  854. info->ndcb0 |= NDCB0_CMD_TYPE(4)
  855. | NDCB0_ADDR_CYC(1)
  856. | command;
  857. info->step_chunk_size = 8;
  858. break;
  859. case NAND_CMD_ERASE1:
  860. info->ndcb0 |= NDCB0_CMD_TYPE(2)
  861. | NDCB0_AUTO_RS
  862. | NDCB0_ADDR_CYC(3)
  863. | NDCB0_DBC
  864. | (NAND_CMD_ERASE2 << 8)
  865. | NAND_CMD_ERASE1;
  866. info->ndcb1 = page_addr;
  867. info->ndcb2 = 0;
  868. break;
  869. case NAND_CMD_RESET:
  870. info->ndcb0 |= NDCB0_CMD_TYPE(5)
  871. | command;
  872. break;
  873. case NAND_CMD_ERASE2:
  874. exec_cmd = 0;
  875. break;
  876. default:
  877. exec_cmd = 0;
  878. dev_err(&info->pdev->dev, "non-supported command %x\n",
  879. command);
  880. break;
  881. }
  882. return exec_cmd;
  883. }
  884. static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
  885. int column, int page_addr)
  886. {
  887. struct nand_chip *chip = mtd_to_nand(mtd);
  888. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  889. struct pxa3xx_nand_info *info = host->info_data;
  890. int exec_cmd;
  891. /*
  892. * if this is a x16 device ,then convert the input
  893. * "byte" address into a "word" address appropriate
  894. * for indexing a word-oriented device
  895. */
  896. if (info->reg_ndcr & NDCR_DWIDTH_M)
  897. column /= 2;
  898. /*
  899. * There may be different NAND chip hooked to
  900. * different chip select, so check whether
  901. * chip select has been changed, if yes, reset the timing
  902. */
  903. if (info->cs != host->cs) {
  904. info->cs = host->cs;
  905. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  906. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  907. }
  908. prepare_start_command(info, command);
  909. info->state = STATE_PREPARED;
  910. exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
  911. if (exec_cmd) {
  912. u32 ts;
  913. info->cmd_complete = 0;
  914. info->dev_ready = 0;
  915. info->need_wait = 1;
  916. pxa3xx_nand_start(info);
  917. ts = get_timer(0);
  918. while (1) {
  919. u32 status;
  920. status = nand_readl(info, NDSR);
  921. if (status)
  922. pxa3xx_nand_irq(info);
  923. if (info->cmd_complete)
  924. break;
  925. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  926. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  927. return;
  928. }
  929. }
  930. }
  931. info->state = STATE_IDLE;
  932. }
  933. static void nand_cmdfunc_extended(struct mtd_info *mtd,
  934. const unsigned command,
  935. int column, int page_addr)
  936. {
  937. struct nand_chip *chip = mtd_to_nand(mtd);
  938. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  939. struct pxa3xx_nand_info *info = host->info_data;
  940. int exec_cmd, ext_cmd_type;
  941. /*
  942. * if this is a x16 device then convert the input
  943. * "byte" address into a "word" address appropriate
  944. * for indexing a word-oriented device
  945. */
  946. if (info->reg_ndcr & NDCR_DWIDTH_M)
  947. column /= 2;
  948. /*
  949. * There may be different NAND chip hooked to
  950. * different chip select, so check whether
  951. * chip select has been changed, if yes, reset the timing
  952. */
  953. if (info->cs != host->cs) {
  954. info->cs = host->cs;
  955. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  956. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  957. }
  958. /* Select the extended command for the first command */
  959. switch (command) {
  960. case NAND_CMD_READ0:
  961. case NAND_CMD_READOOB:
  962. ext_cmd_type = EXT_CMD_TYPE_MONO;
  963. break;
  964. case NAND_CMD_SEQIN:
  965. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  966. break;
  967. case NAND_CMD_PAGEPROG:
  968. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  969. break;
  970. default:
  971. ext_cmd_type = 0;
  972. break;
  973. }
  974. prepare_start_command(info, command);
  975. /*
  976. * Prepare the "is ready" completion before starting a command
  977. * transaction sequence. If the command is not executed the
  978. * completion will be completed, see below.
  979. *
  980. * We can do that inside the loop because the command variable
  981. * is invariant and thus so is the exec_cmd.
  982. */
  983. info->need_wait = 1;
  984. info->dev_ready = 0;
  985. do {
  986. u32 ts;
  987. info->state = STATE_PREPARED;
  988. exec_cmd = prepare_set_command(info, command, ext_cmd_type,
  989. column, page_addr);
  990. if (!exec_cmd) {
  991. info->need_wait = 0;
  992. info->dev_ready = 1;
  993. break;
  994. }
  995. info->cmd_complete = 0;
  996. pxa3xx_nand_start(info);
  997. ts = get_timer(0);
  998. while (1) {
  999. u32 status;
  1000. status = nand_readl(info, NDSR);
  1001. if (status)
  1002. pxa3xx_nand_irq(info);
  1003. if (info->cmd_complete)
  1004. break;
  1005. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1006. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  1007. return;
  1008. }
  1009. }
  1010. /* Only a few commands need several steps */
  1011. if (command != NAND_CMD_PAGEPROG &&
  1012. command != NAND_CMD_READ0 &&
  1013. command != NAND_CMD_READOOB)
  1014. break;
  1015. info->cur_chunk++;
  1016. /* Check if the sequence is complete */
  1017. if (info->cur_chunk == info->ntotalchunks &&
  1018. command != NAND_CMD_PAGEPROG)
  1019. break;
  1020. /*
  1021. * After a splitted program command sequence has issued
  1022. * the command dispatch, the command sequence is complete.
  1023. */
  1024. if (info->cur_chunk == (info->ntotalchunks + 1) &&
  1025. command == NAND_CMD_PAGEPROG &&
  1026. ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
  1027. break;
  1028. if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
  1029. /* Last read: issue a 'last naked read' */
  1030. if (info->cur_chunk == info->ntotalchunks - 1)
  1031. ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
  1032. else
  1033. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  1034. /*
  1035. * If a splitted program command has no more data to transfer,
  1036. * the command dispatch must be issued to complete.
  1037. */
  1038. } else if (command == NAND_CMD_PAGEPROG &&
  1039. info->cur_chunk == info->ntotalchunks) {
  1040. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  1041. }
  1042. } while (1);
  1043. info->state = STATE_IDLE;
  1044. }
  1045. static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
  1046. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  1047. int page)
  1048. {
  1049. chip->write_buf(mtd, buf, mtd->writesize);
  1050. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1051. return 0;
  1052. }
  1053. static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
  1054. struct nand_chip *chip, uint8_t *buf, int oob_required,
  1055. int page)
  1056. {
  1057. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1058. struct pxa3xx_nand_info *info = host->info_data;
  1059. int bf;
  1060. chip->read_buf(mtd, buf, mtd->writesize);
  1061. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1062. if (info->retcode == ERR_CORERR && info->use_ecc) {
  1063. mtd->ecc_stats.corrected += info->ecc_err_cnt;
  1064. } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) {
  1065. /*
  1066. * Empty pages will trigger uncorrectable errors. Re-read the
  1067. * entire page in raw mode and check for bits not being "1".
  1068. * If there are more than the supported strength, then it means
  1069. * this is an actual uncorrectable error.
  1070. */
  1071. chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page);
  1072. bf = nand_check_erased_ecc_chunk(buf, mtd->writesize,
  1073. chip->oob_poi, mtd->oobsize,
  1074. NULL, 0, chip->ecc.strength);
  1075. if (bf < 0) {
  1076. mtd->ecc_stats.failed++;
  1077. } else if (bf) {
  1078. mtd->ecc_stats.corrected += bf;
  1079. info->max_bitflips = max_t(unsigned int,
  1080. info->max_bitflips, bf);
  1081. info->retcode = ERR_CORERR;
  1082. } else {
  1083. info->retcode = ERR_NONE;
  1084. }
  1085. } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) {
  1086. /* Raw read is not supported with Hamming ECC engine */
  1087. if (is_buf_blank(buf, mtd->writesize))
  1088. info->retcode = ERR_NONE;
  1089. else
  1090. mtd->ecc_stats.failed++;
  1091. }
  1092. return info->max_bitflips;
  1093. }
  1094. static int pxa3xx_nand_read_page_raw(struct mtd_info *mtd,
  1095. struct nand_chip *chip, uint8_t *buf,
  1096. int oob_required, int page)
  1097. {
  1098. struct pxa3xx_nand_host *host = chip->priv;
  1099. struct pxa3xx_nand_info *info = host->info_data;
  1100. int chunk, ecc_off_buf;
  1101. if (!info->ecc_bch)
  1102. return -ENOTSUPP;
  1103. /*
  1104. * Set the force_raw boolean, then re-call ->cmdfunc() that will run
  1105. * pxa3xx_nand_start(), which will actually disable the ECC engine.
  1106. */
  1107. info->force_raw = true;
  1108. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  1109. ecc_off_buf = (info->nfullchunks * info->spare_size) +
  1110. info->last_spare_size;
  1111. for (chunk = 0; chunk < info->nfullchunks; chunk++) {
  1112. chip->read_buf(mtd,
  1113. buf + (chunk * info->chunk_size),
  1114. info->chunk_size);
  1115. chip->read_buf(mtd,
  1116. chip->oob_poi +
  1117. (chunk * (info->spare_size)),
  1118. info->spare_size);
  1119. chip->read_buf(mtd,
  1120. chip->oob_poi + ecc_off_buf +
  1121. (chunk * (info->ecc_size)),
  1122. info->ecc_size - 2);
  1123. }
  1124. if (info->ntotalchunks > info->nfullchunks) {
  1125. chip->read_buf(mtd,
  1126. buf + (info->nfullchunks * info->chunk_size),
  1127. info->last_chunk_size);
  1128. chip->read_buf(mtd,
  1129. chip->oob_poi +
  1130. (info->nfullchunks * (info->spare_size)),
  1131. info->last_spare_size);
  1132. chip->read_buf(mtd,
  1133. chip->oob_poi + ecc_off_buf +
  1134. (info->nfullchunks * (info->ecc_size)),
  1135. info->ecc_size - 2);
  1136. }
  1137. info->force_raw = false;
  1138. return 0;
  1139. }
  1140. static int pxa3xx_nand_read_oob_raw(struct mtd_info *mtd,
  1141. struct nand_chip *chip, int page)
  1142. {
  1143. /* Invalidate page cache */
  1144. chip->pagebuf = -1;
  1145. return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true,
  1146. page);
  1147. }
  1148. static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
  1149. {
  1150. struct nand_chip *chip = mtd_to_nand(mtd);
  1151. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1152. struct pxa3xx_nand_info *info = host->info_data;
  1153. char retval = 0xFF;
  1154. if (info->buf_start < info->buf_count)
  1155. /* Has just send a new command? */
  1156. retval = info->data_buff[info->buf_start++];
  1157. return retval;
  1158. }
  1159. static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
  1160. {
  1161. struct nand_chip *chip = mtd_to_nand(mtd);
  1162. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1163. struct pxa3xx_nand_info *info = host->info_data;
  1164. u16 retval = 0xFFFF;
  1165. if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
  1166. retval = *((u16 *)(info->data_buff+info->buf_start));
  1167. info->buf_start += 2;
  1168. }
  1169. return retval;
  1170. }
  1171. static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  1172. {
  1173. struct nand_chip *chip = mtd_to_nand(mtd);
  1174. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1175. struct pxa3xx_nand_info *info = host->info_data;
  1176. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1177. memcpy(buf, info->data_buff + info->buf_start, real_len);
  1178. info->buf_start += real_len;
  1179. }
  1180. static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
  1181. const uint8_t *buf, int len)
  1182. {
  1183. struct nand_chip *chip = mtd_to_nand(mtd);
  1184. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1185. struct pxa3xx_nand_info *info = host->info_data;
  1186. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1187. memcpy(info->data_buff + info->buf_start, buf, real_len);
  1188. info->buf_start += real_len;
  1189. }
  1190. static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
  1191. {
  1192. return;
  1193. }
  1194. static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  1195. {
  1196. struct nand_chip *chip = mtd_to_nand(mtd);
  1197. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1198. struct pxa3xx_nand_info *info = host->info_data;
  1199. if (info->need_wait) {
  1200. u32 ts;
  1201. info->need_wait = 0;
  1202. ts = get_timer(0);
  1203. while (1) {
  1204. u32 status;
  1205. status = nand_readl(info, NDSR);
  1206. if (status)
  1207. pxa3xx_nand_irq(info);
  1208. if (info->dev_ready)
  1209. break;
  1210. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1211. dev_err(&info->pdev->dev, "Ready timeout!!!\n");
  1212. return NAND_STATUS_FAIL;
  1213. }
  1214. }
  1215. }
  1216. /* pxa3xx_nand_send_command has waited for command complete */
  1217. if (this->state == FL_WRITING || this->state == FL_ERASING) {
  1218. if (info->retcode == ERR_NONE)
  1219. return 0;
  1220. else
  1221. return NAND_STATUS_FAIL;
  1222. }
  1223. return NAND_STATUS_READY;
  1224. }
  1225. static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
  1226. {
  1227. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1228. /* Configure default flash values */
  1229. info->reg_ndcr = 0x0; /* enable all interrupts */
  1230. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1231. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1232. info->reg_ndcr |= NDCR_SPARE_EN;
  1233. return 0;
  1234. }
  1235. static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
  1236. {
  1237. struct pxa3xx_nand_host *host = info->host[info->cs];
  1238. struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1239. struct nand_chip *chip = mtd_to_nand(mtd);
  1240. info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
  1241. info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
  1242. info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
  1243. }
  1244. static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
  1245. {
  1246. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1247. uint32_t ndcr = nand_readl(info, NDCR);
  1248. /* Set an initial chunk size */
  1249. info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
  1250. info->reg_ndcr = ndcr &
  1251. ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
  1252. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1253. info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
  1254. info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
  1255. }
  1256. static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
  1257. {
  1258. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1259. if (info->data_buff == NULL)
  1260. return -ENOMEM;
  1261. return 0;
  1262. }
  1263. static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
  1264. {
  1265. struct pxa3xx_nand_info *info = host->info_data;
  1266. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1267. struct mtd_info *mtd;
  1268. struct nand_chip *chip;
  1269. const struct nand_sdr_timings *timings;
  1270. int ret;
  1271. mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1272. chip = mtd_to_nand(mtd);
  1273. /* configure default flash values */
  1274. info->reg_ndcr = 0x0; /* enable all interrupts */
  1275. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1276. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1277. info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  1278. /* use the common timing to make a try */
  1279. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1280. if (IS_ERR(timings))
  1281. return PTR_ERR(timings);
  1282. pxa3xx_nand_set_sdr_timing(host, timings);
  1283. chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
  1284. ret = chip->waitfunc(mtd, chip);
  1285. if (ret & NAND_STATUS_FAIL)
  1286. return -ENODEV;
  1287. return 0;
  1288. }
  1289. static int pxa_ecc_init(struct pxa3xx_nand_info *info,
  1290. struct nand_ecc_ctrl *ecc,
  1291. int strength, int ecc_stepsize, int page_size)
  1292. {
  1293. if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
  1294. info->nfullchunks = 1;
  1295. info->ntotalchunks = 1;
  1296. info->chunk_size = 2048;
  1297. info->spare_size = 40;
  1298. info->ecc_size = 24;
  1299. ecc->mode = NAND_ECC_HW;
  1300. ecc->size = 512;
  1301. ecc->strength = 1;
  1302. } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
  1303. info->nfullchunks = 1;
  1304. info->ntotalchunks = 1;
  1305. info->chunk_size = 512;
  1306. info->spare_size = 8;
  1307. info->ecc_size = 8;
  1308. ecc->mode = NAND_ECC_HW;
  1309. ecc->size = 512;
  1310. ecc->strength = 1;
  1311. /*
  1312. * Required ECC: 4-bit correction per 512 bytes
  1313. * Select: 16-bit correction per 2048 bytes
  1314. */
  1315. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
  1316. info->ecc_bch = 1;
  1317. info->nfullchunks = 1;
  1318. info->ntotalchunks = 1;
  1319. info->chunk_size = 2048;
  1320. info->spare_size = 32;
  1321. info->ecc_size = 32;
  1322. ecc->mode = NAND_ECC_HW;
  1323. ecc->size = info->chunk_size;
  1324. ecc->layout = &ecc_layout_2KB_bch4bit;
  1325. ecc->strength = 16;
  1326. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
  1327. info->ecc_bch = 1;
  1328. info->nfullchunks = 2;
  1329. info->ntotalchunks = 2;
  1330. info->chunk_size = 2048;
  1331. info->spare_size = 32;
  1332. info->ecc_size = 32;
  1333. ecc->mode = NAND_ECC_HW;
  1334. ecc->size = info->chunk_size;
  1335. ecc->layout = &ecc_layout_4KB_bch4bit;
  1336. ecc->strength = 16;
  1337. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
  1338. info->ecc_bch = 1;
  1339. info->nfullchunks = 4;
  1340. info->ntotalchunks = 4;
  1341. info->chunk_size = 2048;
  1342. info->spare_size = 32;
  1343. info->ecc_size = 32;
  1344. ecc->mode = NAND_ECC_HW;
  1345. ecc->size = info->chunk_size;
  1346. ecc->layout = &ecc_layout_8KB_bch4bit;
  1347. ecc->strength = 16;
  1348. /*
  1349. * Required ECC: 8-bit correction per 512 bytes
  1350. * Select: 16-bit correction per 1024 bytes
  1351. */
  1352. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
  1353. info->ecc_bch = 1;
  1354. info->nfullchunks = 1;
  1355. info->ntotalchunks = 2;
  1356. info->chunk_size = 1024;
  1357. info->spare_size = 0;
  1358. info->last_chunk_size = 1024;
  1359. info->last_spare_size = 32;
  1360. info->ecc_size = 32;
  1361. ecc->mode = NAND_ECC_HW;
  1362. ecc->size = info->chunk_size;
  1363. ecc->layout = &ecc_layout_2KB_bch8bit;
  1364. ecc->strength = 16;
  1365. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
  1366. info->ecc_bch = 1;
  1367. info->nfullchunks = 4;
  1368. info->ntotalchunks = 5;
  1369. info->chunk_size = 1024;
  1370. info->spare_size = 0;
  1371. info->last_chunk_size = 0;
  1372. info->last_spare_size = 64;
  1373. info->ecc_size = 32;
  1374. ecc->mode = NAND_ECC_HW;
  1375. ecc->size = info->chunk_size;
  1376. ecc->layout = &ecc_layout_4KB_bch8bit;
  1377. ecc->strength = 16;
  1378. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
  1379. info->ecc_bch = 1;
  1380. info->nfullchunks = 8;
  1381. info->ntotalchunks = 9;
  1382. info->chunk_size = 1024;
  1383. info->spare_size = 0;
  1384. info->last_chunk_size = 0;
  1385. info->last_spare_size = 160;
  1386. info->ecc_size = 32;
  1387. ecc->mode = NAND_ECC_HW;
  1388. ecc->size = info->chunk_size;
  1389. ecc->layout = &ecc_layout_8KB_bch8bit;
  1390. ecc->strength = 16;
  1391. } else {
  1392. dev_err(&info->pdev->dev,
  1393. "ECC strength %d at page size %d is not supported\n",
  1394. strength, page_size);
  1395. return -ENODEV;
  1396. }
  1397. return 0;
  1398. }
  1399. static int pxa3xx_nand_scan(struct mtd_info *mtd)
  1400. {
  1401. struct nand_chip *chip = mtd_to_nand(mtd);
  1402. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1403. struct pxa3xx_nand_info *info = host->info_data;
  1404. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1405. int ret;
  1406. uint16_t ecc_strength, ecc_step;
  1407. if (pdata->keep_config) {
  1408. pxa3xx_nand_detect_config(info);
  1409. } else {
  1410. ret = pxa3xx_nand_config_ident(info);
  1411. if (ret)
  1412. return ret;
  1413. ret = pxa3xx_nand_sensing(host);
  1414. if (ret) {
  1415. dev_info(&info->pdev->dev,
  1416. "There is no chip on cs %d!\n",
  1417. info->cs);
  1418. return ret;
  1419. }
  1420. }
  1421. /* Device detection must be done with ECC disabled */
  1422. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  1423. nand_writel(info, NDECCCTRL, 0x0);
  1424. if (nand_scan_ident(mtd, 1, NULL))
  1425. return -ENODEV;
  1426. if (!pdata->keep_config) {
  1427. ret = pxa3xx_nand_init_timings(host);
  1428. if (ret) {
  1429. dev_err(&info->pdev->dev,
  1430. "Failed to set timings: %d\n", ret);
  1431. return ret;
  1432. }
  1433. }
  1434. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1435. /*
  1436. * We'll use a bad block table stored in-flash and don't
  1437. * allow writing the bad block marker to the flash.
  1438. */
  1439. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
  1440. chip->bbt_td = &bbt_main_descr;
  1441. chip->bbt_md = &bbt_mirror_descr;
  1442. #endif
  1443. if (pdata->ecc_strength && pdata->ecc_step_size) {
  1444. ecc_strength = pdata->ecc_strength;
  1445. ecc_step = pdata->ecc_step_size;
  1446. } else {
  1447. ecc_strength = chip->ecc_strength_ds;
  1448. ecc_step = chip->ecc_step_ds;
  1449. }
  1450. /* Set default ECC strength requirements on non-ONFI devices */
  1451. if (ecc_strength < 1 && ecc_step < 1) {
  1452. ecc_strength = 1;
  1453. ecc_step = 512;
  1454. }
  1455. ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
  1456. ecc_step, mtd->writesize);
  1457. if (ret)
  1458. return ret;
  1459. /*
  1460. * If the page size is bigger than the FIFO size, let's check
  1461. * we are given the right variant and then switch to the extended
  1462. * (aka split) command handling,
  1463. */
  1464. if (mtd->writesize > info->chunk_size) {
  1465. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
  1466. chip->cmdfunc = nand_cmdfunc_extended;
  1467. } else {
  1468. dev_err(&info->pdev->dev,
  1469. "unsupported page size on this variant\n");
  1470. return -ENODEV;
  1471. }
  1472. }
  1473. /* calculate addressing information */
  1474. if (mtd->writesize >= 2048)
  1475. host->col_addr_cycles = 2;
  1476. else
  1477. host->col_addr_cycles = 1;
  1478. /* release the initial buffer */
  1479. kfree(info->data_buff);
  1480. /* allocate the real data + oob buffer */
  1481. info->buf_size = mtd->writesize + mtd->oobsize;
  1482. ret = pxa3xx_nand_init_buff(info);
  1483. if (ret)
  1484. return ret;
  1485. info->oob_buff = info->data_buff + mtd->writesize;
  1486. if ((mtd->size >> chip->page_shift) > 65536)
  1487. host->row_addr_cycles = 3;
  1488. else
  1489. host->row_addr_cycles = 2;
  1490. if (!pdata->keep_config)
  1491. pxa3xx_nand_config_tail(info);
  1492. return nand_scan_tail(mtd);
  1493. }
  1494. static int alloc_nand_resource(struct pxa3xx_nand_info *info)
  1495. {
  1496. struct pxa3xx_nand_platform_data *pdata;
  1497. struct pxa3xx_nand_host *host;
  1498. struct nand_chip *chip = NULL;
  1499. struct mtd_info *mtd;
  1500. int ret, cs;
  1501. pdata = info->pdata;
  1502. if (pdata->num_cs <= 0)
  1503. return -ENODEV;
  1504. info->variant = pxa3xx_nand_get_variant();
  1505. for (cs = 0; cs < pdata->num_cs; cs++) {
  1506. chip = (struct nand_chip *)
  1507. ((u8 *)&info[1] + sizeof(*host) * cs);
  1508. mtd = nand_to_mtd(chip);
  1509. host = (struct pxa3xx_nand_host *)chip;
  1510. info->host[cs] = host;
  1511. host->cs = cs;
  1512. host->info_data = info;
  1513. mtd->owner = THIS_MODULE;
  1514. nand_set_controller_data(chip, host);
  1515. chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
  1516. chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw;
  1517. chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw;
  1518. chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
  1519. chip->controller = &info->controller;
  1520. chip->waitfunc = pxa3xx_nand_waitfunc;
  1521. chip->select_chip = pxa3xx_nand_select_chip;
  1522. chip->read_word = pxa3xx_nand_read_word;
  1523. chip->read_byte = pxa3xx_nand_read_byte;
  1524. chip->read_buf = pxa3xx_nand_read_buf;
  1525. chip->write_buf = pxa3xx_nand_write_buf;
  1526. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1527. chip->cmdfunc = nand_cmdfunc;
  1528. }
  1529. /* Allocate a buffer to allow flash detection */
  1530. info->buf_size = INIT_BUFFER_SIZE;
  1531. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1532. if (info->data_buff == NULL) {
  1533. ret = -ENOMEM;
  1534. goto fail_disable_clk;
  1535. }
  1536. /* initialize all interrupts to be disabled */
  1537. disable_int(info, NDSR_MASK);
  1538. return 0;
  1539. kfree(info->data_buff);
  1540. fail_disable_clk:
  1541. return ret;
  1542. }
  1543. static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
  1544. {
  1545. struct pxa3xx_nand_platform_data *pdata;
  1546. const void *blob = gd->fdt_blob;
  1547. int node = -1;
  1548. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  1549. if (!pdata)
  1550. return -ENOMEM;
  1551. /* Get address decoding nodes from the FDT blob */
  1552. do {
  1553. node = fdt_node_offset_by_compatible(blob, node,
  1554. "marvell,mvebu-pxa3xx-nand");
  1555. if (node < 0)
  1556. break;
  1557. /* Bypass disabeld nodes */
  1558. if (!fdtdec_get_is_enabled(blob, node))
  1559. continue;
  1560. /* Get the first enabled NAND controler base address */
  1561. info->mmio_base =
  1562. (void __iomem *)fdtdec_get_addr_size_auto_noparent(
  1563. blob, node, "reg", 0, NULL, true);
  1564. pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
  1565. if (pdata->num_cs != 1) {
  1566. pr_err("pxa3xx driver supports single CS only\n");
  1567. break;
  1568. }
  1569. if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
  1570. pdata->enable_arbiter = 1;
  1571. if (fdtdec_get_bool(blob, node, "nand-keep-config"))
  1572. pdata->keep_config = 1;
  1573. /*
  1574. * ECC parameters.
  1575. * If these are not set, they will be selected according
  1576. * to the detected flash type.
  1577. */
  1578. /* ECC strength */
  1579. pdata->ecc_strength = fdtdec_get_int(blob, node,
  1580. "nand-ecc-strength", 0);
  1581. /* ECC step size */
  1582. pdata->ecc_step_size = fdtdec_get_int(blob, node,
  1583. "nand-ecc-step-size", 0);
  1584. info->pdata = pdata;
  1585. /* Currently support only a single NAND controller */
  1586. return 0;
  1587. } while (node >= 0);
  1588. return -EINVAL;
  1589. }
  1590. static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
  1591. {
  1592. struct pxa3xx_nand_platform_data *pdata;
  1593. int ret, cs, probe_success;
  1594. ret = pxa3xx_nand_probe_dt(info);
  1595. if (ret)
  1596. return ret;
  1597. pdata = info->pdata;
  1598. ret = alloc_nand_resource(info);
  1599. if (ret) {
  1600. dev_err(&pdev->dev, "alloc nand resource failed\n");
  1601. return ret;
  1602. }
  1603. probe_success = 0;
  1604. for (cs = 0; cs < pdata->num_cs; cs++) {
  1605. struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
  1606. /*
  1607. * The mtd name matches the one used in 'mtdparts' kernel
  1608. * parameter. This name cannot be changed or otherwise
  1609. * user's mtd partitions configuration would get broken.
  1610. */
  1611. mtd->name = "pxa3xx_nand-0";
  1612. info->cs = cs;
  1613. ret = pxa3xx_nand_scan(mtd);
  1614. if (ret) {
  1615. dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
  1616. cs);
  1617. continue;
  1618. }
  1619. if (nand_register(cs, mtd))
  1620. continue;
  1621. probe_success = 1;
  1622. }
  1623. if (!probe_success)
  1624. return -ENODEV;
  1625. return 0;
  1626. }
  1627. /*
  1628. * Main initialization routine
  1629. */
  1630. void board_nand_init(void)
  1631. {
  1632. struct pxa3xx_nand_info *info;
  1633. struct pxa3xx_nand_host *host;
  1634. int ret;
  1635. info = kzalloc(sizeof(*info) +
  1636. sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
  1637. GFP_KERNEL);
  1638. if (!info)
  1639. return;
  1640. ret = pxa3xx_nand_probe(info);
  1641. if (ret)
  1642. return;
  1643. }