fsl_ifc_nand.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Integrated Flash Controller NAND Machine Driver
  3. *
  4. * Copyright (c) 2012 Freescale Semiconductor, Inc
  5. *
  6. * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <malloc.h>
  11. #include <nand.h>
  12. #include <dm/devres.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/rawnand.h>
  15. #include <linux/mtd/nand_ecc.h>
  16. #include <asm/io.h>
  17. #include <linux/errno.h>
  18. #include <fsl_ifc.h>
  19. #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  20. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  21. #endif
  22. #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
  23. #define ERR_BYTE 0xFF /* Value returned for read bytes
  24. when read failed */
  25. struct fsl_ifc_ctrl;
  26. /* mtd information per set */
  27. struct fsl_ifc_mtd {
  28. struct nand_chip chip;
  29. struct fsl_ifc_ctrl *ctrl;
  30. struct device *dev;
  31. int bank; /* Chip select bank number */
  32. unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  33. u8 __iomem *vbase; /* Chip select base virtual address */
  34. };
  35. /* overview of the fsl ifc controller */
  36. struct fsl_ifc_ctrl {
  37. struct nand_hw_control controller;
  38. struct fsl_ifc_mtd *chips[MAX_BANKS];
  39. /* device info */
  40. struct fsl_ifc regs;
  41. void __iomem *addr; /* Address of assigned IFC buffer */
  42. unsigned int page; /* Last page written to / read from */
  43. unsigned int read_bytes; /* Number of bytes read during command */
  44. unsigned int column; /* Saved column from SEQIN */
  45. unsigned int index; /* Pointer to next byte to 'read' */
  46. unsigned int status; /* status read from NEESR after last op */
  47. unsigned int oob; /* Non zero if operating on OOB data */
  48. unsigned int eccread; /* Non zero for a full-page ECC read */
  49. };
  50. static struct fsl_ifc_ctrl *ifc_ctrl;
  51. /* 512-byte page with 4-bit ECC, 8-bit */
  52. static struct nand_ecclayout oob_512_8bit_ecc4 = {
  53. .eccbytes = 8,
  54. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  55. .oobfree = { {0, 5}, {6, 2} },
  56. };
  57. /* 512-byte page with 4-bit ECC, 16-bit */
  58. static struct nand_ecclayout oob_512_16bit_ecc4 = {
  59. .eccbytes = 8,
  60. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  61. .oobfree = { {2, 6}, },
  62. };
  63. /* 2048-byte page size with 4-bit ECC */
  64. static struct nand_ecclayout oob_2048_ecc4 = {
  65. .eccbytes = 32,
  66. .eccpos = {
  67. 8, 9, 10, 11, 12, 13, 14, 15,
  68. 16, 17, 18, 19, 20, 21, 22, 23,
  69. 24, 25, 26, 27, 28, 29, 30, 31,
  70. 32, 33, 34, 35, 36, 37, 38, 39,
  71. },
  72. .oobfree = { {2, 6}, {40, 24} },
  73. };
  74. /* 4096-byte page size with 4-bit ECC */
  75. static struct nand_ecclayout oob_4096_ecc4 = {
  76. .eccbytes = 64,
  77. .eccpos = {
  78. 8, 9, 10, 11, 12, 13, 14, 15,
  79. 16, 17, 18, 19, 20, 21, 22, 23,
  80. 24, 25, 26, 27, 28, 29, 30, 31,
  81. 32, 33, 34, 35, 36, 37, 38, 39,
  82. 40, 41, 42, 43, 44, 45, 46, 47,
  83. 48, 49, 50, 51, 52, 53, 54, 55,
  84. 56, 57, 58, 59, 60, 61, 62, 63,
  85. 64, 65, 66, 67, 68, 69, 70, 71,
  86. },
  87. .oobfree = { {2, 6}, {72, 56} },
  88. };
  89. /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
  90. static struct nand_ecclayout oob_4096_ecc8 = {
  91. .eccbytes = 128,
  92. .eccpos = {
  93. 8, 9, 10, 11, 12, 13, 14, 15,
  94. 16, 17, 18, 19, 20, 21, 22, 23,
  95. 24, 25, 26, 27, 28, 29, 30, 31,
  96. 32, 33, 34, 35, 36, 37, 38, 39,
  97. 40, 41, 42, 43, 44, 45, 46, 47,
  98. 48, 49, 50, 51, 52, 53, 54, 55,
  99. 56, 57, 58, 59, 60, 61, 62, 63,
  100. 64, 65, 66, 67, 68, 69, 70, 71,
  101. 72, 73, 74, 75, 76, 77, 78, 79,
  102. 80, 81, 82, 83, 84, 85, 86, 87,
  103. 88, 89, 90, 91, 92, 93, 94, 95,
  104. 96, 97, 98, 99, 100, 101, 102, 103,
  105. 104, 105, 106, 107, 108, 109, 110, 111,
  106. 112, 113, 114, 115, 116, 117, 118, 119,
  107. 120, 121, 122, 123, 124, 125, 126, 127,
  108. 128, 129, 130, 131, 132, 133, 134, 135,
  109. },
  110. .oobfree = { {2, 6}, {136, 82} },
  111. };
  112. /* 8192-byte page size with 4-bit ECC */
  113. static struct nand_ecclayout oob_8192_ecc4 = {
  114. .eccbytes = 128,
  115. .eccpos = {
  116. 8, 9, 10, 11, 12, 13, 14, 15,
  117. 16, 17, 18, 19, 20, 21, 22, 23,
  118. 24, 25, 26, 27, 28, 29, 30, 31,
  119. 32, 33, 34, 35, 36, 37, 38, 39,
  120. 40, 41, 42, 43, 44, 45, 46, 47,
  121. 48, 49, 50, 51, 52, 53, 54, 55,
  122. 56, 57, 58, 59, 60, 61, 62, 63,
  123. 64, 65, 66, 67, 68, 69, 70, 71,
  124. 72, 73, 74, 75, 76, 77, 78, 79,
  125. 80, 81, 82, 83, 84, 85, 86, 87,
  126. 88, 89, 90, 91, 92, 93, 94, 95,
  127. 96, 97, 98, 99, 100, 101, 102, 103,
  128. 104, 105, 106, 107, 108, 109, 110, 111,
  129. 112, 113, 114, 115, 116, 117, 118, 119,
  130. 120, 121, 122, 123, 124, 125, 126, 127,
  131. 128, 129, 130, 131, 132, 133, 134, 135,
  132. },
  133. .oobfree = { {2, 6}, {136, 208} },
  134. };
  135. /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
  136. static struct nand_ecclayout oob_8192_ecc8 = {
  137. .eccbytes = 256,
  138. .eccpos = {
  139. 8, 9, 10, 11, 12, 13, 14, 15,
  140. 16, 17, 18, 19, 20, 21, 22, 23,
  141. 24, 25, 26, 27, 28, 29, 30, 31,
  142. 32, 33, 34, 35, 36, 37, 38, 39,
  143. 40, 41, 42, 43, 44, 45, 46, 47,
  144. 48, 49, 50, 51, 52, 53, 54, 55,
  145. 56, 57, 58, 59, 60, 61, 62, 63,
  146. 64, 65, 66, 67, 68, 69, 70, 71,
  147. 72, 73, 74, 75, 76, 77, 78, 79,
  148. 80, 81, 82, 83, 84, 85, 86, 87,
  149. 88, 89, 90, 91, 92, 93, 94, 95,
  150. 96, 97, 98, 99, 100, 101, 102, 103,
  151. 104, 105, 106, 107, 108, 109, 110, 111,
  152. 112, 113, 114, 115, 116, 117, 118, 119,
  153. 120, 121, 122, 123, 124, 125, 126, 127,
  154. 128, 129, 130, 131, 132, 133, 134, 135,
  155. 136, 137, 138, 139, 140, 141, 142, 143,
  156. 144, 145, 146, 147, 148, 149, 150, 151,
  157. 152, 153, 154, 155, 156, 157, 158, 159,
  158. 160, 161, 162, 163, 164, 165, 166, 167,
  159. 168, 169, 170, 171, 172, 173, 174, 175,
  160. 176, 177, 178, 179, 180, 181, 182, 183,
  161. 184, 185, 186, 187, 188, 189, 190, 191,
  162. 192, 193, 194, 195, 196, 197, 198, 199,
  163. 200, 201, 202, 203, 204, 205, 206, 207,
  164. 208, 209, 210, 211, 212, 213, 214, 215,
  165. 216, 217, 218, 219, 220, 221, 222, 223,
  166. 224, 225, 226, 227, 228, 229, 230, 231,
  167. 232, 233, 234, 235, 236, 237, 238, 239,
  168. 240, 241, 242, 243, 244, 245, 246, 247,
  169. 248, 249, 250, 251, 252, 253, 254, 255,
  170. 256, 257, 258, 259, 260, 261, 262, 263,
  171. },
  172. .oobfree = { {2, 6}, {264, 80} },
  173. };
  174. /*
  175. * Generic flash bbt descriptors
  176. */
  177. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  178. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  179. static struct nand_bbt_descr bbt_main_descr = {
  180. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  181. NAND_BBT_2BIT | NAND_BBT_VERSION,
  182. .offs = 2, /* 0 on 8-bit small page */
  183. .len = 4,
  184. .veroffs = 6,
  185. .maxblocks = 4,
  186. .pattern = bbt_pattern,
  187. };
  188. static struct nand_bbt_descr bbt_mirror_descr = {
  189. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  190. NAND_BBT_2BIT | NAND_BBT_VERSION,
  191. .offs = 2, /* 0 on 8-bit small page */
  192. .len = 4,
  193. .veroffs = 6,
  194. .maxblocks = 4,
  195. .pattern = mirror_pattern,
  196. };
  197. /*
  198. * Set up the IFC hardware block and page address fields, and the ifc nand
  199. * structure addr field to point to the correct IFC buffer in memory
  200. */
  201. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  202. {
  203. struct nand_chip *chip = mtd_to_nand(mtd);
  204. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  205. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  206. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  207. int buf_num;
  208. ctrl->page = page_addr;
  209. /* Program ROW0/COL0 */
  210. ifc_out32(&ifc->ifc_nand.row0, page_addr);
  211. ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
  212. buf_num = page_addr & priv->bufnum_mask;
  213. ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
  214. ctrl->index = column;
  215. /* for OOB data point to the second half of the buffer */
  216. if (oob)
  217. ctrl->index += mtd->writesize;
  218. }
  219. /* returns nonzero if entire page is blank */
  220. static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  221. u32 eccstat, unsigned int bufnum)
  222. {
  223. return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
  224. }
  225. /*
  226. * execute IFC NAND command and wait for it to complete
  227. */
  228. static int fsl_ifc_run_command(struct mtd_info *mtd)
  229. {
  230. struct nand_chip *chip = mtd_to_nand(mtd);
  231. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  232. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  233. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  234. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  235. u32 time_start;
  236. u32 eccstat;
  237. int i;
  238. /* set the chip select for NAND Transaction */
  239. ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  240. /* start read/write seq */
  241. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  242. IFC_NAND_SEQ_STRT_FIR_STRT);
  243. /* wait for NAND Machine complete flag or timeout */
  244. time_start = get_timer(0);
  245. while (get_timer(time_start) < timeo) {
  246. ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  247. if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  248. break;
  249. }
  250. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
  251. if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
  252. printf("%s: Flash Time Out Error\n", __func__);
  253. if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
  254. printf("%s: Write Protect Error\n", __func__);
  255. if (ctrl->eccread) {
  256. int errors;
  257. int bufnum = ctrl->page & priv->bufnum_mask;
  258. int sector_start = bufnum * chip->ecc.steps;
  259. int sector_end = sector_start + chip->ecc.steps - 1;
  260. u32 *eccstat_regs;
  261. eccstat_regs = ifc->ifc_nand.nand_eccstat;
  262. eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
  263. for (i = sector_start; i <= sector_end; i++) {
  264. if ((i != sector_start) && !(i % 4))
  265. eccstat = ifc_in32(&eccstat_regs[i / 4]);
  266. errors = check_read_ecc(mtd, ctrl, eccstat, i);
  267. if (errors == 15) {
  268. /*
  269. * Uncorrectable error.
  270. * We'll check for blank pages later.
  271. *
  272. * We disable ECCER reporting due to erratum
  273. * IFC-A002770 -- so report it now if we
  274. * see an uncorrectable error in ECCSTAT.
  275. */
  276. ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
  277. continue;
  278. }
  279. mtd->ecc_stats.corrected += errors;
  280. }
  281. ctrl->eccread = 0;
  282. }
  283. /* returns 0 on success otherwise non-zero) */
  284. return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
  285. }
  286. static void fsl_ifc_do_read(struct nand_chip *chip,
  287. int oob,
  288. struct mtd_info *mtd)
  289. {
  290. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  291. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  292. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  293. /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
  294. if (mtd->writesize > 512) {
  295. ifc_out32(&ifc->ifc_nand.nand_fir0,
  296. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  297. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  298. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  299. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  300. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
  301. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  302. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  303. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  304. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  305. } else {
  306. ifc_out32(&ifc->ifc_nand.nand_fir0,
  307. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  308. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  309. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  310. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
  311. if (oob)
  312. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  313. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
  314. else
  315. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  316. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  317. }
  318. }
  319. /* cmdfunc send commands to the IFC NAND Machine */
  320. static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  321. int column, int page_addr)
  322. {
  323. struct nand_chip *chip = mtd_to_nand(mtd);
  324. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  325. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  326. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  327. /* clear the read buffer */
  328. ctrl->read_bytes = 0;
  329. if (command != NAND_CMD_PAGEPROG)
  330. ctrl->index = 0;
  331. switch (command) {
  332. /* READ0 read the entire buffer to use hardware ECC. */
  333. case NAND_CMD_READ0: {
  334. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  335. set_addr(mtd, 0, page_addr, 0);
  336. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  337. ctrl->index += column;
  338. if (chip->ecc.mode == NAND_ECC_HW)
  339. ctrl->eccread = 1;
  340. fsl_ifc_do_read(chip, 0, mtd);
  341. fsl_ifc_run_command(mtd);
  342. return;
  343. }
  344. /* READOOB reads only the OOB because no ECC is performed. */
  345. case NAND_CMD_READOOB:
  346. ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
  347. set_addr(mtd, column, page_addr, 1);
  348. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  349. fsl_ifc_do_read(chip, 1, mtd);
  350. fsl_ifc_run_command(mtd);
  351. return;
  352. /* READID must read all possible bytes while CEB is active */
  353. case NAND_CMD_READID:
  354. case NAND_CMD_PARAM: {
  355. int timing = IFC_FIR_OP_RB;
  356. if (command == NAND_CMD_PARAM)
  357. timing = IFC_FIR_OP_RBCD;
  358. ifc_out32(&ifc->ifc_nand.nand_fir0,
  359. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  360. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  361. (timing << IFC_NAND_FIR0_OP2_SHIFT));
  362. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  363. command << IFC_NAND_FCR0_CMD0_SHIFT);
  364. ifc_out32(&ifc->ifc_nand.row3, column);
  365. /*
  366. * although currently it's 8 bytes for READID, we always read
  367. * the maximum 256 bytes(for PARAM)
  368. */
  369. ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
  370. ctrl->read_bytes = 256;
  371. set_addr(mtd, 0, 0, 0);
  372. fsl_ifc_run_command(mtd);
  373. return;
  374. }
  375. /* ERASE1 stores the block and page address */
  376. case NAND_CMD_ERASE1:
  377. set_addr(mtd, 0, page_addr, 0);
  378. return;
  379. /* ERASE2 uses the block and page address from ERASE1 */
  380. case NAND_CMD_ERASE2:
  381. ifc_out32(&ifc->ifc_nand.nand_fir0,
  382. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  383. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  384. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
  385. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  386. (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  387. (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
  388. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  389. ctrl->read_bytes = 0;
  390. fsl_ifc_run_command(mtd);
  391. return;
  392. /* SEQIN sets up the addr buffer and all registers except the length */
  393. case NAND_CMD_SEQIN: {
  394. u32 nand_fcr0;
  395. ctrl->column = column;
  396. ctrl->oob = 0;
  397. if (mtd->writesize > 512) {
  398. nand_fcr0 =
  399. (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
  400. (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
  401. (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
  402. ifc_out32(&ifc->ifc_nand.nand_fir0,
  403. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  404. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  405. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  406. (IFC_FIR_OP_WBCD <<
  407. IFC_NAND_FIR0_OP3_SHIFT) |
  408. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
  409. ifc_out32(&ifc->ifc_nand.nand_fir1,
  410. (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
  411. (IFC_FIR_OP_RDSTAT <<
  412. IFC_NAND_FIR1_OP6_SHIFT) |
  413. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
  414. } else {
  415. nand_fcr0 = ((NAND_CMD_PAGEPROG <<
  416. IFC_NAND_FCR0_CMD1_SHIFT) |
  417. (NAND_CMD_SEQIN <<
  418. IFC_NAND_FCR0_CMD2_SHIFT) |
  419. (NAND_CMD_STATUS <<
  420. IFC_NAND_FCR0_CMD3_SHIFT));
  421. ifc_out32(&ifc->ifc_nand.nand_fir0,
  422. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  423. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  424. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  425. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  426. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
  427. ifc_out32(&ifc->ifc_nand.nand_fir1,
  428. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
  429. (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
  430. (IFC_FIR_OP_RDSTAT <<
  431. IFC_NAND_FIR1_OP7_SHIFT) |
  432. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
  433. if (column >= mtd->writesize)
  434. nand_fcr0 |=
  435. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
  436. else
  437. nand_fcr0 |=
  438. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
  439. }
  440. if (column >= mtd->writesize) {
  441. /* OOB area --> READOOB */
  442. column -= mtd->writesize;
  443. ctrl->oob = 1;
  444. }
  445. ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
  446. set_addr(mtd, column, page_addr, ctrl->oob);
  447. return;
  448. }
  449. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  450. case NAND_CMD_PAGEPROG:
  451. if (ctrl->oob)
  452. ifc_out32(&ifc->ifc_nand.nand_fbcr,
  453. ctrl->index - ctrl->column);
  454. else
  455. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  456. fsl_ifc_run_command(mtd);
  457. return;
  458. case NAND_CMD_STATUS:
  459. ifc_out32(&ifc->ifc_nand.nand_fir0,
  460. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  461. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
  462. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  463. NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
  464. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  465. set_addr(mtd, 0, 0, 0);
  466. ctrl->read_bytes = 1;
  467. fsl_ifc_run_command(mtd);
  468. /*
  469. * The chip always seems to report that it is
  470. * write-protected, even when it is not.
  471. */
  472. if (chip->options & NAND_BUSWIDTH_16)
  473. ifc_out16(ctrl->addr,
  474. ifc_in16(ctrl->addr) | NAND_STATUS_WP);
  475. else
  476. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  477. return;
  478. case NAND_CMD_RESET:
  479. ifc_out32(&ifc->ifc_nand.nand_fir0,
  480. IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
  481. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  482. NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
  483. fsl_ifc_run_command(mtd);
  484. return;
  485. default:
  486. printf("%s: error, unsupported command 0x%x.\n",
  487. __func__, command);
  488. }
  489. }
  490. /*
  491. * Write buf to the IFC NAND Controller Data Buffer
  492. */
  493. static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  494. {
  495. struct nand_chip *chip = mtd_to_nand(mtd);
  496. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  497. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  498. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  499. if (len <= 0) {
  500. printf("%s of %d bytes", __func__, len);
  501. ctrl->status = 0;
  502. return;
  503. }
  504. if ((unsigned int)len > bufsize - ctrl->index) {
  505. printf("%s beyond end of buffer "
  506. "(%d requested, %u available)\n",
  507. __func__, len, bufsize - ctrl->index);
  508. len = bufsize - ctrl->index;
  509. }
  510. memcpy_toio(ctrl->addr + ctrl->index, buf, len);
  511. ctrl->index += len;
  512. }
  513. /*
  514. * read a byte from either the IFC hardware buffer if it has any data left
  515. * otherwise issue a command to read a single byte.
  516. */
  517. static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
  518. {
  519. struct nand_chip *chip = mtd_to_nand(mtd);
  520. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  521. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  522. unsigned int offset;
  523. /*
  524. * If there are still bytes in the IFC buffer, then use the
  525. * next byte.
  526. */
  527. if (ctrl->index < ctrl->read_bytes) {
  528. offset = ctrl->index++;
  529. return in_8(ctrl->addr + offset);
  530. }
  531. printf("%s beyond end of buffer\n", __func__);
  532. return ERR_BYTE;
  533. }
  534. /*
  535. * Read two bytes from the IFC hardware buffer
  536. * read function for 16-bit buswith
  537. */
  538. static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  539. {
  540. struct nand_chip *chip = mtd_to_nand(mtd);
  541. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  542. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  543. uint16_t data;
  544. /*
  545. * If there are still bytes in the IFC buffer, then use the
  546. * next byte.
  547. */
  548. if (ctrl->index < ctrl->read_bytes) {
  549. data = ifc_in16(ctrl->addr + ctrl->index);
  550. ctrl->index += 2;
  551. return (uint8_t)data;
  552. }
  553. printf("%s beyond end of buffer\n", __func__);
  554. return ERR_BYTE;
  555. }
  556. /*
  557. * Read from the IFC Controller Data Buffer
  558. */
  559. static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  560. {
  561. struct nand_chip *chip = mtd_to_nand(mtd);
  562. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  563. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  564. int avail;
  565. if (len < 0)
  566. return;
  567. avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
  568. memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
  569. ctrl->index += avail;
  570. if (len > avail)
  571. printf("%s beyond end of buffer "
  572. "(%d requested, %d available)\n",
  573. __func__, len, avail);
  574. }
  575. /* This function is called after Program and Erase Operations to
  576. * check for success or failure.
  577. */
  578. static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  579. {
  580. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  581. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  582. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  583. u32 nand_fsr;
  584. int status;
  585. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  586. return NAND_STATUS_FAIL;
  587. /* Use READ_STATUS command, but wait for the device to be ready */
  588. ifc_out32(&ifc->ifc_nand.nand_fir0,
  589. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  590. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
  591. ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
  592. IFC_NAND_FCR0_CMD0_SHIFT);
  593. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  594. set_addr(mtd, 0, 0, 0);
  595. ctrl->read_bytes = 1;
  596. fsl_ifc_run_command(mtd);
  597. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  598. return NAND_STATUS_FAIL;
  599. nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
  600. status = nand_fsr >> 24;
  601. /* Chip sometimes reporting write protect even when it's not */
  602. return status | NAND_STATUS_WP;
  603. }
  604. /*
  605. * The controller does not check for bitflips in erased pages,
  606. * therefore software must check instead.
  607. */
  608. static int
  609. check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd)
  610. {
  611. u8 *ecc = chip->oob_poi;
  612. const int ecc_size = chip->ecc.bytes;
  613. const int pkt_size = chip->ecc.size;
  614. int i, res, bitflips;
  615. /* IFC starts ecc bytes at offset 8 in the spare area. */
  616. ecc += 8;
  617. bitflips = 0;
  618. for (i = 0; i < chip->ecc.steps; i++) {
  619. res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
  620. NULL, 0, chip->ecc.strength);
  621. if (res < 0) {
  622. printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n");
  623. mtd->ecc_stats.failed++;
  624. } else if (res > 0) {
  625. mtd->ecc_stats.corrected += res;
  626. }
  627. bitflips = max(res, bitflips);
  628. buf += pkt_size;
  629. ecc += ecc_size;
  630. }
  631. return bitflips;
  632. }
  633. static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  634. uint8_t *buf, int oob_required, int page)
  635. {
  636. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  637. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  638. fsl_ifc_read_buf(mtd, buf, mtd->writesize);
  639. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  640. if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER)
  641. return check_erased_page(chip, buf, mtd);
  642. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  643. mtd->ecc_stats.failed++;
  644. return 0;
  645. }
  646. /* ECC will be calculated automatically, and errors will be detected in
  647. * waitfunc.
  648. */
  649. static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  650. const uint8_t *buf, int oob_required, int page)
  651. {
  652. fsl_ifc_write_buf(mtd, buf, mtd->writesize);
  653. fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  654. return 0;
  655. }
  656. static void fsl_ifc_ctrl_init(void)
  657. {
  658. uint32_t ver = 0;
  659. ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
  660. if (!ifc_ctrl)
  661. return;
  662. ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
  663. ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
  664. if (ver >= FSL_IFC_V2_0_0)
  665. ifc_ctrl->regs.rregs =
  666. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  667. else
  668. ifc_ctrl->regs.rregs =
  669. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  670. /* clear event registers */
  671. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
  672. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
  673. /* Enable error and event for any detected errors */
  674. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
  675. IFC_NAND_EVTER_EN_OPC_EN |
  676. IFC_NAND_EVTER_EN_PGRDCMPL_EN |
  677. IFC_NAND_EVTER_EN_FTOER_EN |
  678. IFC_NAND_EVTER_EN_WPER_EN);
  679. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
  680. }
  681. static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  682. {
  683. }
  684. static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
  685. {
  686. struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
  687. uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
  688. uint32_t ncfgr = 0;
  689. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  690. u32 time_start;
  691. if (ver > FSL_IFC_V1_1_0) {
  692. ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
  693. ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
  694. /* wait for SRAM_INIT bit to be clear or timeout */
  695. time_start = get_timer(0);
  696. while (get_timer(time_start) < timeo) {
  697. ifc_ctrl->status =
  698. ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  699. if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
  700. return 0;
  701. }
  702. printf("fsl-ifc: Failed to Initialise SRAM\n");
  703. return 1;
  704. }
  705. cs = priv->bank;
  706. /* Save CSOR and CSOR_ext */
  707. csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
  708. csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
  709. /* chage PageSize 8K and SpareSize 1K*/
  710. csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
  711. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
  712. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
  713. /* READID */
  714. ifc_out32(&ifc->ifc_nand.nand_fir0,
  715. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  716. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  717. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
  718. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  719. NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
  720. ifc_out32(&ifc->ifc_nand.row3, 0x0);
  721. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
  722. /* Program ROW0/COL0 */
  723. ifc_out32(&ifc->ifc_nand.row0, 0x0);
  724. ifc_out32(&ifc->ifc_nand.col0, 0x0);
  725. /* set the chip select for NAND Transaction */
  726. ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  727. /* start read seq */
  728. ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  729. time_start = get_timer(0);
  730. while (get_timer(time_start) < timeo) {
  731. ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  732. if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  733. break;
  734. }
  735. if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
  736. printf("fsl-ifc: Failed to Initialise SRAM\n");
  737. return 1;
  738. }
  739. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
  740. /* Restore CSOR and CSOR_ext */
  741. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
  742. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
  743. return 0;
  744. }
  745. static int fsl_ifc_chip_init(int devnum, u8 *addr)
  746. {
  747. struct mtd_info *mtd;
  748. struct nand_chip *nand;
  749. struct fsl_ifc_mtd *priv;
  750. struct nand_ecclayout *layout;
  751. struct fsl_ifc_fcm *gregs = NULL;
  752. uint32_t cspr = 0, csor = 0, ver = 0;
  753. int ret = 0;
  754. if (!ifc_ctrl) {
  755. fsl_ifc_ctrl_init();
  756. if (!ifc_ctrl)
  757. return -1;
  758. }
  759. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  760. if (!priv)
  761. return -ENOMEM;
  762. priv->ctrl = ifc_ctrl;
  763. priv->vbase = addr;
  764. gregs = ifc_ctrl->regs.gregs;
  765. /* Find which chip select it is connected to.
  766. */
  767. for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
  768. phys_addr_t phys_addr = virt_to_phys(addr);
  769. cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
  770. csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
  771. if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
  772. (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
  773. break;
  774. }
  775. if (priv->bank >= MAX_BANKS) {
  776. printf("%s: address did not match any "
  777. "chip selects\n", __func__);
  778. kfree(priv);
  779. return -ENODEV;
  780. }
  781. nand = &priv->chip;
  782. mtd = nand_to_mtd(nand);
  783. ifc_ctrl->chips[priv->bank] = priv;
  784. /* fill in nand_chip structure */
  785. /* set up function call table */
  786. nand->write_buf = fsl_ifc_write_buf;
  787. nand->read_buf = fsl_ifc_read_buf;
  788. nand->select_chip = fsl_ifc_select_chip;
  789. nand->cmdfunc = fsl_ifc_cmdfunc;
  790. nand->waitfunc = fsl_ifc_wait;
  791. /* set up nand options */
  792. nand->bbt_td = &bbt_main_descr;
  793. nand->bbt_md = &bbt_mirror_descr;
  794. /* set up nand options */
  795. nand->options = NAND_NO_SUBPAGE_WRITE;
  796. nand->bbt_options = NAND_BBT_USE_FLASH;
  797. if (cspr & CSPR_PORT_SIZE_16) {
  798. nand->read_byte = fsl_ifc_read_byte16;
  799. nand->options |= NAND_BUSWIDTH_16;
  800. } else {
  801. nand->read_byte = fsl_ifc_read_byte;
  802. }
  803. nand->controller = &ifc_ctrl->controller;
  804. nand_set_controller_data(nand, priv);
  805. nand->ecc.read_page = fsl_ifc_read_page;
  806. nand->ecc.write_page = fsl_ifc_write_page;
  807. /* Hardware generates ECC per 512 Bytes */
  808. nand->ecc.size = 512;
  809. nand->ecc.bytes = 8;
  810. switch (csor & CSOR_NAND_PGS_MASK) {
  811. case CSOR_NAND_PGS_512:
  812. if (nand->options & NAND_BUSWIDTH_16) {
  813. layout = &oob_512_16bit_ecc4;
  814. } else {
  815. layout = &oob_512_8bit_ecc4;
  816. /* Avoid conflict with bad block marker */
  817. bbt_main_descr.offs = 0;
  818. bbt_mirror_descr.offs = 0;
  819. }
  820. nand->ecc.strength = 4;
  821. priv->bufnum_mask = 15;
  822. break;
  823. case CSOR_NAND_PGS_2K:
  824. layout = &oob_2048_ecc4;
  825. nand->ecc.strength = 4;
  826. priv->bufnum_mask = 3;
  827. break;
  828. case CSOR_NAND_PGS_4K:
  829. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  830. CSOR_NAND_ECC_MODE_4) {
  831. layout = &oob_4096_ecc4;
  832. nand->ecc.strength = 4;
  833. } else {
  834. layout = &oob_4096_ecc8;
  835. nand->ecc.strength = 8;
  836. nand->ecc.bytes = 16;
  837. }
  838. priv->bufnum_mask = 1;
  839. break;
  840. case CSOR_NAND_PGS_8K:
  841. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  842. CSOR_NAND_ECC_MODE_4) {
  843. layout = &oob_8192_ecc4;
  844. nand->ecc.strength = 4;
  845. } else {
  846. layout = &oob_8192_ecc8;
  847. nand->ecc.strength = 8;
  848. nand->ecc.bytes = 16;
  849. }
  850. priv->bufnum_mask = 0;
  851. break;
  852. default:
  853. printf("ifc nand: bad csor %#x: bad page size\n", csor);
  854. return -ENODEV;
  855. }
  856. /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
  857. if (csor & CSOR_NAND_ECC_DEC_EN) {
  858. nand->ecc.mode = NAND_ECC_HW;
  859. nand->ecc.layout = layout;
  860. } else {
  861. nand->ecc.mode = NAND_ECC_SOFT;
  862. }
  863. ver = ifc_in32(&gregs->ifc_rev);
  864. if (ver >= FSL_IFC_V1_1_0)
  865. ret = fsl_ifc_sram_init(priv, ver);
  866. if (ret)
  867. return ret;
  868. if (ver >= FSL_IFC_V2_0_0)
  869. priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
  870. ret = nand_scan_ident(mtd, 1, NULL);
  871. if (ret)
  872. return ret;
  873. ret = nand_scan_tail(mtd);
  874. if (ret)
  875. return ret;
  876. ret = nand_register(devnum, mtd);
  877. if (ret)
  878. return ret;
  879. return 0;
  880. }
  881. #ifndef CONFIG_SYS_NAND_BASE_LIST
  882. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  883. #endif
  884. static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
  885. CONFIG_SYS_NAND_BASE_LIST;
  886. void board_nand_init(void)
  887. {
  888. int i;
  889. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  890. fsl_ifc_chip_init(i, (u8 *)base_address[i]);
  891. }