denali.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Panasonic Corporation
  4. * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
  5. * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
  6. */
  7. #include <asm/dma-mapping.h>
  8. #include <dm.h>
  9. #include <nand.h>
  10. #include <dm/devres.h>
  11. #include <linux/bitfield.h>
  12. #include <linux/dma-direction.h>
  13. #include <linux/err.h>
  14. #include <linux/errno.h>
  15. #include <linux/io.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/rawnand.h>
  18. #include "denali.h"
  19. #define DENALI_NAND_NAME "denali-nand"
  20. /* for Indexed Addressing */
  21. #define DENALI_INDEXED_CTRL 0x00
  22. #define DENALI_INDEXED_DATA 0x10
  23. #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
  24. #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
  25. #define DENALI_MAP10 (2 << 26) /* high-level control plane */
  26. #define DENALI_MAP11 (3 << 26) /* direct controller access */
  27. /* MAP11 access cycle type */
  28. #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
  29. #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
  30. #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
  31. /* MAP10 commands */
  32. #define DENALI_ERASE 0x01
  33. #define DENALI_BANK(denali) ((denali)->active_bank << 24)
  34. #define DENALI_INVALID_BANK -1
  35. #define DENALI_NR_BANKS 4
  36. static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
  37. {
  38. return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
  39. }
  40. /*
  41. * Direct Addressing - the slave address forms the control information (command
  42. * type, bank, block, and page address). The slave data is the actual data to
  43. * be transferred. This mode requires 28 bits of address region allocated.
  44. */
  45. static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
  46. {
  47. return ioread32(denali->host + addr);
  48. }
  49. static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
  50. u32 data)
  51. {
  52. iowrite32(data, denali->host + addr);
  53. }
  54. /*
  55. * Indexed Addressing - address translation module intervenes in passing the
  56. * control information. This mode reduces the required address range. The
  57. * control information and transferred data are latched by the registers in
  58. * the translation module.
  59. */
  60. static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
  61. {
  62. iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
  63. return ioread32(denali->host + DENALI_INDEXED_DATA);
  64. }
  65. static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
  66. u32 data)
  67. {
  68. iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
  69. iowrite32(data, denali->host + DENALI_INDEXED_DATA);
  70. }
  71. /*
  72. * Use the configuration feature register to determine the maximum number of
  73. * banks that the hardware supports.
  74. */
  75. static void denali_detect_max_banks(struct denali_nand_info *denali)
  76. {
  77. uint32_t features = ioread32(denali->reg + FEATURES);
  78. denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
  79. /* the encoding changed from rev 5.0 to 5.1 */
  80. if (denali->revision < 0x0501)
  81. denali->max_banks <<= 1;
  82. }
  83. static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
  84. {
  85. int i;
  86. for (i = 0; i < DENALI_NR_BANKS; i++)
  87. iowrite32(U32_MAX, denali->reg + INTR_EN(i));
  88. iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
  89. }
  90. static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
  91. {
  92. int i;
  93. for (i = 0; i < DENALI_NR_BANKS; i++)
  94. iowrite32(0, denali->reg + INTR_EN(i));
  95. iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
  96. }
  97. static void denali_clear_irq(struct denali_nand_info *denali,
  98. int bank, uint32_t irq_status)
  99. {
  100. /* write one to clear bits */
  101. iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
  102. }
  103. static void denali_clear_irq_all(struct denali_nand_info *denali)
  104. {
  105. int i;
  106. for (i = 0; i < DENALI_NR_BANKS; i++)
  107. denali_clear_irq(denali, i, U32_MAX);
  108. }
  109. static void __denali_check_irq(struct denali_nand_info *denali)
  110. {
  111. uint32_t irq_status;
  112. int i;
  113. for (i = 0; i < DENALI_NR_BANKS; i++) {
  114. irq_status = ioread32(denali->reg + INTR_STATUS(i));
  115. denali_clear_irq(denali, i, irq_status);
  116. if (i != denali->active_bank)
  117. continue;
  118. denali->irq_status |= irq_status;
  119. }
  120. }
  121. static void denali_reset_irq(struct denali_nand_info *denali)
  122. {
  123. denali->irq_status = 0;
  124. denali->irq_mask = 0;
  125. }
  126. static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
  127. uint32_t irq_mask)
  128. {
  129. unsigned long time_left = 1000000;
  130. while (time_left) {
  131. __denali_check_irq(denali);
  132. if (irq_mask & denali->irq_status)
  133. return denali->irq_status;
  134. udelay(1);
  135. time_left--;
  136. }
  137. if (!time_left) {
  138. dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
  139. irq_mask);
  140. return 0;
  141. }
  142. return denali->irq_status;
  143. }
  144. static uint32_t denali_check_irq(struct denali_nand_info *denali)
  145. {
  146. __denali_check_irq(denali);
  147. return denali->irq_status;
  148. }
  149. static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  150. {
  151. struct denali_nand_info *denali = mtd_to_denali(mtd);
  152. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  153. int i;
  154. for (i = 0; i < len; i++)
  155. buf[i] = denali->host_read(denali, addr);
  156. }
  157. static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  158. {
  159. struct denali_nand_info *denali = mtd_to_denali(mtd);
  160. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  161. int i;
  162. for (i = 0; i < len; i++)
  163. denali->host_write(denali, addr, buf[i]);
  164. }
  165. static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  166. {
  167. struct denali_nand_info *denali = mtd_to_denali(mtd);
  168. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  169. uint16_t *buf16 = (uint16_t *)buf;
  170. int i;
  171. for (i = 0; i < len / 2; i++)
  172. buf16[i] = denali->host_read(denali, addr);
  173. }
  174. static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
  175. int len)
  176. {
  177. struct denali_nand_info *denali = mtd_to_denali(mtd);
  178. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  179. const uint16_t *buf16 = (const uint16_t *)buf;
  180. int i;
  181. for (i = 0; i < len / 2; i++)
  182. denali->host_write(denali, addr, buf16[i]);
  183. }
  184. static uint8_t denali_read_byte(struct mtd_info *mtd)
  185. {
  186. uint8_t byte;
  187. denali_read_buf(mtd, &byte, 1);
  188. return byte;
  189. }
  190. static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
  191. {
  192. denali_write_buf(mtd, &byte, 1);
  193. }
  194. static uint16_t denali_read_word(struct mtd_info *mtd)
  195. {
  196. uint16_t word;
  197. denali_read_buf16(mtd, (uint8_t *)&word, 2);
  198. return word;
  199. }
  200. static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
  201. {
  202. struct denali_nand_info *denali = mtd_to_denali(mtd);
  203. uint32_t type;
  204. if (ctrl & NAND_CLE)
  205. type = DENALI_MAP11_CMD;
  206. else if (ctrl & NAND_ALE)
  207. type = DENALI_MAP11_ADDR;
  208. else
  209. return;
  210. /*
  211. * Some commands are followed by chip->dev_ready or chip->waitfunc.
  212. * irq_status must be cleared here to catch the R/B# interrupt later.
  213. */
  214. if (ctrl & NAND_CTRL_CHANGE)
  215. denali_reset_irq(denali);
  216. denali->host_write(denali, DENALI_BANK(denali) | type, dat);
  217. }
  218. static int denali_dev_ready(struct mtd_info *mtd)
  219. {
  220. struct denali_nand_info *denali = mtd_to_denali(mtd);
  221. return !!(denali_check_irq(denali) & INTR__INT_ACT);
  222. }
  223. static int denali_check_erased_page(struct mtd_info *mtd,
  224. struct nand_chip *chip, uint8_t *buf,
  225. unsigned long uncor_ecc_flags,
  226. unsigned int max_bitflips)
  227. {
  228. uint8_t *ecc_code = chip->buffers->ecccode;
  229. int ecc_steps = chip->ecc.steps;
  230. int ecc_size = chip->ecc.size;
  231. int ecc_bytes = chip->ecc.bytes;
  232. int i, ret, stat;
  233. ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
  234. chip->ecc.total);
  235. if (ret)
  236. return ret;
  237. for (i = 0; i < ecc_steps; i++) {
  238. if (!(uncor_ecc_flags & BIT(i)))
  239. continue;
  240. stat = nand_check_erased_ecc_chunk(buf, ecc_size,
  241. ecc_code, ecc_bytes,
  242. NULL, 0,
  243. chip->ecc.strength);
  244. if (stat < 0) {
  245. mtd->ecc_stats.failed++;
  246. } else {
  247. mtd->ecc_stats.corrected += stat;
  248. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  249. }
  250. buf += ecc_size;
  251. ecc_code += ecc_bytes;
  252. }
  253. return max_bitflips;
  254. }
  255. static int denali_hw_ecc_fixup(struct mtd_info *mtd,
  256. struct denali_nand_info *denali,
  257. unsigned long *uncor_ecc_flags)
  258. {
  259. struct nand_chip *chip = mtd_to_nand(mtd);
  260. int bank = denali->active_bank;
  261. uint32_t ecc_cor;
  262. unsigned int max_bitflips;
  263. ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
  264. ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
  265. if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
  266. /*
  267. * This flag is set when uncorrectable error occurs at least in
  268. * one ECC sector. We can not know "how many sectors", or
  269. * "which sector(s)". We need erase-page check for all sectors.
  270. */
  271. *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
  272. return 0;
  273. }
  274. max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
  275. /*
  276. * The register holds the maximum of per-sector corrected bitflips.
  277. * This is suitable for the return value of the ->read_page() callback.
  278. * Unfortunately, we can not know the total number of corrected bits in
  279. * the page. Increase the stats by max_bitflips. (compromised solution)
  280. */
  281. mtd->ecc_stats.corrected += max_bitflips;
  282. return max_bitflips;
  283. }
  284. static int denali_sw_ecc_fixup(struct mtd_info *mtd,
  285. struct denali_nand_info *denali,
  286. unsigned long *uncor_ecc_flags, uint8_t *buf)
  287. {
  288. unsigned int ecc_size = denali->nand.ecc.size;
  289. unsigned int bitflips = 0;
  290. unsigned int max_bitflips = 0;
  291. uint32_t err_addr, err_cor_info;
  292. unsigned int err_byte, err_sector, err_device;
  293. uint8_t err_cor_value;
  294. unsigned int prev_sector = 0;
  295. uint32_t irq_status;
  296. denali_reset_irq(denali);
  297. do {
  298. err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
  299. err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
  300. err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
  301. err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
  302. err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
  303. err_cor_info);
  304. err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
  305. err_cor_info);
  306. /* reset the bitflip counter when crossing ECC sector */
  307. if (err_sector != prev_sector)
  308. bitflips = 0;
  309. if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
  310. /*
  311. * Check later if this is a real ECC error, or
  312. * an erased sector.
  313. */
  314. *uncor_ecc_flags |= BIT(err_sector);
  315. } else if (err_byte < ecc_size) {
  316. /*
  317. * If err_byte is larger than ecc_size, means error
  318. * happened in OOB, so we ignore it. It's no need for
  319. * us to correct it err_device is represented the NAND
  320. * error bits are happened in if there are more than
  321. * one NAND connected.
  322. */
  323. int offset;
  324. unsigned int flips_in_byte;
  325. offset = (err_sector * ecc_size + err_byte) *
  326. denali->devs_per_cs + err_device;
  327. /* correct the ECC error */
  328. flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
  329. buf[offset] ^= err_cor_value;
  330. mtd->ecc_stats.corrected += flips_in_byte;
  331. bitflips += flips_in_byte;
  332. max_bitflips = max(max_bitflips, bitflips);
  333. }
  334. prev_sector = err_sector;
  335. } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
  336. /*
  337. * Once handle all ECC errors, controller will trigger an
  338. * ECC_TRANSACTION_DONE interrupt.
  339. */
  340. irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
  341. if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
  342. return -EIO;
  343. return max_bitflips;
  344. }
  345. static void denali_setup_dma64(struct denali_nand_info *denali,
  346. dma_addr_t dma_addr, int page, int write)
  347. {
  348. uint32_t mode;
  349. const int page_count = 1;
  350. mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
  351. /* DMA is a three step process */
  352. /*
  353. * 1. setup transfer type, interrupt when complete,
  354. * burst len = 64 bytes, the number of pages
  355. */
  356. denali->host_write(denali, mode,
  357. 0x01002000 | (64 << 16) | (write << 8) | page_count);
  358. /* 2. set memory low address */
  359. denali->host_write(denali, mode, lower_32_bits(dma_addr));
  360. /* 3. set memory high address */
  361. denali->host_write(denali, mode, upper_32_bits(dma_addr));
  362. }
  363. static void denali_setup_dma32(struct denali_nand_info *denali,
  364. dma_addr_t dma_addr, int page, int write)
  365. {
  366. uint32_t mode;
  367. const int page_count = 1;
  368. mode = DENALI_MAP10 | DENALI_BANK(denali);
  369. /* DMA is a four step process */
  370. /* 1. setup transfer type and # of pages */
  371. denali->host_write(denali, mode | page,
  372. 0x2000 | (write << 8) | page_count);
  373. /* 2. set memory high address bits 23:8 */
  374. denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
  375. /* 3. set memory low address bits 23:8 */
  376. denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
  377. /* 4. interrupt when complete, burst len = 64 bytes */
  378. denali->host_write(denali, mode | 0x14000, 0x2400);
  379. }
  380. static int denali_pio_read(struct denali_nand_info *denali, void *buf,
  381. size_t size, int page, int raw)
  382. {
  383. u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
  384. uint32_t *buf32 = (uint32_t *)buf;
  385. uint32_t irq_status, ecc_err_mask;
  386. int i;
  387. if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
  388. ecc_err_mask = INTR__ECC_UNCOR_ERR;
  389. else
  390. ecc_err_mask = INTR__ECC_ERR;
  391. denali_reset_irq(denali);
  392. for (i = 0; i < size / 4; i++)
  393. *buf32++ = denali->host_read(denali, addr);
  394. irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
  395. if (!(irq_status & INTR__PAGE_XFER_INC))
  396. return -EIO;
  397. if (irq_status & INTR__ERASED_PAGE)
  398. memset(buf, 0xff, size);
  399. return irq_status & ecc_err_mask ? -EBADMSG : 0;
  400. }
  401. static int denali_pio_write(struct denali_nand_info *denali,
  402. const void *buf, size_t size, int page, int raw)
  403. {
  404. u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
  405. const uint32_t *buf32 = (uint32_t *)buf;
  406. uint32_t irq_status;
  407. int i;
  408. denali_reset_irq(denali);
  409. for (i = 0; i < size / 4; i++)
  410. denali->host_write(denali, addr, *buf32++);
  411. irq_status = denali_wait_for_irq(denali,
  412. INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
  413. if (!(irq_status & INTR__PROGRAM_COMP))
  414. return -EIO;
  415. return 0;
  416. }
  417. static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
  418. size_t size, int page, int raw, int write)
  419. {
  420. if (write)
  421. return denali_pio_write(denali, buf, size, page, raw);
  422. else
  423. return denali_pio_read(denali, buf, size, page, raw);
  424. }
  425. static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
  426. size_t size, int page, int raw, int write)
  427. {
  428. dma_addr_t dma_addr;
  429. uint32_t irq_mask, irq_status, ecc_err_mask;
  430. enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  431. int ret = 0;
  432. dma_addr = dma_map_single(buf, size, dir);
  433. if (dma_mapping_error(denali->dev, dma_addr)) {
  434. dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
  435. return denali_pio_xfer(denali, buf, size, page, raw, write);
  436. }
  437. if (write) {
  438. /*
  439. * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
  440. * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
  441. * when the page program is completed.
  442. */
  443. irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
  444. ecc_err_mask = 0;
  445. } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
  446. irq_mask = INTR__DMA_CMD_COMP;
  447. ecc_err_mask = INTR__ECC_UNCOR_ERR;
  448. } else {
  449. irq_mask = INTR__DMA_CMD_COMP;
  450. ecc_err_mask = INTR__ECC_ERR;
  451. }
  452. iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
  453. /*
  454. * The ->setup_dma() hook kicks DMA by using the data/command
  455. * interface, which belongs to a different AXI port from the
  456. * register interface. Read back the register to avoid a race.
  457. */
  458. ioread32(denali->reg + DMA_ENABLE);
  459. denali_reset_irq(denali);
  460. denali->setup_dma(denali, dma_addr, page, write);
  461. irq_status = denali_wait_for_irq(denali, irq_mask);
  462. if (!(irq_status & INTR__DMA_CMD_COMP))
  463. ret = -EIO;
  464. else if (irq_status & ecc_err_mask)
  465. ret = -EBADMSG;
  466. iowrite32(0, denali->reg + DMA_ENABLE);
  467. dma_unmap_single(buf, size, dir);
  468. if (irq_status & INTR__ERASED_PAGE)
  469. memset(buf, 0xff, size);
  470. return ret;
  471. }
  472. static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
  473. size_t size, int page, int raw, int write)
  474. {
  475. iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
  476. iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
  477. denali->reg + TRANSFER_SPARE_REG);
  478. if (denali->dma_avail)
  479. return denali_dma_xfer(denali, buf, size, page, raw, write);
  480. else
  481. return denali_pio_xfer(denali, buf, size, page, raw, write);
  482. }
  483. static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
  484. int page, int write)
  485. {
  486. struct denali_nand_info *denali = mtd_to_denali(mtd);
  487. unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
  488. unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
  489. int writesize = mtd->writesize;
  490. int oobsize = mtd->oobsize;
  491. uint8_t *bufpoi = chip->oob_poi;
  492. int ecc_steps = chip->ecc.steps;
  493. int ecc_size = chip->ecc.size;
  494. int ecc_bytes = chip->ecc.bytes;
  495. int oob_skip = denali->oob_skip_bytes;
  496. size_t size = writesize + oobsize;
  497. int i, pos, len;
  498. /* BBM at the beginning of the OOB area */
  499. chip->cmdfunc(mtd, start_cmd, writesize, page);
  500. if (write)
  501. chip->write_buf(mtd, bufpoi, oob_skip);
  502. else
  503. chip->read_buf(mtd, bufpoi, oob_skip);
  504. bufpoi += oob_skip;
  505. /* OOB ECC */
  506. for (i = 0; i < ecc_steps; i++) {
  507. pos = ecc_size + i * (ecc_size + ecc_bytes);
  508. len = ecc_bytes;
  509. if (pos >= writesize)
  510. pos += oob_skip;
  511. else if (pos + len > writesize)
  512. len = writesize - pos;
  513. chip->cmdfunc(mtd, rnd_cmd, pos, -1);
  514. if (write)
  515. chip->write_buf(mtd, bufpoi, len);
  516. else
  517. chip->read_buf(mtd, bufpoi, len);
  518. bufpoi += len;
  519. if (len < ecc_bytes) {
  520. len = ecc_bytes - len;
  521. chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
  522. if (write)
  523. chip->write_buf(mtd, bufpoi, len);
  524. else
  525. chip->read_buf(mtd, bufpoi, len);
  526. bufpoi += len;
  527. }
  528. }
  529. /* OOB free */
  530. len = oobsize - (bufpoi - chip->oob_poi);
  531. chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
  532. if (write)
  533. chip->write_buf(mtd, bufpoi, len);
  534. else
  535. chip->read_buf(mtd, bufpoi, len);
  536. }
  537. static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  538. uint8_t *buf, int oob_required, int page)
  539. {
  540. struct denali_nand_info *denali = mtd_to_denali(mtd);
  541. int writesize = mtd->writesize;
  542. int oobsize = mtd->oobsize;
  543. int ecc_steps = chip->ecc.steps;
  544. int ecc_size = chip->ecc.size;
  545. int ecc_bytes = chip->ecc.bytes;
  546. void *tmp_buf = denali->buf;
  547. int oob_skip = denali->oob_skip_bytes;
  548. size_t size = writesize + oobsize;
  549. int ret, i, pos, len;
  550. ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
  551. if (ret)
  552. return ret;
  553. /* Arrange the buffer for syndrome payload/ecc layout */
  554. if (buf) {
  555. for (i = 0; i < ecc_steps; i++) {
  556. pos = i * (ecc_size + ecc_bytes);
  557. len = ecc_size;
  558. if (pos >= writesize)
  559. pos += oob_skip;
  560. else if (pos + len > writesize)
  561. len = writesize - pos;
  562. memcpy(buf, tmp_buf + pos, len);
  563. buf += len;
  564. if (len < ecc_size) {
  565. len = ecc_size - len;
  566. memcpy(buf, tmp_buf + writesize + oob_skip,
  567. len);
  568. buf += len;
  569. }
  570. }
  571. }
  572. if (oob_required) {
  573. uint8_t *oob = chip->oob_poi;
  574. /* BBM at the beginning of the OOB area */
  575. memcpy(oob, tmp_buf + writesize, oob_skip);
  576. oob += oob_skip;
  577. /* OOB ECC */
  578. for (i = 0; i < ecc_steps; i++) {
  579. pos = ecc_size + i * (ecc_size + ecc_bytes);
  580. len = ecc_bytes;
  581. if (pos >= writesize)
  582. pos += oob_skip;
  583. else if (pos + len > writesize)
  584. len = writesize - pos;
  585. memcpy(oob, tmp_buf + pos, len);
  586. oob += len;
  587. if (len < ecc_bytes) {
  588. len = ecc_bytes - len;
  589. memcpy(oob, tmp_buf + writesize + oob_skip,
  590. len);
  591. oob += len;
  592. }
  593. }
  594. /* OOB free */
  595. len = oobsize - (oob - chip->oob_poi);
  596. memcpy(oob, tmp_buf + size - len, len);
  597. }
  598. return 0;
  599. }
  600. static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  601. int page)
  602. {
  603. denali_oob_xfer(mtd, chip, page, 0);
  604. return 0;
  605. }
  606. static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  607. int page)
  608. {
  609. struct denali_nand_info *denali = mtd_to_denali(mtd);
  610. int status;
  611. denali_reset_irq(denali);
  612. denali_oob_xfer(mtd, chip, page, 1);
  613. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  614. status = chip->waitfunc(mtd, chip);
  615. return status & NAND_STATUS_FAIL ? -EIO : 0;
  616. }
  617. static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  618. uint8_t *buf, int oob_required, int page)
  619. {
  620. struct denali_nand_info *denali = mtd_to_denali(mtd);
  621. unsigned long uncor_ecc_flags = 0;
  622. int stat = 0;
  623. int ret;
  624. ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
  625. if (ret && ret != -EBADMSG)
  626. return ret;
  627. if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
  628. stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
  629. else if (ret == -EBADMSG)
  630. stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
  631. if (stat < 0)
  632. return stat;
  633. if (uncor_ecc_flags) {
  634. ret = denali_read_oob(mtd, chip, page);
  635. if (ret)
  636. return ret;
  637. stat = denali_check_erased_page(mtd, chip, buf,
  638. uncor_ecc_flags, stat);
  639. }
  640. return stat;
  641. }
  642. static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  643. const uint8_t *buf, int oob_required, int page)
  644. {
  645. struct denali_nand_info *denali = mtd_to_denali(mtd);
  646. int writesize = mtd->writesize;
  647. int oobsize = mtd->oobsize;
  648. int ecc_steps = chip->ecc.steps;
  649. int ecc_size = chip->ecc.size;
  650. int ecc_bytes = chip->ecc.bytes;
  651. void *tmp_buf = denali->buf;
  652. int oob_skip = denali->oob_skip_bytes;
  653. size_t size = writesize + oobsize;
  654. int i, pos, len;
  655. /*
  656. * Fill the buffer with 0xff first except the full page transfer.
  657. * This simplifies the logic.
  658. */
  659. if (!buf || !oob_required)
  660. memset(tmp_buf, 0xff, size);
  661. /* Arrange the buffer for syndrome payload/ecc layout */
  662. if (buf) {
  663. for (i = 0; i < ecc_steps; i++) {
  664. pos = i * (ecc_size + ecc_bytes);
  665. len = ecc_size;
  666. if (pos >= writesize)
  667. pos += oob_skip;
  668. else if (pos + len > writesize)
  669. len = writesize - pos;
  670. memcpy(tmp_buf + pos, buf, len);
  671. buf += len;
  672. if (len < ecc_size) {
  673. len = ecc_size - len;
  674. memcpy(tmp_buf + writesize + oob_skip, buf,
  675. len);
  676. buf += len;
  677. }
  678. }
  679. }
  680. if (oob_required) {
  681. const uint8_t *oob = chip->oob_poi;
  682. /* BBM at the beginning of the OOB area */
  683. memcpy(tmp_buf + writesize, oob, oob_skip);
  684. oob += oob_skip;
  685. /* OOB ECC */
  686. for (i = 0; i < ecc_steps; i++) {
  687. pos = ecc_size + i * (ecc_size + ecc_bytes);
  688. len = ecc_bytes;
  689. if (pos >= writesize)
  690. pos += oob_skip;
  691. else if (pos + len > writesize)
  692. len = writesize - pos;
  693. memcpy(tmp_buf + pos, oob, len);
  694. oob += len;
  695. if (len < ecc_bytes) {
  696. len = ecc_bytes - len;
  697. memcpy(tmp_buf + writesize + oob_skip, oob,
  698. len);
  699. oob += len;
  700. }
  701. }
  702. /* OOB free */
  703. len = oobsize - (oob - chip->oob_poi);
  704. memcpy(tmp_buf + size - len, oob, len);
  705. }
  706. return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
  707. }
  708. static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  709. const uint8_t *buf, int oob_required, int page)
  710. {
  711. struct denali_nand_info *denali = mtd_to_denali(mtd);
  712. return denali_data_xfer(denali, (void *)buf, mtd->writesize,
  713. page, 0, 1);
  714. }
  715. static void denali_select_chip(struct mtd_info *mtd, int chip)
  716. {
  717. struct denali_nand_info *denali = mtd_to_denali(mtd);
  718. denali->active_bank = chip;
  719. }
  720. static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
  721. {
  722. struct denali_nand_info *denali = mtd_to_denali(mtd);
  723. uint32_t irq_status;
  724. /* R/B# pin transitioned from low to high? */
  725. irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
  726. return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
  727. }
  728. static int denali_erase(struct mtd_info *mtd, int page)
  729. {
  730. struct denali_nand_info *denali = mtd_to_denali(mtd);
  731. uint32_t irq_status;
  732. denali_reset_irq(denali);
  733. denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
  734. DENALI_ERASE);
  735. /* wait for erase to complete or failure to occur */
  736. irq_status = denali_wait_for_irq(denali,
  737. INTR__ERASE_COMP | INTR__ERASE_FAIL);
  738. return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
  739. }
  740. static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
  741. const struct nand_data_interface *conf)
  742. {
  743. struct denali_nand_info *denali = mtd_to_denali(mtd);
  744. const struct nand_sdr_timings *timings;
  745. unsigned long t_x, mult_x;
  746. int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
  747. int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
  748. int addr_2_data_mask;
  749. uint32_t tmp;
  750. timings = nand_get_sdr_timings(conf);
  751. if (IS_ERR(timings))
  752. return PTR_ERR(timings);
  753. /* clk_x period in picoseconds */
  754. t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
  755. if (!t_x)
  756. return -EINVAL;
  757. /*
  758. * The bus interface clock, clk_x, is phase aligned with the core clock.
  759. * The clk_x is an integral multiple N of the core clk. The value N is
  760. * configured at IP delivery time, and its available value is 4, 5, 6.
  761. */
  762. mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
  763. if (mult_x < 4 || mult_x > 6)
  764. return -EINVAL;
  765. if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
  766. return 0;
  767. /* tREA -> ACC_CLKS */
  768. acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
  769. acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
  770. tmp = ioread32(denali->reg + ACC_CLKS);
  771. tmp &= ~ACC_CLKS__VALUE;
  772. tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
  773. iowrite32(tmp, denali->reg + ACC_CLKS);
  774. /* tRWH -> RE_2_WE */
  775. re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
  776. re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
  777. tmp = ioread32(denali->reg + RE_2_WE);
  778. tmp &= ~RE_2_WE__VALUE;
  779. tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
  780. iowrite32(tmp, denali->reg + RE_2_WE);
  781. /* tRHZ -> RE_2_RE */
  782. re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
  783. re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
  784. tmp = ioread32(denali->reg + RE_2_RE);
  785. tmp &= ~RE_2_RE__VALUE;
  786. tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
  787. iowrite32(tmp, denali->reg + RE_2_RE);
  788. /*
  789. * tCCS, tWHR -> WE_2_RE
  790. *
  791. * With WE_2_RE properly set, the Denali controller automatically takes
  792. * care of the delay; the driver need not set NAND_WAIT_TCCS.
  793. */
  794. we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
  795. we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
  796. tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
  797. tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
  798. tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
  799. iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
  800. /* tADL -> ADDR_2_DATA */
  801. /* for older versions, ADDR_2_DATA is only 6 bit wide */
  802. addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
  803. if (denali->revision < 0x0501)
  804. addr_2_data_mask >>= 1;
  805. addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
  806. addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
  807. tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
  808. tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
  809. tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
  810. iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
  811. /* tREH, tWH -> RDWR_EN_HI_CNT */
  812. rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
  813. t_x);
  814. rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
  815. tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
  816. tmp &= ~RDWR_EN_HI_CNT__VALUE;
  817. tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
  818. iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
  819. /* tRP, tWP -> RDWR_EN_LO_CNT */
  820. rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
  821. rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
  822. t_x);
  823. rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
  824. rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
  825. rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
  826. tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
  827. tmp &= ~RDWR_EN_LO_CNT__VALUE;
  828. tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
  829. iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
  830. /* tCS, tCEA -> CS_SETUP_CNT */
  831. cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
  832. (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
  833. 0);
  834. cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
  835. tmp = ioread32(denali->reg + CS_SETUP_CNT);
  836. tmp &= ~CS_SETUP_CNT__VALUE;
  837. tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
  838. iowrite32(tmp, denali->reg + CS_SETUP_CNT);
  839. return 0;
  840. }
  841. static void denali_reset_banks(struct denali_nand_info *denali)
  842. {
  843. u32 irq_status;
  844. int i;
  845. for (i = 0; i < denali->max_banks; i++) {
  846. denali->active_bank = i;
  847. denali_reset_irq(denali);
  848. iowrite32(DEVICE_RESET__BANK(i),
  849. denali->reg + DEVICE_RESET);
  850. irq_status = denali_wait_for_irq(denali,
  851. INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
  852. if (!(irq_status & INTR__INT_ACT))
  853. break;
  854. }
  855. dev_dbg(denali->dev, "%d chips connected\n", i);
  856. denali->max_banks = i;
  857. }
  858. static void denali_hw_init(struct denali_nand_info *denali)
  859. {
  860. /*
  861. * The REVISION register may not be reliable. Platforms are allowed to
  862. * override it.
  863. */
  864. if (!denali->revision)
  865. denali->revision = swab16(ioread32(denali->reg + REVISION));
  866. /*
  867. * Set how many bytes should be skipped before writing data in OOB.
  868. * If a platform requests a non-zero value, set it to the register.
  869. * Otherwise, read the value out, expecting it has already been set up
  870. * by firmware.
  871. */
  872. if (denali->oob_skip_bytes)
  873. iowrite32(denali->oob_skip_bytes,
  874. denali->reg + SPARE_AREA_SKIP_BYTES);
  875. else
  876. denali->oob_skip_bytes = ioread32(denali->reg +
  877. SPARE_AREA_SKIP_BYTES);
  878. denali_detect_max_banks(denali);
  879. iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
  880. iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
  881. iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
  882. }
  883. int denali_calc_ecc_bytes(int step_size, int strength)
  884. {
  885. /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
  886. return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
  887. }
  888. EXPORT_SYMBOL(denali_calc_ecc_bytes);
  889. static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
  890. struct denali_nand_info *denali)
  891. {
  892. int oobavail = mtd->oobsize - denali->oob_skip_bytes;
  893. int ret;
  894. /*
  895. * If .size and .strength are already set (usually by DT),
  896. * check if they are supported by this controller.
  897. */
  898. if (chip->ecc.size && chip->ecc.strength)
  899. return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
  900. /*
  901. * We want .size and .strength closest to the chip's requirement
  902. * unless NAND_ECC_MAXIMIZE is requested.
  903. */
  904. if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
  905. ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
  906. if (!ret)
  907. return 0;
  908. }
  909. /* Max ECC strength is the last thing we can do */
  910. return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
  911. }
  912. static struct nand_ecclayout nand_oob;
  913. static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
  914. struct mtd_oob_region *oobregion)
  915. {
  916. struct denali_nand_info *denali = mtd_to_denali(mtd);
  917. struct nand_chip *chip = mtd_to_nand(mtd);
  918. if (section)
  919. return -ERANGE;
  920. oobregion->offset = denali->oob_skip_bytes;
  921. oobregion->length = chip->ecc.total;
  922. return 0;
  923. }
  924. static int denali_ooblayout_free(struct mtd_info *mtd, int section,
  925. struct mtd_oob_region *oobregion)
  926. {
  927. struct denali_nand_info *denali = mtd_to_denali(mtd);
  928. struct nand_chip *chip = mtd_to_nand(mtd);
  929. if (section)
  930. return -ERANGE;
  931. oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
  932. oobregion->length = mtd->oobsize - oobregion->offset;
  933. return 0;
  934. }
  935. static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
  936. .ecc = denali_ooblayout_ecc,
  937. .rfree = denali_ooblayout_free,
  938. };
  939. static int denali_multidev_fixup(struct denali_nand_info *denali)
  940. {
  941. struct nand_chip *chip = &denali->nand;
  942. struct mtd_info *mtd = nand_to_mtd(chip);
  943. /*
  944. * Support for multi device:
  945. * When the IP configuration is x16 capable and two x8 chips are
  946. * connected in parallel, DEVICES_CONNECTED should be set to 2.
  947. * In this case, the core framework knows nothing about this fact,
  948. * so we should tell it the _logical_ pagesize and anything necessary.
  949. */
  950. denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
  951. /*
  952. * On some SoCs, DEVICES_CONNECTED is not auto-detected.
  953. * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
  954. */
  955. if (denali->devs_per_cs == 0) {
  956. denali->devs_per_cs = 1;
  957. iowrite32(1, denali->reg + DEVICES_CONNECTED);
  958. }
  959. if (denali->devs_per_cs == 1)
  960. return 0;
  961. if (denali->devs_per_cs != 2) {
  962. dev_err(denali->dev, "unsupported number of devices %d\n",
  963. denali->devs_per_cs);
  964. return -EINVAL;
  965. }
  966. /* 2 chips in parallel */
  967. mtd->size <<= 1;
  968. mtd->erasesize <<= 1;
  969. mtd->writesize <<= 1;
  970. mtd->oobsize <<= 1;
  971. chip->chipsize <<= 1;
  972. chip->page_shift += 1;
  973. chip->phys_erase_shift += 1;
  974. chip->bbt_erase_shift += 1;
  975. chip->chip_shift += 1;
  976. chip->pagemask <<= 1;
  977. chip->ecc.size <<= 1;
  978. chip->ecc.bytes <<= 1;
  979. chip->ecc.strength <<= 1;
  980. denali->oob_skip_bytes <<= 1;
  981. return 0;
  982. }
  983. int denali_init(struct denali_nand_info *denali)
  984. {
  985. struct nand_chip *chip = &denali->nand;
  986. struct mtd_info *mtd = nand_to_mtd(chip);
  987. u32 features = ioread32(denali->reg + FEATURES);
  988. int ret;
  989. denali_hw_init(denali);
  990. denali_clear_irq_all(denali);
  991. denali_reset_banks(denali);
  992. denali->active_bank = DENALI_INVALID_BANK;
  993. chip->flash_node = dev_of_offset(denali->dev);
  994. /* Fallback to the default name if DT did not give "label" property */
  995. if (!mtd->name)
  996. mtd->name = "denali-nand";
  997. chip->select_chip = denali_select_chip;
  998. chip->read_byte = denali_read_byte;
  999. chip->write_byte = denali_write_byte;
  1000. chip->read_word = denali_read_word;
  1001. chip->cmd_ctrl = denali_cmd_ctrl;
  1002. chip->dev_ready = denali_dev_ready;
  1003. chip->waitfunc = denali_waitfunc;
  1004. if (features & FEATURES__INDEX_ADDR) {
  1005. denali->host_read = denali_indexed_read;
  1006. denali->host_write = denali_indexed_write;
  1007. } else {
  1008. denali->host_read = denali_direct_read;
  1009. denali->host_write = denali_direct_write;
  1010. }
  1011. /* clk rate info is needed for setup_data_interface */
  1012. if (denali->clk_x_rate)
  1013. chip->setup_data_interface = denali_setup_data_interface;
  1014. ret = nand_scan_ident(mtd, denali->max_banks, NULL);
  1015. if (ret)
  1016. return ret;
  1017. if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
  1018. denali->dma_avail = 1;
  1019. if (denali->dma_avail) {
  1020. chip->buf_align = ARCH_DMA_MINALIGN;
  1021. if (denali->caps & DENALI_CAP_DMA_64BIT)
  1022. denali->setup_dma = denali_setup_dma64;
  1023. else
  1024. denali->setup_dma = denali_setup_dma32;
  1025. } else {
  1026. chip->buf_align = 4;
  1027. }
  1028. chip->options |= NAND_USE_BOUNCE_BUFFER;
  1029. chip->bbt_options |= NAND_BBT_USE_FLASH;
  1030. chip->bbt_options |= NAND_BBT_NO_OOB;
  1031. denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
  1032. /* no subpage writes on denali */
  1033. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1034. ret = denali_ecc_setup(mtd, chip, denali);
  1035. if (ret) {
  1036. dev_err(denali->dev, "Failed to setup ECC settings.\n");
  1037. return ret;
  1038. }
  1039. dev_dbg(denali->dev,
  1040. "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
  1041. chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
  1042. iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
  1043. FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
  1044. denali->reg + ECC_CORRECTION);
  1045. iowrite32(mtd->erasesize / mtd->writesize,
  1046. denali->reg + PAGES_PER_BLOCK);
  1047. iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
  1048. denali->reg + DEVICE_WIDTH);
  1049. iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
  1050. denali->reg + TWO_ROW_ADDR_CYCLES);
  1051. iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
  1052. iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
  1053. iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
  1054. iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
  1055. /* chip->ecc.steps is set by nand_scan_tail(); not available here */
  1056. iowrite32(mtd->writesize / chip->ecc.size,
  1057. denali->reg + CFG_NUM_DATA_BLOCKS);
  1058. mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
  1059. nand_oob.eccbytes = denali->nand.ecc.bytes;
  1060. denali->nand.ecc.layout = &nand_oob;
  1061. if (chip->options & NAND_BUSWIDTH_16) {
  1062. chip->read_buf = denali_read_buf16;
  1063. chip->write_buf = denali_write_buf16;
  1064. } else {
  1065. chip->read_buf = denali_read_buf;
  1066. chip->write_buf = denali_write_buf;
  1067. }
  1068. chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
  1069. chip->ecc.read_page = denali_read_page;
  1070. chip->ecc.read_page_raw = denali_read_page_raw;
  1071. chip->ecc.write_page = denali_write_page;
  1072. chip->ecc.write_page_raw = denali_write_page_raw;
  1073. chip->ecc.read_oob = denali_read_oob;
  1074. chip->ecc.write_oob = denali_write_oob;
  1075. chip->erase = denali_erase;
  1076. ret = denali_multidev_fixup(denali);
  1077. if (ret)
  1078. return ret;
  1079. /*
  1080. * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
  1081. * use devm_kmalloc() because the memory allocated by devm_ does not
  1082. * guarantee DMA-safe alignment.
  1083. */
  1084. denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
  1085. if (!denali->buf)
  1086. return -ENOMEM;
  1087. ret = nand_scan_tail(mtd);
  1088. if (ret)
  1089. goto free_buf;
  1090. ret = nand_register(0, mtd);
  1091. if (ret) {
  1092. dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
  1093. goto free_buf;
  1094. }
  1095. return 0;
  1096. free_buf:
  1097. kfree(denali->buf);
  1098. return ret;
  1099. }