zynq_sdhci.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include "mmc_private.h"
  12. #include <linux/err.h>
  13. #include <linux/libfdt.h>
  14. #include <malloc.h>
  15. #include <sdhci.h>
  16. #include <zynqmp_tap_delay.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct arasan_sdhci_plat {
  19. struct mmc_config cfg;
  20. struct mmc mmc;
  21. unsigned int f_max;
  22. };
  23. struct arasan_sdhci_priv {
  24. struct sdhci_host *host;
  25. u8 deviceid;
  26. u8 bank;
  27. u8 no_1p8;
  28. };
  29. #if defined(CONFIG_ARCH_ZYNQMP)
  30. #define MMC_HS200_BUS_SPEED 5
  31. static const u8 mode2timing[] = {
  32. [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
  33. [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
  34. [MMC_HS] = HIGH_SPEED_BUS_SPEED,
  35. [SD_HS] = HIGH_SPEED_BUS_SPEED,
  36. [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
  37. [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
  38. [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  39. [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  40. [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  41. [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  42. [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  43. [MMC_HS_200] = MMC_HS200_BUS_SPEED,
  44. };
  45. #define SDHCI_TUNING_LOOP_COUNT 40
  46. static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  47. {
  48. u16 clk;
  49. unsigned long timeout;
  50. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  51. clk &= ~(SDHCI_CLOCK_CARD_EN);
  52. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  53. /* Issue DLL Reset */
  54. zynqmp_dll_reset(deviceid);
  55. /* Wait max 20 ms */
  56. timeout = 100;
  57. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  58. & SDHCI_CLOCK_INT_STABLE)) {
  59. if (timeout == 0) {
  60. dev_err(mmc_dev(host->mmc),
  61. ": Internal clock never stabilised.\n");
  62. return;
  63. }
  64. timeout--;
  65. udelay(1000);
  66. }
  67. clk |= SDHCI_CLOCK_CARD_EN;
  68. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  69. }
  70. static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  71. {
  72. struct mmc_cmd cmd;
  73. struct mmc_data data;
  74. u32 ctrl;
  75. struct sdhci_host *host;
  76. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  77. char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  78. u8 deviceid;
  79. debug("%s\n", __func__);
  80. host = priv->host;
  81. deviceid = priv->deviceid;
  82. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  83. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  84. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  85. mdelay(1);
  86. arasan_zynqmp_dll_reset(host, deviceid);
  87. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  88. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  89. do {
  90. cmd.cmdidx = opcode;
  91. cmd.resp_type = MMC_RSP_R1;
  92. cmd.cmdarg = 0;
  93. data.blocksize = 64;
  94. data.blocks = 1;
  95. data.flags = MMC_DATA_READ;
  96. if (tuning_loop_counter-- == 0)
  97. break;
  98. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  99. mmc->bus_width == 8)
  100. data.blocksize = 128;
  101. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  102. data.blocksize),
  103. SDHCI_BLOCK_SIZE);
  104. sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  105. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  106. mmc_send_cmd(mmc, &cmd, NULL);
  107. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  108. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  109. udelay(1);
  110. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  111. if (tuning_loop_counter < 0) {
  112. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  113. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  114. }
  115. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  116. printf("%s:Tuning failed\n", __func__);
  117. return -1;
  118. }
  119. udelay(1);
  120. arasan_zynqmp_dll_reset(host, deviceid);
  121. /* Enable only interrupts served by the SD controller */
  122. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  123. SDHCI_INT_ENABLE);
  124. /* Mask all sdhci interrupt sources */
  125. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  126. return 0;
  127. }
  128. static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  129. {
  130. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  131. struct mmc *mmc = (struct mmc *)host->mmc;
  132. u8 uhsmode;
  133. uhsmode = mode2timing[mmc->selected_mode];
  134. if (uhsmode >= UHS_SDR25_BUS_SPEED)
  135. arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
  136. priv->bank);
  137. }
  138. static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
  139. {
  140. struct mmc *mmc = (struct mmc *)host->mmc;
  141. u32 reg;
  142. if (!IS_SD(mmc))
  143. return;
  144. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  145. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  146. reg |= SDHCI_CTRL_VDD_180;
  147. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  148. }
  149. if (mmc->selected_mode > SD_HS &&
  150. mmc->selected_mode <= UHS_DDR50)
  151. sdhci_set_uhs_timing(host);
  152. }
  153. #endif
  154. #if defined(CONFIG_ARCH_ZYNQMP)
  155. const struct sdhci_ops arasan_ops = {
  156. .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  157. .set_delay = &arasan_sdhci_set_tapdelay,
  158. .set_control_reg = &arasan_sdhci_set_control_reg,
  159. };
  160. #endif
  161. static int arasan_sdhci_probe(struct udevice *dev)
  162. {
  163. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  164. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  165. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  166. struct sdhci_host *host;
  167. struct clk clk;
  168. unsigned long clock;
  169. int ret;
  170. host = priv->host;
  171. ret = clk_get_by_index(dev, 0, &clk);
  172. if (ret < 0) {
  173. dev_err(dev, "failed to get clock\n");
  174. return ret;
  175. }
  176. clock = clk_get_rate(&clk);
  177. if (IS_ERR_VALUE(clock)) {
  178. dev_err(dev, "failed to get rate\n");
  179. return clock;
  180. }
  181. debug("%s: CLK %ld\n", __func__, clock);
  182. ret = clk_enable(&clk);
  183. if (ret && ret != -ENOSYS) {
  184. dev_err(dev, "failed to enable clock\n");
  185. return ret;
  186. }
  187. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  188. SDHCI_QUIRK_BROKEN_R1B;
  189. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  190. host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
  191. #endif
  192. if (priv->no_1p8)
  193. host->quirks |= SDHCI_QUIRK_NO_1_8_V;
  194. host->max_clk = clock;
  195. host->mmc = &plat->mmc;
  196. host->mmc->dev = dev;
  197. host->mmc->priv = host;
  198. ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
  199. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  200. if (ret)
  201. return ret;
  202. upriv->mmc = host->mmc;
  203. return sdhci_probe(dev);
  204. }
  205. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  206. {
  207. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  208. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  209. priv->host = calloc(1, sizeof(struct sdhci_host));
  210. if (!priv->host)
  211. return -1;
  212. priv->host->name = dev->name;
  213. #if defined(CONFIG_ARCH_ZYNQMP)
  214. priv->host->ops = &arasan_ops;
  215. #endif
  216. priv->host->ioaddr = (void *)dev_read_addr(dev);
  217. if (IS_ERR(priv->host->ioaddr))
  218. return PTR_ERR(priv->host->ioaddr);
  219. priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
  220. priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
  221. priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
  222. plat->f_max = dev_read_u32_default(dev, "max-frequency",
  223. CONFIG_ZYNQ_SDHCI_MAX_FREQ);
  224. return 0;
  225. }
  226. static int arasan_sdhci_bind(struct udevice *dev)
  227. {
  228. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  229. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  230. }
  231. static const struct udevice_id arasan_sdhci_ids[] = {
  232. { .compatible = "arasan,sdhci-8.9a" },
  233. { }
  234. };
  235. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  236. .name = "arasan_sdhci",
  237. .id = UCLASS_MMC,
  238. .of_match = arasan_sdhci_ids,
  239. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  240. .ops = &sdhci_ops,
  241. .bind = arasan_sdhci_bind,
  242. .probe = arasan_sdhci_probe,
  243. .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
  244. .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
  245. };