tegra_mmc.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 SAMSUNG Electronics
  4. * Minkyu Kang <mk7.kang@samsung.com>
  5. * Jaehoon Chung <jh80.chung@samsung.com>
  6. * Portions Copyright 2011-2016 NVIDIA Corporation
  7. */
  8. #include <bouncebuf.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <mmc.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-tegra/tegra_mmc.h>
  16. #include <linux/err.h>
  17. struct tegra_mmc_plat {
  18. struct mmc_config cfg;
  19. struct mmc mmc;
  20. };
  21. struct tegra_mmc_priv {
  22. struct tegra_mmc *reg;
  23. struct reset_ctl reset_ctl;
  24. struct clk clk;
  25. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  26. struct gpio_desc pwr_gpio; /* Power GPIO */
  27. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  28. unsigned int version; /* SDHCI spec. version */
  29. unsigned int clock; /* Current clock (MHz) */
  30. };
  31. static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  32. unsigned short power)
  33. {
  34. u8 pwr = 0;
  35. debug("%s: power = %x\n", __func__, power);
  36. if (power != (unsigned short)-1) {
  37. switch (1 << power) {
  38. case MMC_VDD_165_195:
  39. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  40. break;
  41. case MMC_VDD_29_30:
  42. case MMC_VDD_30_31:
  43. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  44. break;
  45. case MMC_VDD_32_33:
  46. case MMC_VDD_33_34:
  47. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  48. break;
  49. }
  50. }
  51. debug("%s: pwr = %X\n", __func__, pwr);
  52. /* Set the bus voltage first (if any) */
  53. writeb(pwr, &priv->reg->pwrcon);
  54. if (pwr == 0)
  55. return;
  56. /* Now enable bus power */
  57. pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  58. writeb(pwr, &priv->reg->pwrcon);
  59. }
  60. static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  61. struct mmc_data *data,
  62. struct bounce_buffer *bbstate)
  63. {
  64. unsigned char ctrl;
  65. debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  66. bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  67. data->blocksize);
  68. writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  69. /*
  70. * DMASEL[4:3]
  71. * 00 = Selects SDMA
  72. * 01 = Reserved
  73. * 10 = Selects 32-bit Address ADMA2
  74. * 11 = Selects 64-bit Address ADMA2
  75. */
  76. ctrl = readb(&priv->reg->hostctl);
  77. ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  78. ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  79. writeb(ctrl, &priv->reg->hostctl);
  80. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  81. writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
  82. writew(data->blocks, &priv->reg->blkcnt);
  83. }
  84. static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
  85. struct mmc_data *data)
  86. {
  87. unsigned short mode;
  88. debug(" mmc_set_transfer_mode called\n");
  89. /*
  90. * TRNMOD
  91. * MUL1SIN0[5] : Multi/Single Block Select
  92. * RD1WT0[4] : Data Transfer Direction Select
  93. * 1 = read
  94. * 0 = write
  95. * ENACMD12[2] : Auto CMD12 Enable
  96. * ENBLKCNT[1] : Block Count Enable
  97. * ENDMA[0] : DMA Enable
  98. */
  99. mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
  100. TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
  101. if (data->blocks > 1)
  102. mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
  103. if (data->flags & MMC_DATA_READ)
  104. mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
  105. writew(mode, &priv->reg->trnmod);
  106. }
  107. static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
  108. struct mmc_cmd *cmd,
  109. struct mmc_data *data,
  110. unsigned int timeout)
  111. {
  112. /*
  113. * PRNSTS
  114. * CMDINHDAT[1] : Command Inhibit (DAT)
  115. * CMDINHCMD[0] : Command Inhibit (CMD)
  116. */
  117. unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
  118. /*
  119. * We shouldn't wait for data inhibit for stop commands, even
  120. * though they might use busy signaling
  121. */
  122. if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
  123. mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
  124. while (readl(&priv->reg->prnsts) & mask) {
  125. if (timeout == 0) {
  126. printf("%s: timeout error\n", __func__);
  127. return -1;
  128. }
  129. timeout--;
  130. udelay(1000);
  131. }
  132. return 0;
  133. }
  134. static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
  135. struct mmc_data *data,
  136. struct bounce_buffer *bbstate)
  137. {
  138. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  139. int flags, i;
  140. int result;
  141. unsigned int mask = 0;
  142. unsigned int retry = 0x100000;
  143. debug(" mmc_send_cmd called\n");
  144. result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
  145. if (result < 0)
  146. return result;
  147. if (data)
  148. tegra_mmc_prepare_data(priv, data, bbstate);
  149. debug("cmd->arg: %08x\n", cmd->cmdarg);
  150. writel(cmd->cmdarg, &priv->reg->argument);
  151. if (data)
  152. tegra_mmc_set_transfer_mode(priv, data);
  153. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  154. return -1;
  155. /*
  156. * CMDREG
  157. * CMDIDX[13:8] : Command index
  158. * DATAPRNT[5] : Data Present Select
  159. * ENCMDIDX[4] : Command Index Check Enable
  160. * ENCMDCRC[3] : Command CRC Check Enable
  161. * RSPTYP[1:0]
  162. * 00 = No Response
  163. * 01 = Length 136
  164. * 10 = Length 48
  165. * 11 = Length 48 Check busy after response
  166. */
  167. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  168. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
  169. else if (cmd->resp_type & MMC_RSP_136)
  170. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
  171. else if (cmd->resp_type & MMC_RSP_BUSY)
  172. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
  173. else
  174. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
  175. if (cmd->resp_type & MMC_RSP_CRC)
  176. flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
  177. if (cmd->resp_type & MMC_RSP_OPCODE)
  178. flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
  179. if (data)
  180. flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
  181. debug("cmd: %d\n", cmd->cmdidx);
  182. writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
  183. for (i = 0; i < retry; i++) {
  184. mask = readl(&priv->reg->norintsts);
  185. /* Command Complete */
  186. if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
  187. if (!data)
  188. writel(mask, &priv->reg->norintsts);
  189. break;
  190. }
  191. }
  192. if (i == retry) {
  193. printf("%s: waiting for status update\n", __func__);
  194. writel(mask, &priv->reg->norintsts);
  195. return -ETIMEDOUT;
  196. }
  197. if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
  198. /* Timeout Error */
  199. debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
  200. writel(mask, &priv->reg->norintsts);
  201. return -ETIMEDOUT;
  202. } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  203. /* Error Interrupt */
  204. debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
  205. writel(mask, &priv->reg->norintsts);
  206. return -1;
  207. }
  208. if (cmd->resp_type & MMC_RSP_PRESENT) {
  209. if (cmd->resp_type & MMC_RSP_136) {
  210. /* CRC is stripped so we need to do some shifting. */
  211. for (i = 0; i < 4; i++) {
  212. unsigned long offset = (unsigned long)
  213. (&priv->reg->rspreg3 - i);
  214. cmd->response[i] = readl(offset) << 8;
  215. if (i != 3) {
  216. cmd->response[i] |=
  217. readb(offset - 1);
  218. }
  219. debug("cmd->resp[%d]: %08x\n",
  220. i, cmd->response[i]);
  221. }
  222. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  223. for (i = 0; i < retry; i++) {
  224. /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
  225. if (readl(&priv->reg->prnsts)
  226. & (1 << 20)) /* DAT[0] */
  227. break;
  228. }
  229. if (i == retry) {
  230. printf("%s: card is still busy\n", __func__);
  231. writel(mask, &priv->reg->norintsts);
  232. return -ETIMEDOUT;
  233. }
  234. cmd->response[0] = readl(&priv->reg->rspreg0);
  235. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  236. } else {
  237. cmd->response[0] = readl(&priv->reg->rspreg0);
  238. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  239. }
  240. }
  241. if (data) {
  242. unsigned long start = get_timer(0);
  243. while (1) {
  244. mask = readl(&priv->reg->norintsts);
  245. if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  246. /* Error Interrupt */
  247. writel(mask, &priv->reg->norintsts);
  248. printf("%s: error during transfer: 0x%08x\n",
  249. __func__, mask);
  250. return -1;
  251. } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
  252. /*
  253. * DMA Interrupt, restart the transfer where
  254. * it was interrupted.
  255. */
  256. unsigned int address = readl(&priv->reg->sysad);
  257. debug("DMA end\n");
  258. writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
  259. &priv->reg->norintsts);
  260. writel(address, &priv->reg->sysad);
  261. } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
  262. /* Transfer Complete */
  263. debug("r/w is done\n");
  264. break;
  265. } else if (get_timer(start) > 8000UL) {
  266. writel(mask, &priv->reg->norintsts);
  267. printf("%s: MMC Timeout\n"
  268. " Interrupt status 0x%08x\n"
  269. " Interrupt status enable 0x%08x\n"
  270. " Interrupt signal enable 0x%08x\n"
  271. " Present status 0x%08x\n",
  272. __func__, mask,
  273. readl(&priv->reg->norintstsen),
  274. readl(&priv->reg->norintsigen),
  275. readl(&priv->reg->prnsts));
  276. return -1;
  277. }
  278. }
  279. writel(mask, &priv->reg->norintsts);
  280. }
  281. udelay(1000);
  282. return 0;
  283. }
  284. static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  285. struct mmc_data *data)
  286. {
  287. void *buf;
  288. unsigned int bbflags;
  289. size_t len;
  290. struct bounce_buffer bbstate;
  291. int ret;
  292. if (data) {
  293. if (data->flags & MMC_DATA_READ) {
  294. buf = data->dest;
  295. bbflags = GEN_BB_WRITE;
  296. } else {
  297. buf = (void *)data->src;
  298. bbflags = GEN_BB_READ;
  299. }
  300. len = data->blocks * data->blocksize;
  301. bounce_buffer_start(&bbstate, buf, len, bbflags);
  302. }
  303. ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
  304. if (data)
  305. bounce_buffer_stop(&bbstate);
  306. return ret;
  307. }
  308. static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
  309. {
  310. ulong rate;
  311. int div;
  312. unsigned short clk;
  313. unsigned long timeout;
  314. debug(" mmc_change_clock called\n");
  315. /*
  316. * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
  317. */
  318. if (clock == 0)
  319. goto out;
  320. rate = clk_set_rate(&priv->clk, clock);
  321. div = (rate + clock - 1) / clock;
  322. debug("div = %d\n", div);
  323. writew(0, &priv->reg->clkcon);
  324. /*
  325. * CLKCON
  326. * SELFREQ[15:8] : base clock divided by value
  327. * ENSDCLK[2] : SD Clock Enable
  328. * STBLINTCLK[1] : Internal Clock Stable
  329. * ENINTCLK[0] : Internal Clock Enable
  330. */
  331. div >>= 1;
  332. clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
  333. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
  334. writew(clk, &priv->reg->clkcon);
  335. /* Wait max 10 ms */
  336. timeout = 10;
  337. while (!(readw(&priv->reg->clkcon) &
  338. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
  339. if (timeout == 0) {
  340. printf("%s: timeout error\n", __func__);
  341. return;
  342. }
  343. timeout--;
  344. udelay(1000);
  345. }
  346. clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  347. writew(clk, &priv->reg->clkcon);
  348. debug("mmc_change_clock: clkcon = %08X\n", clk);
  349. out:
  350. priv->clock = clock;
  351. }
  352. static int tegra_mmc_set_ios(struct udevice *dev)
  353. {
  354. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  355. struct mmc *mmc = mmc_get_mmc_dev(dev);
  356. unsigned char ctrl;
  357. debug(" mmc_set_ios called\n");
  358. debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
  359. /* Change clock first */
  360. tegra_mmc_change_clock(priv, mmc->clock);
  361. ctrl = readb(&priv->reg->hostctl);
  362. /*
  363. * WIDE8[5]
  364. * 0 = Depend on WIDE4
  365. * 1 = 8-bit mode
  366. * WIDE4[1]
  367. * 1 = 4-bit mode
  368. * 0 = 1-bit mode
  369. */
  370. if (mmc->bus_width == 8)
  371. ctrl |= (1 << 5);
  372. else if (mmc->bus_width == 4)
  373. ctrl |= (1 << 1);
  374. else
  375. ctrl &= ~(1 << 1 | 1 << 5);
  376. writeb(ctrl, &priv->reg->hostctl);
  377. debug("mmc_set_ios: hostctl = %08X\n", ctrl);
  378. return 0;
  379. }
  380. static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
  381. {
  382. #if defined(CONFIG_TEGRA30)
  383. u32 val;
  384. debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
  385. /* Set the pad drive strength for SDMMC1 or 3 only */
  386. if (priv->reg != (void *)0x78000000 &&
  387. priv->reg != (void *)0x78000400) {
  388. debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
  389. __func__);
  390. return;
  391. }
  392. val = readl(&priv->reg->sdmemcmppadctl);
  393. val &= 0xFFFFFFF0;
  394. val |= MEMCOMP_PADCTRL_VREF;
  395. writel(val, &priv->reg->sdmemcmppadctl);
  396. val = readl(&priv->reg->autocalcfg);
  397. val &= 0xFFFF0000;
  398. val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
  399. writel(val, &priv->reg->autocalcfg);
  400. #endif
  401. }
  402. static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
  403. {
  404. unsigned int timeout;
  405. debug(" mmc_reset called\n");
  406. /*
  407. * RSTALL[0] : Software reset for all
  408. * 1 = reset
  409. * 0 = work
  410. */
  411. writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
  412. priv->clock = 0;
  413. /* Wait max 100 ms */
  414. timeout = 100;
  415. /* hw clears the bit when it's done */
  416. while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
  417. if (timeout == 0) {
  418. printf("%s: timeout error\n", __func__);
  419. return;
  420. }
  421. timeout--;
  422. udelay(1000);
  423. }
  424. /* Set SD bus voltage & enable bus power */
  425. tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
  426. debug("%s: power control = %02X, host control = %02X\n", __func__,
  427. readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
  428. /* Make sure SDIO pads are set up */
  429. tegra_mmc_pad_init(priv);
  430. }
  431. static int tegra_mmc_init(struct udevice *dev)
  432. {
  433. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  434. struct mmc *mmc = mmc_get_mmc_dev(dev);
  435. unsigned int mask;
  436. debug(" tegra_mmc_init called\n");
  437. tegra_mmc_reset(priv, mmc);
  438. #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
  439. /*
  440. * Disable the external clock loopback and use the internal one on
  441. * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
  442. * bits being set to 0xfffd according to the TRM.
  443. *
  444. * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
  445. * approach once proper kernel integration made it mainline.
  446. */
  447. if (priv->reg == (void *)0x700b0400) {
  448. mask = readl(&priv->reg->venmiscctl);
  449. mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
  450. writel(mask, &priv->reg->venmiscctl);
  451. }
  452. #endif
  453. priv->version = readw(&priv->reg->hcver);
  454. debug("host version = %x\n", priv->version);
  455. /* mask all */
  456. writel(0xffffffff, &priv->reg->norintstsen);
  457. writel(0xffffffff, &priv->reg->norintsigen);
  458. writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
  459. /*
  460. * NORMAL Interrupt Status Enable Register init
  461. * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
  462. * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
  463. * [3] ENSTADMAINT : DMA boundary interrupt
  464. * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
  465. * [0] ENSTACMDCMPLT : Command Complete Status Enable
  466. */
  467. mask = readl(&priv->reg->norintstsen);
  468. mask &= ~(0xffff);
  469. mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
  470. TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
  471. TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
  472. TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
  473. TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
  474. writel(mask, &priv->reg->norintstsen);
  475. /*
  476. * NORMAL Interrupt Signal Enable Register init
  477. * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
  478. */
  479. mask = readl(&priv->reg->norintsigen);
  480. mask &= ~(0xffff);
  481. mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
  482. writel(mask, &priv->reg->norintsigen);
  483. return 0;
  484. }
  485. static int tegra_mmc_getcd(struct udevice *dev)
  486. {
  487. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  488. debug("tegra_mmc_getcd called\n");
  489. if (dm_gpio_is_valid(&priv->cd_gpio))
  490. return dm_gpio_get_value(&priv->cd_gpio);
  491. return 1;
  492. }
  493. static const struct dm_mmc_ops tegra_mmc_ops = {
  494. .send_cmd = tegra_mmc_send_cmd,
  495. .set_ios = tegra_mmc_set_ios,
  496. .get_cd = tegra_mmc_getcd,
  497. };
  498. static int tegra_mmc_probe(struct udevice *dev)
  499. {
  500. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  501. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  502. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  503. struct mmc_config *cfg = &plat->cfg;
  504. int bus_width, ret;
  505. cfg->name = dev->name;
  506. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  507. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  508. cfg->host_caps = 0;
  509. if (bus_width == 8)
  510. cfg->host_caps |= MMC_MODE_8BIT;
  511. if (bus_width >= 4)
  512. cfg->host_caps |= MMC_MODE_4BIT;
  513. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  514. /*
  515. * min freq is for card identification, and is the highest
  516. * low-speed SDIO card frequency (actually 400KHz)
  517. * max freq is highest HS eMMC clock as per the SD/MMC spec
  518. * (actually 52MHz)
  519. */
  520. cfg->f_min = 375000;
  521. cfg->f_max = 48000000;
  522. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  523. priv->reg = (void *)dev_read_addr(dev);
  524. ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
  525. if (ret) {
  526. debug("reset_get_by_name() failed: %d\n", ret);
  527. return ret;
  528. }
  529. ret = clk_get_by_index(dev, 0, &priv->clk);
  530. if (ret) {
  531. debug("clk_get_by_index() failed: %d\n", ret);
  532. return ret;
  533. }
  534. ret = reset_assert(&priv->reset_ctl);
  535. if (ret)
  536. return ret;
  537. ret = clk_enable(&priv->clk);
  538. if (ret)
  539. return ret;
  540. ret = clk_set_rate(&priv->clk, 20000000);
  541. if (IS_ERR_VALUE(ret))
  542. return ret;
  543. ret = reset_deassert(&priv->reset_ctl);
  544. if (ret)
  545. return ret;
  546. /* These GPIOs are optional */
  547. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  548. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  549. gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
  550. GPIOD_IS_OUT);
  551. if (dm_gpio_is_valid(&priv->pwr_gpio))
  552. dm_gpio_set_value(&priv->pwr_gpio, 1);
  553. upriv->mmc = &plat->mmc;
  554. return tegra_mmc_init(dev);
  555. }
  556. static int tegra_mmc_bind(struct udevice *dev)
  557. {
  558. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  559. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  560. }
  561. static const struct udevice_id tegra_mmc_ids[] = {
  562. { .compatible = "nvidia,tegra20-sdhci" },
  563. { .compatible = "nvidia,tegra30-sdhci" },
  564. { .compatible = "nvidia,tegra114-sdhci" },
  565. { .compatible = "nvidia,tegra124-sdhci" },
  566. { .compatible = "nvidia,tegra210-sdhci" },
  567. { .compatible = "nvidia,tegra186-sdhci" },
  568. { }
  569. };
  570. U_BOOT_DRIVER(tegra_mmc_drv) = {
  571. .name = "tegra_mmc",
  572. .id = UCLASS_MMC,
  573. .of_match = tegra_mmc_ids,
  574. .bind = tegra_mmc_bind,
  575. .probe = tegra_mmc_probe,
  576. .ops = &tegra_mmc_ops,
  577. .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
  578. .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
  579. };