omap_hsmmc.c 50 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. * Sukumar Ghorai <s-ghorai@ti.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation's version 2 of
  12. * the License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <config.h>
  25. #include <common.h>
  26. #include <cpu_func.h>
  27. #include <malloc.h>
  28. #include <memalign.h>
  29. #include <mmc.h>
  30. #include <part.h>
  31. #include <i2c.h>
  32. #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33. #include <palmas.h>
  34. #endif
  35. #include <asm/io.h>
  36. #include <asm/arch/mmc_host_def.h>
  37. #ifdef CONFIG_OMAP54XX
  38. #include <asm/arch/mux_dra7xx.h>
  39. #include <asm/arch/dra7xx_iodelay.h>
  40. #endif
  41. #if !defined(CONFIG_SOC_KEYSTONE)
  42. #include <asm/gpio.h>
  43. #include <asm/arch/sys_proto.h>
  44. #endif
  45. #ifdef CONFIG_MMC_OMAP36XX_PINS
  46. #include <asm/arch/mux.h>
  47. #endif
  48. #include <dm.h>
  49. #include <dm/devres.h>
  50. #include <linux/err.h>
  51. #include <power/regulator.h>
  52. #include <thermal.h>
  53. DECLARE_GLOBAL_DATA_PTR;
  54. /* simplify defines to OMAP_HSMMC_USE_GPIO */
  55. #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  56. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  57. #define OMAP_HSMMC_USE_GPIO
  58. #else
  59. #undef OMAP_HSMMC_USE_GPIO
  60. #endif
  61. /* common definitions for all OMAPs */
  62. #define SYSCTL_SRC (1 << 25)
  63. #define SYSCTL_SRD (1 << 26)
  64. #ifdef CONFIG_IODELAY_RECALIBRATION
  65. struct omap_hsmmc_pinctrl_state {
  66. struct pad_conf_entry *padconf;
  67. int npads;
  68. struct iodelay_cfg_entry *iodelay;
  69. int niodelays;
  70. };
  71. #endif
  72. struct omap_hsmmc_data {
  73. struct hsmmc *base_addr;
  74. #if !CONFIG_IS_ENABLED(DM_MMC)
  75. struct mmc_config cfg;
  76. #endif
  77. uint bus_width;
  78. uint clock;
  79. ushort last_cmd;
  80. #ifdef OMAP_HSMMC_USE_GPIO
  81. #if CONFIG_IS_ENABLED(DM_MMC)
  82. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  83. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  84. #else
  85. int cd_gpio;
  86. int wp_gpio;
  87. #endif
  88. #endif
  89. #if CONFIG_IS_ENABLED(DM_MMC)
  90. enum bus_mode mode;
  91. #endif
  92. u8 controller_flags;
  93. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  94. struct omap_hsmmc_adma_desc *adma_desc_table;
  95. uint desc_slot;
  96. #endif
  97. const char *hw_rev;
  98. struct udevice *pbias_supply;
  99. uint signal_voltage;
  100. #ifdef CONFIG_IODELAY_RECALIBRATION
  101. struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
  102. struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
  103. struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
  104. struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
  105. struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
  106. struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
  107. struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
  108. struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
  109. struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
  110. #endif
  111. };
  112. struct omap_mmc_of_data {
  113. u8 controller_flags;
  114. };
  115. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  116. struct omap_hsmmc_adma_desc {
  117. u8 attr;
  118. u8 reserved;
  119. u16 len;
  120. u32 addr;
  121. };
  122. #define ADMA_MAX_LEN 63488
  123. /* Decriptor table defines */
  124. #define ADMA_DESC_ATTR_VALID BIT(0)
  125. #define ADMA_DESC_ATTR_END BIT(1)
  126. #define ADMA_DESC_ATTR_INT BIT(2)
  127. #define ADMA_DESC_ATTR_ACT1 BIT(4)
  128. #define ADMA_DESC_ATTR_ACT2 BIT(5)
  129. #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
  130. #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
  131. #endif
  132. /* If we fail after 1 second wait, something is really bad */
  133. #define MAX_RETRY_MS 1000
  134. #define MMC_TIMEOUT_MS 20
  135. /* DMA transfers can take a long time if a lot a data is transferred.
  136. * The timeout must take in account the amount of data. Let's assume
  137. * that the time will never exceed 333 ms per MB (in other word we assume
  138. * that the bandwidth is always above 3MB/s).
  139. */
  140. #define DMA_TIMEOUT_PER_MB 333
  141. #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
  142. #define OMAP_HSMMC_NO_1_8_V BIT(1)
  143. #define OMAP_HSMMC_USE_ADMA BIT(2)
  144. #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
  145. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  146. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  147. unsigned int siz);
  148. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
  149. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
  150. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
  151. static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
  152. {
  153. #if CONFIG_IS_ENABLED(DM_MMC)
  154. return dev_get_priv(mmc->dev);
  155. #else
  156. return (struct omap_hsmmc_data *)mmc->priv;
  157. #endif
  158. }
  159. static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
  160. {
  161. #if CONFIG_IS_ENABLED(DM_MMC)
  162. struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
  163. return &plat->cfg;
  164. #else
  165. return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
  166. #endif
  167. }
  168. #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
  169. static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  170. {
  171. int ret;
  172. #if !CONFIG_IS_ENABLED(DM_GPIO)
  173. if (!gpio_is_valid(gpio))
  174. return -1;
  175. #endif
  176. ret = gpio_request(gpio, label);
  177. if (ret)
  178. return ret;
  179. ret = gpio_direction_input(gpio);
  180. if (ret)
  181. return ret;
  182. return gpio;
  183. }
  184. #endif
  185. static unsigned char mmc_board_init(struct mmc *mmc)
  186. {
  187. #if defined(CONFIG_OMAP34XX)
  188. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  189. t2_t *t2_base = (t2_t *)T2_BASE;
  190. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  191. u32 pbias_lite;
  192. #ifdef CONFIG_MMC_OMAP36XX_PINS
  193. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  194. #endif
  195. pbias_lite = readl(&t2_base->pbias_lite);
  196. pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
  197. #ifdef CONFIG_TARGET_OMAP3_CAIRO
  198. /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
  199. pbias_lite &= ~PBIASLITEVMODE0;
  200. #endif
  201. #ifdef CONFIG_TARGET_OMAP3_LOGIC
  202. /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
  203. pbias_lite &= ~PBIASLITEVMODE1;
  204. #endif
  205. #ifdef CONFIG_MMC_OMAP36XX_PINS
  206. if (get_cpu_family() == CPU_OMAP36XX) {
  207. /* Disable extended drain IO before changing PBIAS */
  208. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  209. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  210. }
  211. #endif
  212. writel(pbias_lite, &t2_base->pbias_lite);
  213. writel(pbias_lite | PBIASLITEPWRDNZ1 |
  214. PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  215. &t2_base->pbias_lite);
  216. #ifdef CONFIG_MMC_OMAP36XX_PINS
  217. if (get_cpu_family() == CPU_OMAP36XX)
  218. /* Enable extended drain IO after changing PBIAS */
  219. writel(wkup_ctrl |
  220. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  221. OMAP34XX_CTRL_WKUP_CTRL);
  222. #endif
  223. writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  224. &t2_base->devconf0);
  225. writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  226. &t2_base->devconf1);
  227. /* Change from default of 52MHz to 26MHz if necessary */
  228. if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
  229. writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
  230. &t2_base->ctl_prog_io1);
  231. writel(readl(&prcm_base->fclken1_core) |
  232. EN_MMC1 | EN_MMC2 | EN_MMC3,
  233. &prcm_base->fclken1_core);
  234. writel(readl(&prcm_base->iclken1_core) |
  235. EN_MMC1 | EN_MMC2 | EN_MMC3,
  236. &prcm_base->iclken1_core);
  237. #endif
  238. #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
  239. !CONFIG_IS_ENABLED(DM_REGULATOR)
  240. /* PBIAS config needed for MMC1 only */
  241. if (mmc_get_blk_desc(mmc)->devnum == 0)
  242. vmmc_pbias_config(LDO_VOLT_3V3);
  243. #endif
  244. return 0;
  245. }
  246. void mmc_init_stream(struct hsmmc *mmc_base)
  247. {
  248. ulong start;
  249. writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
  250. writel(MMC_CMD0, &mmc_base->cmd);
  251. start = get_timer(0);
  252. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  253. if (get_timer(0) - start > MAX_RETRY_MS) {
  254. printf("%s: timedout waiting for cc!\n", __func__);
  255. return;
  256. }
  257. }
  258. writel(CC_MASK, &mmc_base->stat)
  259. ;
  260. writel(MMC_CMD0, &mmc_base->cmd)
  261. ;
  262. start = get_timer(0);
  263. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  264. if (get_timer(0) - start > MAX_RETRY_MS) {
  265. printf("%s: timedout waiting for cc2!\n", __func__);
  266. return;
  267. }
  268. }
  269. writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
  270. }
  271. #if CONFIG_IS_ENABLED(DM_MMC)
  272. #ifdef CONFIG_IODELAY_RECALIBRATION
  273. static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
  274. {
  275. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  276. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  277. switch (priv->mode) {
  278. case MMC_HS_200:
  279. pinctrl_state = priv->hs200_1_8v_pinctrl_state;
  280. break;
  281. case UHS_SDR104:
  282. pinctrl_state = priv->sdr104_pinctrl_state;
  283. break;
  284. case UHS_SDR50:
  285. pinctrl_state = priv->sdr50_pinctrl_state;
  286. break;
  287. case UHS_DDR50:
  288. pinctrl_state = priv->ddr50_pinctrl_state;
  289. break;
  290. case UHS_SDR25:
  291. pinctrl_state = priv->sdr25_pinctrl_state;
  292. break;
  293. case UHS_SDR12:
  294. pinctrl_state = priv->sdr12_pinctrl_state;
  295. break;
  296. case SD_HS:
  297. case MMC_HS:
  298. case MMC_HS_52:
  299. pinctrl_state = priv->hs_pinctrl_state;
  300. break;
  301. case MMC_DDR_52:
  302. pinctrl_state = priv->ddr_1_8v_pinctrl_state;
  303. default:
  304. pinctrl_state = priv->default_pinctrl_state;
  305. break;
  306. }
  307. if (!pinctrl_state)
  308. pinctrl_state = priv->default_pinctrl_state;
  309. if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
  310. if (pinctrl_state->iodelay)
  311. late_recalibrate_iodelay(pinctrl_state->padconf,
  312. pinctrl_state->npads,
  313. pinctrl_state->iodelay,
  314. pinctrl_state->niodelays);
  315. else
  316. do_set_mux32((*ctrl)->control_padconf_core_base,
  317. pinctrl_state->padconf,
  318. pinctrl_state->npads);
  319. }
  320. }
  321. #endif
  322. static void omap_hsmmc_set_timing(struct mmc *mmc)
  323. {
  324. u32 val;
  325. struct hsmmc *mmc_base;
  326. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  327. mmc_base = priv->base_addr;
  328. omap_hsmmc_stop_clock(mmc_base);
  329. val = readl(&mmc_base->ac12);
  330. val &= ~AC12_UHSMC_MASK;
  331. priv->mode = mmc->selected_mode;
  332. if (mmc_is_mode_ddr(priv->mode))
  333. writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
  334. else
  335. writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
  336. switch (priv->mode) {
  337. case MMC_HS_200:
  338. case UHS_SDR104:
  339. val |= AC12_UHSMC_SDR104;
  340. break;
  341. case UHS_SDR50:
  342. val |= AC12_UHSMC_SDR50;
  343. break;
  344. case MMC_DDR_52:
  345. case UHS_DDR50:
  346. val |= AC12_UHSMC_DDR50;
  347. break;
  348. case SD_HS:
  349. case MMC_HS_52:
  350. case UHS_SDR25:
  351. val |= AC12_UHSMC_SDR25;
  352. break;
  353. case MMC_LEGACY:
  354. case MMC_HS:
  355. case SD_LEGACY:
  356. case UHS_SDR12:
  357. val |= AC12_UHSMC_SDR12;
  358. break;
  359. default:
  360. val |= AC12_UHSMC_RES;
  361. break;
  362. }
  363. writel(val, &mmc_base->ac12);
  364. #ifdef CONFIG_IODELAY_RECALIBRATION
  365. omap_hsmmc_io_recalibrate(mmc);
  366. #endif
  367. omap_hsmmc_start_clock(mmc_base);
  368. }
  369. static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
  370. {
  371. struct hsmmc *mmc_base;
  372. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  373. u32 hctl, ac12;
  374. mmc_base = priv->base_addr;
  375. hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
  376. ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
  377. switch (signal_voltage) {
  378. case MMC_SIGNAL_VOLTAGE_330:
  379. hctl |= SDVS_3V3;
  380. break;
  381. case MMC_SIGNAL_VOLTAGE_180:
  382. hctl |= SDVS_1V8;
  383. ac12 |= AC12_V1V8_SIGEN;
  384. break;
  385. }
  386. writel(hctl, &mmc_base->hctl);
  387. writel(ac12, &mmc_base->ac12);
  388. }
  389. static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
  390. {
  391. int ret = -ETIMEDOUT;
  392. u32 con;
  393. bool dat0_high;
  394. bool target_dat0_high = !!state;
  395. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  396. struct hsmmc *mmc_base = priv->base_addr;
  397. con = readl(&mmc_base->con);
  398. writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
  399. timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
  400. while (timeout_us--) {
  401. dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
  402. if (dat0_high == target_dat0_high) {
  403. ret = 0;
  404. break;
  405. }
  406. udelay(10);
  407. }
  408. writel(con, &mmc_base->con);
  409. return ret;
  410. }
  411. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  412. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  413. static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
  414. {
  415. int ret = 0;
  416. int uV = mV * 1000;
  417. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  418. if (!mmc->vqmmc_supply)
  419. return 0;
  420. /* Disable PBIAS */
  421. ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
  422. if (ret)
  423. return ret;
  424. /* Turn off IO voltage */
  425. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
  426. if (ret)
  427. return ret;
  428. /* Program a new IO voltage value */
  429. ret = regulator_set_value(mmc->vqmmc_supply, uV);
  430. if (ret)
  431. return ret;
  432. /* Turn on IO voltage */
  433. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
  434. if (ret)
  435. return ret;
  436. /* Program PBIAS voltage*/
  437. ret = regulator_set_value(priv->pbias_supply, uV);
  438. if (ret && ret != -ENOSYS)
  439. return ret;
  440. /* Enable PBIAS */
  441. ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
  442. if (ret)
  443. return ret;
  444. return 0;
  445. }
  446. #endif
  447. static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
  448. {
  449. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  450. struct hsmmc *mmc_base = priv->base_addr;
  451. int mv = mmc_voltage_to_mv(mmc->signal_voltage);
  452. u32 capa_mask;
  453. __maybe_unused u8 palmas_ldo_volt;
  454. u32 val;
  455. if (mv < 0)
  456. return -EINVAL;
  457. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
  458. mv = 3300;
  459. capa_mask = VS33_3V3SUP;
  460. palmas_ldo_volt = LDO_VOLT_3V3;
  461. } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  462. capa_mask = VS18_1V8SUP;
  463. palmas_ldo_volt = LDO_VOLT_1V8;
  464. } else {
  465. return -EOPNOTSUPP;
  466. }
  467. val = readl(&mmc_base->capa);
  468. if (!(val & capa_mask))
  469. return -EOPNOTSUPP;
  470. priv->signal_voltage = mmc->signal_voltage;
  471. omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
  472. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  473. return omap_hsmmc_set_io_regulator(mmc, mv);
  474. #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
  475. defined(CONFIG_PALMAS_POWER)
  476. if (mmc_get_blk_desc(mmc)->devnum == 0)
  477. vmmc_pbias_config(palmas_ldo_volt);
  478. return 0;
  479. #else
  480. return 0;
  481. #endif
  482. }
  483. #endif
  484. static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
  485. {
  486. struct hsmmc *mmc_base;
  487. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  488. u32 val;
  489. mmc_base = priv->base_addr;
  490. val = readl(&mmc_base->capa);
  491. if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  492. val |= (VS33_3V3SUP | VS18_1V8SUP);
  493. } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
  494. val |= VS33_3V3SUP;
  495. val &= ~VS18_1V8SUP;
  496. } else {
  497. val |= VS18_1V8SUP;
  498. val &= ~VS33_3V3SUP;
  499. }
  500. writel(val, &mmc_base->capa);
  501. return val;
  502. }
  503. #ifdef MMC_SUPPORTS_TUNING
  504. static void omap_hsmmc_disable_tuning(struct mmc *mmc)
  505. {
  506. struct hsmmc *mmc_base;
  507. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  508. u32 val;
  509. mmc_base = priv->base_addr;
  510. val = readl(&mmc_base->ac12);
  511. val &= ~(AC12_SCLK_SEL);
  512. writel(val, &mmc_base->ac12);
  513. val = readl(&mmc_base->dll);
  514. val &= ~(DLL_FORCE_VALUE | DLL_SWT);
  515. writel(val, &mmc_base->dll);
  516. }
  517. static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
  518. {
  519. int i;
  520. struct hsmmc *mmc_base;
  521. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  522. u32 val;
  523. mmc_base = priv->base_addr;
  524. val = readl(&mmc_base->dll);
  525. val |= DLL_FORCE_VALUE;
  526. val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
  527. val |= (count << DLL_FORCE_SR_C_SHIFT);
  528. writel(val, &mmc_base->dll);
  529. val |= DLL_CALIB;
  530. writel(val, &mmc_base->dll);
  531. for (i = 0; i < 1000; i++) {
  532. if (readl(&mmc_base->dll) & DLL_CALIB)
  533. break;
  534. }
  535. val &= ~DLL_CALIB;
  536. writel(val, &mmc_base->dll);
  537. }
  538. static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
  539. {
  540. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  541. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  542. struct mmc *mmc = upriv->mmc;
  543. struct hsmmc *mmc_base;
  544. u32 val;
  545. u8 cur_match, prev_match = 0;
  546. int ret;
  547. u32 phase_delay = 0;
  548. u32 start_window = 0, max_window = 0;
  549. u32 length = 0, max_len = 0;
  550. bool single_point_failure = false;
  551. struct udevice *thermal_dev;
  552. int temperature;
  553. int i;
  554. mmc_base = priv->base_addr;
  555. val = readl(&mmc_base->capa2);
  556. /* clock tuning is not needed for upto 52MHz */
  557. if (!((mmc->selected_mode == MMC_HS_200) ||
  558. (mmc->selected_mode == UHS_SDR104) ||
  559. ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
  560. return 0;
  561. ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
  562. if (ret) {
  563. printf("Couldn't get thermal device for tuning\n");
  564. return ret;
  565. }
  566. ret = thermal_get_temp(thermal_dev, &temperature);
  567. if (ret) {
  568. printf("Couldn't get temperature for tuning\n");
  569. return ret;
  570. }
  571. val = readl(&mmc_base->dll);
  572. val |= DLL_SWT;
  573. writel(val, &mmc_base->dll);
  574. /*
  575. * Stage 1: Search for a maximum pass window ignoring any
  576. * any single point failures. If the tuning value ends up
  577. * near it, move away from it in stage 2 below
  578. */
  579. while (phase_delay <= MAX_PHASE_DELAY) {
  580. omap_hsmmc_set_dll(mmc, phase_delay);
  581. cur_match = !mmc_send_tuning(mmc, opcode, NULL);
  582. if (cur_match) {
  583. if (prev_match) {
  584. length++;
  585. } else if (single_point_failure) {
  586. /* ignore single point failure */
  587. length++;
  588. single_point_failure = false;
  589. } else {
  590. start_window = phase_delay;
  591. length = 1;
  592. }
  593. } else {
  594. single_point_failure = prev_match;
  595. }
  596. if (length > max_len) {
  597. max_window = start_window;
  598. max_len = length;
  599. }
  600. prev_match = cur_match;
  601. phase_delay += 4;
  602. }
  603. if (!max_len) {
  604. ret = -EIO;
  605. goto tuning_error;
  606. }
  607. val = readl(&mmc_base->ac12);
  608. if (!(val & AC12_SCLK_SEL)) {
  609. ret = -EIO;
  610. goto tuning_error;
  611. }
  612. /*
  613. * Assign tuning value as a ratio of maximum pass window based
  614. * on temperature
  615. */
  616. if (temperature < -20000)
  617. phase_delay = min(max_window + 4 * max_len - 24,
  618. max_window +
  619. DIV_ROUND_UP(13 * max_len, 16) * 4);
  620. else if (temperature < 20000)
  621. phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
  622. else if (temperature < 40000)
  623. phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
  624. else if (temperature < 70000)
  625. phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
  626. else if (temperature < 90000)
  627. phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
  628. else if (temperature < 120000)
  629. phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
  630. else
  631. phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
  632. /*
  633. * Stage 2: Search for a single point failure near the chosen tuning
  634. * value in two steps. First in the +3 to +10 range and then in the
  635. * +2 to -10 range. If found, move away from it in the appropriate
  636. * direction by the appropriate amount depending on the temperature.
  637. */
  638. for (i = 3; i <= 10; i++) {
  639. omap_hsmmc_set_dll(mmc, phase_delay + i);
  640. if (mmc_send_tuning(mmc, opcode, NULL)) {
  641. if (temperature < 10000)
  642. phase_delay += i + 6;
  643. else if (temperature < 20000)
  644. phase_delay += i - 12;
  645. else if (temperature < 70000)
  646. phase_delay += i - 8;
  647. else if (temperature < 90000)
  648. phase_delay += i - 6;
  649. else
  650. phase_delay += i - 6;
  651. goto single_failure_found;
  652. }
  653. }
  654. for (i = 2; i >= -10; i--) {
  655. omap_hsmmc_set_dll(mmc, phase_delay + i);
  656. if (mmc_send_tuning(mmc, opcode, NULL)) {
  657. if (temperature < 10000)
  658. phase_delay += i + 12;
  659. else if (temperature < 20000)
  660. phase_delay += i + 8;
  661. else if (temperature < 70000)
  662. phase_delay += i + 8;
  663. else if (temperature < 90000)
  664. phase_delay += i + 10;
  665. else
  666. phase_delay += i + 12;
  667. goto single_failure_found;
  668. }
  669. }
  670. single_failure_found:
  671. omap_hsmmc_set_dll(mmc, phase_delay);
  672. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  673. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  674. return 0;
  675. tuning_error:
  676. omap_hsmmc_disable_tuning(mmc);
  677. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  678. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  679. return ret;
  680. }
  681. #endif
  682. #endif
  683. static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
  684. {
  685. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  686. struct hsmmc *mmc_base = priv->base_addr;
  687. u32 irq_mask = INT_EN_MASK;
  688. /*
  689. * TODO: Errata i802 indicates only DCRC interrupts can occur during
  690. * tuning procedure and DCRC should be disabled. But see occurences
  691. * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
  692. * interrupts occur along with BRR, so the data is actually in the
  693. * buffer. It has to be debugged why these interrutps occur
  694. */
  695. if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
  696. irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
  697. writel(irq_mask, &mmc_base->ie);
  698. }
  699. static int omap_hsmmc_init_setup(struct mmc *mmc)
  700. {
  701. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  702. struct hsmmc *mmc_base;
  703. unsigned int reg_val;
  704. unsigned int dsor;
  705. ulong start;
  706. mmc_base = priv->base_addr;
  707. mmc_board_init(mmc);
  708. writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
  709. &mmc_base->sysconfig);
  710. start = get_timer(0);
  711. while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
  712. if (get_timer(0) - start > MAX_RETRY_MS) {
  713. printf("%s: timedout waiting for cc2!\n", __func__);
  714. return -ETIMEDOUT;
  715. }
  716. }
  717. writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
  718. start = get_timer(0);
  719. while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
  720. if (get_timer(0) - start > MAX_RETRY_MS) {
  721. printf("%s: timedout waiting for softresetall!\n",
  722. __func__);
  723. return -ETIMEDOUT;
  724. }
  725. }
  726. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  727. reg_val = readl(&mmc_base->hl_hwinfo);
  728. if (reg_val & MADMA_EN)
  729. priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
  730. #endif
  731. #if CONFIG_IS_ENABLED(DM_MMC)
  732. reg_val = omap_hsmmc_set_capabilities(mmc);
  733. omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
  734. MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
  735. #else
  736. writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
  737. writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
  738. &mmc_base->capa);
  739. #endif
  740. reg_val = readl(&mmc_base->con) & RESERVED_MASK;
  741. writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
  742. MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
  743. HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
  744. dsor = 240;
  745. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
  746. (ICE_STOP | DTO_15THDTO));
  747. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  748. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  749. start = get_timer(0);
  750. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  751. if (get_timer(0) - start > MAX_RETRY_MS) {
  752. printf("%s: timedout waiting for ics!\n", __func__);
  753. return -ETIMEDOUT;
  754. }
  755. }
  756. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  757. writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
  758. mmc_enable_irq(mmc, NULL);
  759. #if !CONFIG_IS_ENABLED(DM_MMC)
  760. mmc_init_stream(mmc_base);
  761. #endif
  762. return 0;
  763. }
  764. /*
  765. * MMC controller internal finite state machine reset
  766. *
  767. * Used to reset command or data internal state machines, using respectively
  768. * SRC or SRD bit of SYSCTL register
  769. */
  770. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
  771. {
  772. ulong start;
  773. mmc_reg_out(&mmc_base->sysctl, bit, bit);
  774. /*
  775. * CMD(DAT) lines reset procedures are slightly different
  776. * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
  777. * According to OMAP3 TRM:
  778. * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
  779. * returns to 0x0.
  780. * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
  781. * procedure steps must be as follows:
  782. * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
  783. * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
  784. * 2. Poll the SRC(SRD) bit until it is set to 0x1.
  785. * 3. Wait until the SRC (SRD) bit returns to 0x0
  786. * (reset procedure is completed).
  787. */
  788. #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  789. defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
  790. if (!(readl(&mmc_base->sysctl) & bit)) {
  791. start = get_timer(0);
  792. while (!(readl(&mmc_base->sysctl) & bit)) {
  793. if (get_timer(0) - start > MMC_TIMEOUT_MS)
  794. return;
  795. }
  796. }
  797. #endif
  798. start = get_timer(0);
  799. while ((readl(&mmc_base->sysctl) & bit) != 0) {
  800. if (get_timer(0) - start > MAX_RETRY_MS) {
  801. printf("%s: timedout waiting for sysctl %x to clear\n",
  802. __func__, bit);
  803. return;
  804. }
  805. }
  806. }
  807. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  808. static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
  809. {
  810. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  811. struct omap_hsmmc_adma_desc *desc;
  812. u8 attr;
  813. desc = &priv->adma_desc_table[priv->desc_slot];
  814. attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  815. if (!end)
  816. priv->desc_slot++;
  817. else
  818. attr |= ADMA_DESC_ATTR_END;
  819. desc->len = len;
  820. desc->addr = (u32)buf;
  821. desc->reserved = 0;
  822. desc->attr = attr;
  823. }
  824. static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
  825. struct mmc_data *data)
  826. {
  827. uint total_len = data->blocksize * data->blocks;
  828. uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
  829. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  830. int i = desc_count;
  831. char *buf;
  832. priv->desc_slot = 0;
  833. priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
  834. memalign(ARCH_DMA_MINALIGN, desc_count *
  835. sizeof(struct omap_hsmmc_adma_desc));
  836. if (data->flags & MMC_DATA_READ)
  837. buf = data->dest;
  838. else
  839. buf = (char *)data->src;
  840. while (--i) {
  841. omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
  842. buf += ADMA_MAX_LEN;
  843. total_len -= ADMA_MAX_LEN;
  844. }
  845. omap_hsmmc_adma_desc(mmc, buf, total_len, true);
  846. flush_dcache_range((long)priv->adma_desc_table,
  847. (long)priv->adma_desc_table +
  848. ROUND(desc_count *
  849. sizeof(struct omap_hsmmc_adma_desc),
  850. ARCH_DMA_MINALIGN));
  851. }
  852. static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
  853. {
  854. struct hsmmc *mmc_base;
  855. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  856. u32 val;
  857. char *buf;
  858. mmc_base = priv->base_addr;
  859. omap_hsmmc_prepare_adma_table(mmc, data);
  860. if (data->flags & MMC_DATA_READ)
  861. buf = data->dest;
  862. else
  863. buf = (char *)data->src;
  864. val = readl(&mmc_base->hctl);
  865. val |= DMA_SELECT;
  866. writel(val, &mmc_base->hctl);
  867. val = readl(&mmc_base->con);
  868. val |= DMA_MASTER;
  869. writel(val, &mmc_base->con);
  870. writel((u32)priv->adma_desc_table, &mmc_base->admasal);
  871. flush_dcache_range((u32)buf,
  872. (u32)buf +
  873. ROUND(data->blocksize * data->blocks,
  874. ARCH_DMA_MINALIGN));
  875. }
  876. static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
  877. {
  878. struct hsmmc *mmc_base;
  879. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  880. u32 val;
  881. mmc_base = priv->base_addr;
  882. val = readl(&mmc_base->con);
  883. val &= ~DMA_MASTER;
  884. writel(val, &mmc_base->con);
  885. val = readl(&mmc_base->hctl);
  886. val &= ~DMA_SELECT;
  887. writel(val, &mmc_base->hctl);
  888. kfree(priv->adma_desc_table);
  889. }
  890. #else
  891. #define omap_hsmmc_adma_desc
  892. #define omap_hsmmc_prepare_adma_table
  893. #define omap_hsmmc_prepare_data
  894. #define omap_hsmmc_dma_cleanup
  895. #endif
  896. #if !CONFIG_IS_ENABLED(DM_MMC)
  897. static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  898. struct mmc_data *data)
  899. {
  900. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  901. #else
  902. static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  903. struct mmc_data *data)
  904. {
  905. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  906. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  907. struct mmc *mmc = upriv->mmc;
  908. #endif
  909. struct hsmmc *mmc_base;
  910. unsigned int flags, mmc_stat;
  911. ulong start;
  912. priv->last_cmd = cmd->cmdidx;
  913. mmc_base = priv->base_addr;
  914. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  915. return 0;
  916. start = get_timer(0);
  917. while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
  918. if (get_timer(0) - start > MAX_RETRY_MS) {
  919. printf("%s: timedout waiting on cmd inhibit to clear\n",
  920. __func__);
  921. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  922. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  923. return -ETIMEDOUT;
  924. }
  925. }
  926. writel(0xFFFFFFFF, &mmc_base->stat);
  927. if (readl(&mmc_base->stat)) {
  928. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  929. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  930. }
  931. /*
  932. * CMDREG
  933. * CMDIDX[13:8] : Command index
  934. * DATAPRNT[5] : Data Present Select
  935. * ENCMDIDX[4] : Command Index Check Enable
  936. * ENCMDCRC[3] : Command CRC Check Enable
  937. * RSPTYP[1:0]
  938. * 00 = No Response
  939. * 01 = Length 136
  940. * 10 = Length 48
  941. * 11 = Length 48 Check busy after response
  942. */
  943. /* Delay added before checking the status of frq change
  944. * retry not supported by mmc.c(core file)
  945. */
  946. if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
  947. udelay(50000); /* wait 50 ms */
  948. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  949. flags = 0;
  950. else if (cmd->resp_type & MMC_RSP_136)
  951. flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
  952. else if (cmd->resp_type & MMC_RSP_BUSY)
  953. flags = RSP_TYPE_LGHT48B;
  954. else
  955. flags = RSP_TYPE_LGHT48;
  956. /* enable default flags */
  957. flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
  958. MSBS_SGLEBLK);
  959. flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
  960. if (cmd->resp_type & MMC_RSP_CRC)
  961. flags |= CCCE_CHECK;
  962. if (cmd->resp_type & MMC_RSP_OPCODE)
  963. flags |= CICE_CHECK;
  964. if (data) {
  965. if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
  966. (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
  967. flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
  968. data->blocksize = 512;
  969. writel(data->blocksize | (data->blocks << 16),
  970. &mmc_base->blk);
  971. } else
  972. writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
  973. if (data->flags & MMC_DATA_READ)
  974. flags |= (DP_DATA | DDIR_READ);
  975. else
  976. flags |= (DP_DATA | DDIR_WRITE);
  977. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  978. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
  979. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  980. omap_hsmmc_prepare_data(mmc, data);
  981. flags |= DE_ENABLE;
  982. }
  983. #endif
  984. }
  985. mmc_enable_irq(mmc, cmd);
  986. writel(cmd->cmdarg, &mmc_base->arg);
  987. udelay(20); /* To fix "No status update" error on eMMC */
  988. writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
  989. start = get_timer(0);
  990. do {
  991. mmc_stat = readl(&mmc_base->stat);
  992. if (get_timer(start) > MAX_RETRY_MS) {
  993. printf("%s : timeout: No status update\n", __func__);
  994. return -ETIMEDOUT;
  995. }
  996. } while (!mmc_stat);
  997. if ((mmc_stat & IE_CTO) != 0) {
  998. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  999. return -ETIMEDOUT;
  1000. } else if ((mmc_stat & ERRI_MASK) != 0)
  1001. return -1;
  1002. if (mmc_stat & CC_MASK) {
  1003. writel(CC_MASK, &mmc_base->stat);
  1004. if (cmd->resp_type & MMC_RSP_PRESENT) {
  1005. if (cmd->resp_type & MMC_RSP_136) {
  1006. /* response type 2 */
  1007. cmd->response[3] = readl(&mmc_base->rsp10);
  1008. cmd->response[2] = readl(&mmc_base->rsp32);
  1009. cmd->response[1] = readl(&mmc_base->rsp54);
  1010. cmd->response[0] = readl(&mmc_base->rsp76);
  1011. } else
  1012. /* response types 1, 1b, 3, 4, 5, 6 */
  1013. cmd->response[0] = readl(&mmc_base->rsp10);
  1014. }
  1015. }
  1016. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  1017. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
  1018. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  1019. u32 sz_mb, timeout;
  1020. if (mmc_stat & IE_ADMAE) {
  1021. omap_hsmmc_dma_cleanup(mmc);
  1022. return -EIO;
  1023. }
  1024. sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
  1025. timeout = sz_mb * DMA_TIMEOUT_PER_MB;
  1026. if (timeout < MAX_RETRY_MS)
  1027. timeout = MAX_RETRY_MS;
  1028. start = get_timer(0);
  1029. do {
  1030. mmc_stat = readl(&mmc_base->stat);
  1031. if (mmc_stat & TC_MASK) {
  1032. writel(readl(&mmc_base->stat) | TC_MASK,
  1033. &mmc_base->stat);
  1034. break;
  1035. }
  1036. if (get_timer(start) > timeout) {
  1037. printf("%s : DMA timeout: No status update\n",
  1038. __func__);
  1039. return -ETIMEDOUT;
  1040. }
  1041. } while (1);
  1042. omap_hsmmc_dma_cleanup(mmc);
  1043. return 0;
  1044. }
  1045. #endif
  1046. if (data && (data->flags & MMC_DATA_READ)) {
  1047. mmc_read_data(mmc_base, data->dest,
  1048. data->blocksize * data->blocks);
  1049. } else if (data && (data->flags & MMC_DATA_WRITE)) {
  1050. mmc_write_data(mmc_base, data->src,
  1051. data->blocksize * data->blocks);
  1052. }
  1053. return 0;
  1054. }
  1055. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
  1056. {
  1057. unsigned int *output_buf = (unsigned int *)buf;
  1058. unsigned int mmc_stat;
  1059. unsigned int count;
  1060. /*
  1061. * Start Polled Read
  1062. */
  1063. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1064. count /= 4;
  1065. while (size) {
  1066. ulong start = get_timer(0);
  1067. do {
  1068. mmc_stat = readl(&mmc_base->stat);
  1069. if (get_timer(0) - start > MAX_RETRY_MS) {
  1070. printf("%s: timedout waiting for status!\n",
  1071. __func__);
  1072. return -ETIMEDOUT;
  1073. }
  1074. } while (mmc_stat == 0);
  1075. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1076. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1077. if ((mmc_stat & ERRI_MASK) != 0)
  1078. return 1;
  1079. if (mmc_stat & BRR_MASK) {
  1080. unsigned int k;
  1081. writel(readl(&mmc_base->stat) | BRR_MASK,
  1082. &mmc_base->stat);
  1083. for (k = 0; k < count; k++) {
  1084. *output_buf = readl(&mmc_base->data);
  1085. output_buf++;
  1086. }
  1087. size -= (count*4);
  1088. }
  1089. if (mmc_stat & BWR_MASK)
  1090. writel(readl(&mmc_base->stat) | BWR_MASK,
  1091. &mmc_base->stat);
  1092. if (mmc_stat & TC_MASK) {
  1093. writel(readl(&mmc_base->stat) | TC_MASK,
  1094. &mmc_base->stat);
  1095. break;
  1096. }
  1097. }
  1098. return 0;
  1099. }
  1100. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1101. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1102. unsigned int size)
  1103. {
  1104. unsigned int *input_buf = (unsigned int *)buf;
  1105. unsigned int mmc_stat;
  1106. unsigned int count;
  1107. /*
  1108. * Start Polled Write
  1109. */
  1110. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1111. count /= 4;
  1112. while (size) {
  1113. ulong start = get_timer(0);
  1114. do {
  1115. mmc_stat = readl(&mmc_base->stat);
  1116. if (get_timer(0) - start > MAX_RETRY_MS) {
  1117. printf("%s: timedout waiting for status!\n",
  1118. __func__);
  1119. return -ETIMEDOUT;
  1120. }
  1121. } while (mmc_stat == 0);
  1122. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1123. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1124. if ((mmc_stat & ERRI_MASK) != 0)
  1125. return 1;
  1126. if (mmc_stat & BWR_MASK) {
  1127. unsigned int k;
  1128. writel(readl(&mmc_base->stat) | BWR_MASK,
  1129. &mmc_base->stat);
  1130. for (k = 0; k < count; k++) {
  1131. writel(*input_buf, &mmc_base->data);
  1132. input_buf++;
  1133. }
  1134. size -= (count*4);
  1135. }
  1136. if (mmc_stat & BRR_MASK)
  1137. writel(readl(&mmc_base->stat) | BRR_MASK,
  1138. &mmc_base->stat);
  1139. if (mmc_stat & TC_MASK) {
  1140. writel(readl(&mmc_base->stat) | TC_MASK,
  1141. &mmc_base->stat);
  1142. break;
  1143. }
  1144. }
  1145. return 0;
  1146. }
  1147. #else
  1148. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1149. unsigned int size)
  1150. {
  1151. return -ENOTSUPP;
  1152. }
  1153. #endif
  1154. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
  1155. {
  1156. writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
  1157. }
  1158. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
  1159. {
  1160. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  1161. }
  1162. static void omap_hsmmc_set_clock(struct mmc *mmc)
  1163. {
  1164. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1165. struct hsmmc *mmc_base;
  1166. unsigned int dsor = 0;
  1167. ulong start;
  1168. mmc_base = priv->base_addr;
  1169. omap_hsmmc_stop_clock(mmc_base);
  1170. /* TODO: Is setting DTO required here? */
  1171. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
  1172. (ICE_STOP | DTO_15THDTO));
  1173. if (mmc->clock != 0) {
  1174. dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
  1175. if (dsor > CLKD_MAX)
  1176. dsor = CLKD_MAX;
  1177. } else {
  1178. dsor = CLKD_MAX;
  1179. }
  1180. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  1181. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  1182. start = get_timer(0);
  1183. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  1184. if (get_timer(0) - start > MAX_RETRY_MS) {
  1185. printf("%s: timedout waiting for ics!\n", __func__);
  1186. return;
  1187. }
  1188. }
  1189. priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
  1190. mmc->clock = priv->clock;
  1191. omap_hsmmc_start_clock(mmc_base);
  1192. }
  1193. static void omap_hsmmc_set_bus_width(struct mmc *mmc)
  1194. {
  1195. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1196. struct hsmmc *mmc_base;
  1197. mmc_base = priv->base_addr;
  1198. /* configue bus width */
  1199. switch (mmc->bus_width) {
  1200. case 8:
  1201. writel(readl(&mmc_base->con) | DTW_8_BITMODE,
  1202. &mmc_base->con);
  1203. break;
  1204. case 4:
  1205. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1206. &mmc_base->con);
  1207. writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
  1208. &mmc_base->hctl);
  1209. break;
  1210. case 1:
  1211. default:
  1212. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1213. &mmc_base->con);
  1214. writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
  1215. &mmc_base->hctl);
  1216. break;
  1217. }
  1218. priv->bus_width = mmc->bus_width;
  1219. }
  1220. #if !CONFIG_IS_ENABLED(DM_MMC)
  1221. static int omap_hsmmc_set_ios(struct mmc *mmc)
  1222. {
  1223. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1224. #else
  1225. static int omap_hsmmc_set_ios(struct udevice *dev)
  1226. {
  1227. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1228. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1229. struct mmc *mmc = upriv->mmc;
  1230. #endif
  1231. struct hsmmc *mmc_base = priv->base_addr;
  1232. int ret = 0;
  1233. if (priv->bus_width != mmc->bus_width)
  1234. omap_hsmmc_set_bus_width(mmc);
  1235. if (priv->clock != mmc->clock)
  1236. omap_hsmmc_set_clock(mmc);
  1237. if (mmc->clk_disable)
  1238. omap_hsmmc_stop_clock(mmc_base);
  1239. else
  1240. omap_hsmmc_start_clock(mmc_base);
  1241. #if CONFIG_IS_ENABLED(DM_MMC)
  1242. if (priv->mode != mmc->selected_mode)
  1243. omap_hsmmc_set_timing(mmc);
  1244. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1245. if (priv->signal_voltage != mmc->signal_voltage)
  1246. ret = omap_hsmmc_set_signal_voltage(mmc);
  1247. #endif
  1248. #endif
  1249. return ret;
  1250. }
  1251. #ifdef OMAP_HSMMC_USE_GPIO
  1252. #if CONFIG_IS_ENABLED(DM_MMC)
  1253. static int omap_hsmmc_getcd(struct udevice *dev)
  1254. {
  1255. int value = -1;
  1256. #if CONFIG_IS_ENABLED(DM_GPIO)
  1257. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1258. value = dm_gpio_get_value(&priv->cd_gpio);
  1259. #endif
  1260. /* if no CD return as 1 */
  1261. if (value < 0)
  1262. return 1;
  1263. return value;
  1264. }
  1265. static int omap_hsmmc_getwp(struct udevice *dev)
  1266. {
  1267. int value = 0;
  1268. #if CONFIG_IS_ENABLED(DM_GPIO)
  1269. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1270. value = dm_gpio_get_value(&priv->wp_gpio);
  1271. #endif
  1272. /* if no WP return as 0 */
  1273. if (value < 0)
  1274. return 0;
  1275. return value;
  1276. }
  1277. #else
  1278. static int omap_hsmmc_getcd(struct mmc *mmc)
  1279. {
  1280. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1281. int cd_gpio;
  1282. /* if no CD return as 1 */
  1283. cd_gpio = priv->cd_gpio;
  1284. if (cd_gpio < 0)
  1285. return 1;
  1286. /* NOTE: assumes card detect signal is active-low */
  1287. return !gpio_get_value(cd_gpio);
  1288. }
  1289. static int omap_hsmmc_getwp(struct mmc *mmc)
  1290. {
  1291. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1292. int wp_gpio;
  1293. /* if no WP return as 0 */
  1294. wp_gpio = priv->wp_gpio;
  1295. if (wp_gpio < 0)
  1296. return 0;
  1297. /* NOTE: assumes write protect signal is active-high */
  1298. return gpio_get_value(wp_gpio);
  1299. }
  1300. #endif
  1301. #endif
  1302. #if CONFIG_IS_ENABLED(DM_MMC)
  1303. static const struct dm_mmc_ops omap_hsmmc_ops = {
  1304. .send_cmd = omap_hsmmc_send_cmd,
  1305. .set_ios = omap_hsmmc_set_ios,
  1306. #ifdef OMAP_HSMMC_USE_GPIO
  1307. .get_cd = omap_hsmmc_getcd,
  1308. .get_wp = omap_hsmmc_getwp,
  1309. #endif
  1310. #ifdef MMC_SUPPORTS_TUNING
  1311. .execute_tuning = omap_hsmmc_execute_tuning,
  1312. #endif
  1313. .wait_dat0 = omap_hsmmc_wait_dat0,
  1314. };
  1315. #else
  1316. static const struct mmc_ops omap_hsmmc_ops = {
  1317. .send_cmd = omap_hsmmc_send_cmd,
  1318. .set_ios = omap_hsmmc_set_ios,
  1319. .init = omap_hsmmc_init_setup,
  1320. #ifdef OMAP_HSMMC_USE_GPIO
  1321. .getcd = omap_hsmmc_getcd,
  1322. .getwp = omap_hsmmc_getwp,
  1323. #endif
  1324. };
  1325. #endif
  1326. #if !CONFIG_IS_ENABLED(DM_MMC)
  1327. int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
  1328. int wp_gpio)
  1329. {
  1330. struct mmc *mmc;
  1331. struct omap_hsmmc_data *priv;
  1332. struct mmc_config *cfg;
  1333. uint host_caps_val;
  1334. priv = calloc(1, sizeof(*priv));
  1335. if (priv == NULL)
  1336. return -1;
  1337. host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1338. switch (dev_index) {
  1339. case 0:
  1340. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1341. break;
  1342. #ifdef OMAP_HSMMC2_BASE
  1343. case 1:
  1344. priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
  1345. #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  1346. defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
  1347. defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
  1348. defined(CONFIG_HSMMC2_8BIT)
  1349. /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
  1350. host_caps_val |= MMC_MODE_8BIT;
  1351. #endif
  1352. break;
  1353. #endif
  1354. #ifdef OMAP_HSMMC3_BASE
  1355. case 2:
  1356. priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
  1357. #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
  1358. /* Enable 8-bit interface for eMMC on DRA7XX */
  1359. host_caps_val |= MMC_MODE_8BIT;
  1360. #endif
  1361. break;
  1362. #endif
  1363. default:
  1364. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1365. return 1;
  1366. }
  1367. #ifdef OMAP_HSMMC_USE_GPIO
  1368. /* on error gpio values are set to -1, which is what we want */
  1369. priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
  1370. priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
  1371. #endif
  1372. cfg = &priv->cfg;
  1373. cfg->name = "OMAP SD/MMC";
  1374. cfg->ops = &omap_hsmmc_ops;
  1375. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1376. cfg->host_caps = host_caps_val & ~host_caps_mask;
  1377. cfg->f_min = 400000;
  1378. if (f_max != 0)
  1379. cfg->f_max = f_max;
  1380. else {
  1381. if (cfg->host_caps & MMC_MODE_HS) {
  1382. if (cfg->host_caps & MMC_MODE_HS_52MHz)
  1383. cfg->f_max = 52000000;
  1384. else
  1385. cfg->f_max = 26000000;
  1386. } else
  1387. cfg->f_max = 20000000;
  1388. }
  1389. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1390. #if defined(CONFIG_OMAP34XX)
  1391. /*
  1392. * Silicon revs 2.1 and older do not support multiblock transfers.
  1393. */
  1394. if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
  1395. cfg->b_max = 1;
  1396. #endif
  1397. mmc = mmc_create(cfg, priv);
  1398. if (mmc == NULL)
  1399. return -1;
  1400. return 0;
  1401. }
  1402. #else
  1403. #ifdef CONFIG_IODELAY_RECALIBRATION
  1404. static struct pad_conf_entry *
  1405. omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
  1406. {
  1407. int index = 0;
  1408. struct pad_conf_entry *padconf;
  1409. padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
  1410. if (!padconf) {
  1411. debug("failed to allocate memory\n");
  1412. return 0;
  1413. }
  1414. while (index < count) {
  1415. padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
  1416. padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
  1417. index++;
  1418. }
  1419. return padconf;
  1420. }
  1421. static struct iodelay_cfg_entry *
  1422. omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
  1423. {
  1424. int index = 0;
  1425. struct iodelay_cfg_entry *iodelay;
  1426. iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
  1427. if (!iodelay) {
  1428. debug("failed to allocate memory\n");
  1429. return 0;
  1430. }
  1431. while (index < count) {
  1432. iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
  1433. iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
  1434. iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
  1435. index++;
  1436. }
  1437. return iodelay;
  1438. }
  1439. static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
  1440. const char *name, int *len)
  1441. {
  1442. const void *fdt = gd->fdt_blob;
  1443. int offset;
  1444. const fdt32_t *pinctrl;
  1445. offset = fdt_node_offset_by_phandle(fdt, phandle);
  1446. if (offset < 0) {
  1447. debug("failed to get pinctrl node %s.\n",
  1448. fdt_strerror(offset));
  1449. return 0;
  1450. }
  1451. pinctrl = fdt_getprop(fdt, offset, name, len);
  1452. if (!pinctrl) {
  1453. debug("failed to get property %s\n", name);
  1454. return 0;
  1455. }
  1456. return pinctrl;
  1457. }
  1458. static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
  1459. char *prop_name)
  1460. {
  1461. const void *fdt = gd->fdt_blob;
  1462. const __be32 *phandle;
  1463. int node = dev_of_offset(mmc->dev);
  1464. phandle = fdt_getprop(fdt, node, prop_name, NULL);
  1465. if (!phandle) {
  1466. debug("failed to get property %s\n", prop_name);
  1467. return 0;
  1468. }
  1469. return fdt32_to_cpu(*phandle);
  1470. }
  1471. static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
  1472. char *prop_name)
  1473. {
  1474. const void *fdt = gd->fdt_blob;
  1475. const __be32 *phandle;
  1476. int len;
  1477. int count;
  1478. int node = dev_of_offset(mmc->dev);
  1479. phandle = fdt_getprop(fdt, node, prop_name, &len);
  1480. if (!phandle) {
  1481. debug("failed to get property %s\n", prop_name);
  1482. return 0;
  1483. }
  1484. /* No manual mode iodelay values if count < 2 */
  1485. count = len / sizeof(*phandle);
  1486. if (count < 2)
  1487. return 0;
  1488. return fdt32_to_cpu(*(phandle + 1));
  1489. }
  1490. static struct pad_conf_entry *
  1491. omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
  1492. {
  1493. int len;
  1494. int count;
  1495. struct pad_conf_entry *padconf;
  1496. u32 phandle;
  1497. const fdt32_t *pinctrl;
  1498. phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
  1499. if (!phandle)
  1500. return ERR_PTR(-EINVAL);
  1501. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
  1502. &len);
  1503. if (!pinctrl)
  1504. return ERR_PTR(-EINVAL);
  1505. count = (len / sizeof(*pinctrl)) / 2;
  1506. padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
  1507. if (!padconf)
  1508. return ERR_PTR(-EINVAL);
  1509. *npads = count;
  1510. return padconf;
  1511. }
  1512. static struct iodelay_cfg_entry *
  1513. omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
  1514. {
  1515. int len;
  1516. int count;
  1517. struct iodelay_cfg_entry *iodelay;
  1518. u32 phandle;
  1519. const fdt32_t *pinctrl;
  1520. phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
  1521. /* Not all modes have manual mode iodelay values. So its not fatal */
  1522. if (!phandle)
  1523. return 0;
  1524. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
  1525. &len);
  1526. if (!pinctrl)
  1527. return ERR_PTR(-EINVAL);
  1528. count = (len / sizeof(*pinctrl)) / 3;
  1529. iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
  1530. if (!iodelay)
  1531. return ERR_PTR(-EINVAL);
  1532. *niodelay = count;
  1533. return iodelay;
  1534. }
  1535. static struct omap_hsmmc_pinctrl_state *
  1536. omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
  1537. {
  1538. int index;
  1539. int npads = 0;
  1540. int niodelays = 0;
  1541. const void *fdt = gd->fdt_blob;
  1542. int node = dev_of_offset(mmc->dev);
  1543. char prop_name[11];
  1544. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  1545. pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
  1546. malloc(sizeof(*pinctrl_state));
  1547. if (!pinctrl_state) {
  1548. debug("failed to allocate memory\n");
  1549. return 0;
  1550. }
  1551. index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
  1552. if (index < 0) {
  1553. debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
  1554. goto err_pinctrl_state;
  1555. }
  1556. sprintf(prop_name, "pinctrl-%d", index);
  1557. pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
  1558. &npads);
  1559. if (IS_ERR(pinctrl_state->padconf))
  1560. goto err_pinctrl_state;
  1561. pinctrl_state->npads = npads;
  1562. pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
  1563. &niodelays);
  1564. if (IS_ERR(pinctrl_state->iodelay))
  1565. goto err_padconf;
  1566. pinctrl_state->niodelays = niodelays;
  1567. return pinctrl_state;
  1568. err_padconf:
  1569. kfree(pinctrl_state->padconf);
  1570. err_pinctrl_state:
  1571. kfree(pinctrl_state);
  1572. return 0;
  1573. }
  1574. #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
  1575. do { \
  1576. struct omap_hsmmc_pinctrl_state *s = NULL; \
  1577. char str[20]; \
  1578. if (!(cfg->host_caps & capmask)) \
  1579. break; \
  1580. \
  1581. if (priv->hw_rev) { \
  1582. sprintf(str, "%s-%s", #mode, priv->hw_rev); \
  1583. s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
  1584. } \
  1585. \
  1586. if (!s) \
  1587. s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
  1588. \
  1589. if (!s && !optional) { \
  1590. debug("%s: no pinctrl for %s\n", \
  1591. mmc->dev->name, #mode); \
  1592. cfg->host_caps &= ~(capmask); \
  1593. } else { \
  1594. priv->mode##_pinctrl_state = s; \
  1595. } \
  1596. } while (0)
  1597. static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
  1598. {
  1599. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1600. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  1601. struct omap_hsmmc_pinctrl_state *default_pinctrl;
  1602. if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
  1603. return 0;
  1604. default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
  1605. if (!default_pinctrl) {
  1606. printf("no pinctrl state for default mode\n");
  1607. return -EINVAL;
  1608. }
  1609. priv->default_pinctrl_state = default_pinctrl;
  1610. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
  1611. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
  1612. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
  1613. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
  1614. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
  1615. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
  1616. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
  1617. OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
  1618. return 0;
  1619. }
  1620. #endif
  1621. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1622. #ifdef CONFIG_OMAP54XX
  1623. __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  1624. {
  1625. return NULL;
  1626. }
  1627. #endif
  1628. static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
  1629. {
  1630. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1631. struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
  1632. struct mmc_config *cfg = &plat->cfg;
  1633. #ifdef CONFIG_OMAP54XX
  1634. const struct mmc_platform_fixups *fixups;
  1635. #endif
  1636. const void *fdt = gd->fdt_blob;
  1637. int node = dev_of_offset(dev);
  1638. int ret;
  1639. plat->base_addr = map_physmem(devfdt_get_addr(dev),
  1640. sizeof(struct hsmmc *),
  1641. MAP_NOCACHE);
  1642. ret = mmc_of_parse(dev, cfg);
  1643. if (ret < 0)
  1644. return ret;
  1645. if (!cfg->f_max)
  1646. cfg->f_max = 52000000;
  1647. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1648. cfg->f_min = 400000;
  1649. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1650. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1651. if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
  1652. plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1653. if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
  1654. plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
  1655. if (of_data)
  1656. plat->controller_flags |= of_data->controller_flags;
  1657. #ifdef CONFIG_OMAP54XX
  1658. fixups = platform_fixups_mmc(devfdt_get_addr(dev));
  1659. if (fixups) {
  1660. plat->hw_rev = fixups->hw_rev;
  1661. cfg->host_caps &= ~fixups->unsupported_caps;
  1662. cfg->f_max = fixups->max_freq;
  1663. }
  1664. #endif
  1665. return 0;
  1666. }
  1667. #endif
  1668. #ifdef CONFIG_BLK
  1669. static int omap_hsmmc_bind(struct udevice *dev)
  1670. {
  1671. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1672. plat->mmc = calloc(1, sizeof(struct mmc));
  1673. return mmc_bind(dev, plat->mmc, &plat->cfg);
  1674. }
  1675. #endif
  1676. static int omap_hsmmc_probe(struct udevice *dev)
  1677. {
  1678. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1679. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1680. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1681. struct mmc_config *cfg = &plat->cfg;
  1682. struct mmc *mmc;
  1683. #ifdef CONFIG_IODELAY_RECALIBRATION
  1684. int ret;
  1685. #endif
  1686. cfg->name = "OMAP SD/MMC";
  1687. priv->base_addr = plat->base_addr;
  1688. priv->controller_flags = plat->controller_flags;
  1689. priv->hw_rev = plat->hw_rev;
  1690. #ifdef CONFIG_BLK
  1691. mmc = plat->mmc;
  1692. #else
  1693. mmc = mmc_create(cfg, priv);
  1694. if (mmc == NULL)
  1695. return -1;
  1696. #endif
  1697. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1698. device_get_supply_regulator(dev, "pbias-supply",
  1699. &priv->pbias_supply);
  1700. #endif
  1701. #if defined(OMAP_HSMMC_USE_GPIO)
  1702. #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
  1703. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  1704. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  1705. #endif
  1706. #endif
  1707. mmc->dev = dev;
  1708. upriv->mmc = mmc;
  1709. #ifdef CONFIG_IODELAY_RECALIBRATION
  1710. ret = omap_hsmmc_get_pinctrl_state(mmc);
  1711. /*
  1712. * disable high speed modes for the platforms that require IO delay
  1713. * and for which we don't have this information
  1714. */
  1715. if ((ret < 0) &&
  1716. (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
  1717. priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
  1718. cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
  1719. UHS_CAPS);
  1720. }
  1721. #endif
  1722. return omap_hsmmc_init_setup(mmc);
  1723. }
  1724. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1725. static const struct omap_mmc_of_data dra7_mmc_of_data = {
  1726. .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
  1727. };
  1728. static const struct udevice_id omap_hsmmc_ids[] = {
  1729. { .compatible = "ti,omap3-hsmmc" },
  1730. { .compatible = "ti,omap4-hsmmc" },
  1731. { .compatible = "ti,am33xx-hsmmc" },
  1732. { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
  1733. { }
  1734. };
  1735. #endif
  1736. U_BOOT_DRIVER(omap_hsmmc) = {
  1737. .name = "omap_hsmmc",
  1738. .id = UCLASS_MMC,
  1739. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1740. .of_match = omap_hsmmc_ids,
  1741. .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
  1742. .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
  1743. #endif
  1744. #ifdef CONFIG_BLK
  1745. .bind = omap_hsmmc_bind,
  1746. #endif
  1747. .ops = &omap_hsmmc_ops,
  1748. .probe = omap_hsmmc_probe,
  1749. .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
  1750. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  1751. .flags = DM_FLAG_PRE_RELOC,
  1752. #endif
  1753. };
  1754. #endif