fsl_esdhc_imx.c 41 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019 NXP Semiconductors
  5. * Andy Fleming
  6. * Yangbo Lu <yangbo.lu@nxp.com>
  7. *
  8. * Based vaguely on the pxa mmc code:
  9. * (C) Copyright 2003
  10. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <command.h>
  15. #include <clk.h>
  16. #include <cpu_func.h>
  17. #include <errno.h>
  18. #include <hwconfig.h>
  19. #include <mmc.h>
  20. #include <part.h>
  21. #include <linux/err.h>
  22. #include <power/regulator.h>
  23. #include <malloc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <fdt_support.h>
  26. #include <asm/io.h>
  27. #include <dm.h>
  28. #include <asm-generic/gpio.h>
  29. #include <dm/pinctrl.h>
  30. #if !CONFIG_IS_ENABLED(BLK)
  31. #include "mmc_private.h"
  32. #endif
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  35. IRQSTATEN_CINT | \
  36. IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  37. IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  38. IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  39. IRQSTATEN_DINT)
  40. #define MAX_TUNING_LOOP 40
  41. #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
  42. struct fsl_esdhc {
  43. uint dsaddr; /* SDMA system address register */
  44. uint blkattr; /* Block attributes register */
  45. uint cmdarg; /* Command argument register */
  46. uint xfertyp; /* Transfer type register */
  47. uint cmdrsp0; /* Command response 0 register */
  48. uint cmdrsp1; /* Command response 1 register */
  49. uint cmdrsp2; /* Command response 2 register */
  50. uint cmdrsp3; /* Command response 3 register */
  51. uint datport; /* Buffer data port register */
  52. uint prsstat; /* Present state register */
  53. uint proctl; /* Protocol control register */
  54. uint sysctl; /* System Control Register */
  55. uint irqstat; /* Interrupt status register */
  56. uint irqstaten; /* Interrupt status enable register */
  57. uint irqsigen; /* Interrupt signal enable register */
  58. uint autoc12err; /* Auto CMD error status register */
  59. uint hostcapblt; /* Host controller capabilities register */
  60. uint wml; /* Watermark level register */
  61. uint mixctrl; /* For USDHC */
  62. char reserved1[4]; /* reserved */
  63. uint fevt; /* Force event register */
  64. uint admaes; /* ADMA error status register */
  65. uint adsaddr; /* ADMA system address register */
  66. char reserved2[4];
  67. uint dllctrl;
  68. uint dllstat;
  69. uint clktunectrlstatus;
  70. char reserved3[4];
  71. uint strobe_dllctrl;
  72. uint strobe_dllstat;
  73. char reserved4[72];
  74. uint vendorspec;
  75. uint mmcboot;
  76. uint vendorspec2;
  77. uint tuning_ctrl; /* on i.MX6/7/8/RT */
  78. char reserved5[44];
  79. uint hostver; /* Host controller version register */
  80. char reserved6[4]; /* reserved */
  81. uint dmaerraddr; /* DMA error address register */
  82. char reserved7[4]; /* reserved */
  83. uint dmaerrattr; /* DMA error attribute register */
  84. char reserved8[4]; /* reserved */
  85. uint hostcapblt2; /* Host controller capabilities register 2 */
  86. char reserved9[8]; /* reserved */
  87. uint tcr; /* Tuning control register */
  88. char reserved10[28]; /* reserved */
  89. uint sddirctl; /* SD direction control register */
  90. char reserved11[712];/* reserved */
  91. uint scr; /* eSDHC control register */
  92. };
  93. struct fsl_esdhc_plat {
  94. struct mmc_config cfg;
  95. struct mmc mmc;
  96. };
  97. struct esdhc_soc_data {
  98. u32 flags;
  99. };
  100. /**
  101. * struct fsl_esdhc_priv
  102. *
  103. * @esdhc_regs: registers of the sdhc controller
  104. * @sdhc_clk: Current clk of the sdhc controller
  105. * @bus_width: bus width, 1bit, 4bit or 8bit
  106. * @cfg: mmc config
  107. * @mmc: mmc
  108. * Following is used when Driver Model is enabled for MMC
  109. * @dev: pointer for the device
  110. * @non_removable: 0: removable; 1: non-removable
  111. * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
  112. * @wp_enable: 1: enable checking wp; 0: no check
  113. * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  114. * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
  115. * @caps: controller capabilities
  116. * @tuning_step: tuning step setting in tuning_ctrl register
  117. * @start_tuning_tap: the start point for tuning in tuning_ctrl register
  118. * @strobe_dll_delay_target: settings in strobe_dllctrl
  119. * @signal_voltage: indicating the current voltage
  120. * @cd_gpio: gpio for card detection
  121. * @wp_gpio: gpio for write protection
  122. */
  123. struct fsl_esdhc_priv {
  124. struct fsl_esdhc *esdhc_regs;
  125. unsigned int sdhc_clk;
  126. struct clk per_clk;
  127. unsigned int clock;
  128. unsigned int mode;
  129. unsigned int bus_width;
  130. #if !CONFIG_IS_ENABLED(BLK)
  131. struct mmc *mmc;
  132. #endif
  133. struct udevice *dev;
  134. int non_removable;
  135. int broken_cd;
  136. int wp_enable;
  137. int vs18_enable;
  138. u32 flags;
  139. u32 caps;
  140. u32 tuning_step;
  141. u32 tuning_start_tap;
  142. u32 strobe_dll_delay_target;
  143. u32 signal_voltage;
  144. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  145. struct udevice *vqmmc_dev;
  146. struct udevice *vmmc_dev;
  147. #endif
  148. #if CONFIG_IS_ENABLED(DM_GPIO)
  149. struct gpio_desc cd_gpio;
  150. struct gpio_desc wp_gpio;
  151. #endif
  152. };
  153. /* Return the XFERTYP flags for a given command and data packet */
  154. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  155. {
  156. uint xfertyp = 0;
  157. if (data) {
  158. xfertyp |= XFERTYP_DPSEL;
  159. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  160. xfertyp |= XFERTYP_DMAEN;
  161. #endif
  162. if (data->blocks > 1) {
  163. xfertyp |= XFERTYP_MSBSEL;
  164. xfertyp |= XFERTYP_BCEN;
  165. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  166. xfertyp |= XFERTYP_AC12EN;
  167. #endif
  168. }
  169. if (data->flags & MMC_DATA_READ)
  170. xfertyp |= XFERTYP_DTDSEL;
  171. }
  172. if (cmd->resp_type & MMC_RSP_CRC)
  173. xfertyp |= XFERTYP_CCCEN;
  174. if (cmd->resp_type & MMC_RSP_OPCODE)
  175. xfertyp |= XFERTYP_CICEN;
  176. if (cmd->resp_type & MMC_RSP_136)
  177. xfertyp |= XFERTYP_RSPTYP_136;
  178. else if (cmd->resp_type & MMC_RSP_BUSY)
  179. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  180. else if (cmd->resp_type & MMC_RSP_PRESENT)
  181. xfertyp |= XFERTYP_RSPTYP_48;
  182. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  183. xfertyp |= XFERTYP_CMDTYP_ABORT;
  184. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  185. }
  186. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  187. /*
  188. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  189. */
  190. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  191. struct mmc_data *data)
  192. {
  193. struct fsl_esdhc *regs = priv->esdhc_regs;
  194. uint blocks;
  195. char *buffer;
  196. uint databuf;
  197. uint size;
  198. uint irqstat;
  199. ulong start;
  200. if (data->flags & MMC_DATA_READ) {
  201. blocks = data->blocks;
  202. buffer = data->dest;
  203. while (blocks) {
  204. start = get_timer(0);
  205. size = data->blocksize;
  206. irqstat = esdhc_read32(&regs->irqstat);
  207. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  208. if (get_timer(start) > PIO_TIMEOUT) {
  209. printf("\nData Read Failed in PIO Mode.");
  210. return;
  211. }
  212. }
  213. while (size && (!(irqstat & IRQSTAT_TC))) {
  214. udelay(100); /* Wait before last byte transfer complete */
  215. irqstat = esdhc_read32(&regs->irqstat);
  216. databuf = in_le32(&regs->datport);
  217. *((uint *)buffer) = databuf;
  218. buffer += 4;
  219. size -= 4;
  220. }
  221. blocks--;
  222. }
  223. } else {
  224. blocks = data->blocks;
  225. buffer = (char *)data->src;
  226. while (blocks) {
  227. start = get_timer(0);
  228. size = data->blocksize;
  229. irqstat = esdhc_read32(&regs->irqstat);
  230. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  231. if (get_timer(start) > PIO_TIMEOUT) {
  232. printf("\nData Write Failed in PIO Mode.");
  233. return;
  234. }
  235. }
  236. while (size && (!(irqstat & IRQSTAT_TC))) {
  237. udelay(100); /* Wait before last byte transfer complete */
  238. databuf = *((uint *)buffer);
  239. buffer += 4;
  240. size -= 4;
  241. irqstat = esdhc_read32(&regs->irqstat);
  242. out_le32(&regs->datport, databuf);
  243. }
  244. blocks--;
  245. }
  246. }
  247. }
  248. #endif
  249. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  250. struct mmc_data *data)
  251. {
  252. int timeout;
  253. struct fsl_esdhc *regs = priv->esdhc_regs;
  254. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  255. dma_addr_t addr;
  256. #endif
  257. uint wml_value;
  258. wml_value = data->blocksize/4;
  259. if (data->flags & MMC_DATA_READ) {
  260. if (wml_value > WML_RD_WML_MAX)
  261. wml_value = WML_RD_WML_MAX_VAL;
  262. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  263. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  264. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  265. addr = virt_to_phys((void *)(data->dest));
  266. if (upper_32_bits(addr))
  267. printf("Error found for upper 32 bits\n");
  268. else
  269. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  270. #else
  271. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  272. #endif
  273. #endif
  274. } else {
  275. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  276. flush_dcache_range((ulong)data->src,
  277. (ulong)data->src+data->blocks
  278. *data->blocksize);
  279. #endif
  280. if (wml_value > WML_WR_WML_MAX)
  281. wml_value = WML_WR_WML_MAX_VAL;
  282. if (priv->wp_enable) {
  283. if ((esdhc_read32(&regs->prsstat) &
  284. PRSSTAT_WPSPL) == 0) {
  285. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  286. return -ETIMEDOUT;
  287. }
  288. } else {
  289. #if CONFIG_IS_ENABLED(DM_GPIO)
  290. if (dm_gpio_is_valid(&priv->wp_gpio) &&
  291. dm_gpio_get_value(&priv->wp_gpio)) {
  292. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  293. return -ETIMEDOUT;
  294. }
  295. #endif
  296. }
  297. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  298. wml_value << 16);
  299. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  300. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  301. addr = virt_to_phys((void *)(data->src));
  302. if (upper_32_bits(addr))
  303. printf("Error found for upper 32 bits\n");
  304. else
  305. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  306. #else
  307. esdhc_write32(&regs->dsaddr, (u32)data->src);
  308. #endif
  309. #endif
  310. }
  311. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  312. /* Calculate the timeout period for data transactions */
  313. /*
  314. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  315. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  316. * So, Number of SD Clock cycles for 0.25sec should be minimum
  317. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  318. * = (mmc->clock * 1/4) SD Clock cycles
  319. * As 1) >= 2)
  320. * => (2^(timeout+13)) >= mmc->clock * 1/4
  321. * Taking log2 both the sides
  322. * => timeout + 13 >= log2(mmc->clock/4)
  323. * Rounding up to next power of 2
  324. * => timeout + 13 = log2(mmc->clock/4) + 1
  325. * => timeout + 13 = fls(mmc->clock/4)
  326. *
  327. * However, the MMC spec "It is strongly recommended for hosts to
  328. * implement more than 500ms timeout value even if the card
  329. * indicates the 250ms maximum busy length." Even the previous
  330. * value of 300ms is known to be insufficient for some cards.
  331. * So, we use
  332. * => timeout + 13 = fls(mmc->clock/2)
  333. */
  334. timeout = fls(mmc->clock/2);
  335. timeout -= 13;
  336. if (timeout > 14)
  337. timeout = 14;
  338. if (timeout < 0)
  339. timeout = 0;
  340. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  341. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  342. timeout++;
  343. #endif
  344. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  345. timeout = 0xE;
  346. #endif
  347. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  348. return 0;
  349. }
  350. static void check_and_invalidate_dcache_range
  351. (struct mmc_cmd *cmd,
  352. struct mmc_data *data) {
  353. unsigned start = 0;
  354. unsigned end = 0;
  355. unsigned size = roundup(ARCH_DMA_MINALIGN,
  356. data->blocks*data->blocksize);
  357. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  358. dma_addr_t addr;
  359. addr = virt_to_phys((void *)(data->dest));
  360. if (upper_32_bits(addr))
  361. printf("Error found for upper 32 bits\n");
  362. else
  363. start = lower_32_bits(addr);
  364. #else
  365. start = (unsigned)data->dest;
  366. #endif
  367. end = start + size;
  368. invalidate_dcache_range(start, end);
  369. }
  370. #ifdef CONFIG_MCF5441x
  371. /*
  372. * Swaps 32-bit words to little-endian byte order.
  373. */
  374. static inline void sd_swap_dma_buff(struct mmc_data *data)
  375. {
  376. int i, size = data->blocksize >> 2;
  377. u32 *buffer = (u32 *)data->dest;
  378. u32 sw;
  379. while (data->blocks--) {
  380. for (i = 0; i < size; i++) {
  381. sw = __sw32(*buffer);
  382. *buffer++ = sw;
  383. }
  384. }
  385. }
  386. #endif
  387. /*
  388. * Sends a command out on the bus. Takes the mmc pointer,
  389. * a command pointer, and an optional data pointer.
  390. */
  391. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  392. struct mmc_cmd *cmd, struct mmc_data *data)
  393. {
  394. int err = 0;
  395. uint xfertyp;
  396. uint irqstat;
  397. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  398. struct fsl_esdhc *regs = priv->esdhc_regs;
  399. unsigned long start;
  400. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  401. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  402. return 0;
  403. #endif
  404. esdhc_write32(&regs->irqstat, -1);
  405. sync();
  406. /* Wait for the bus to be idle */
  407. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  408. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  409. ;
  410. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  411. ;
  412. /* Wait at least 8 SD clock cycles before the next command */
  413. /*
  414. * Note: This is way more than 8 cycles, but 1ms seems to
  415. * resolve timing issues with some cards
  416. */
  417. udelay(1000);
  418. /* Set up for a data transfer if we have one */
  419. if (data) {
  420. err = esdhc_setup_data(priv, mmc, data);
  421. if(err)
  422. return err;
  423. if (data->flags & MMC_DATA_READ)
  424. check_and_invalidate_dcache_range(cmd, data);
  425. }
  426. /* Figure out the transfer arguments */
  427. xfertyp = esdhc_xfertyp(cmd, data);
  428. /* Mask all irqs */
  429. esdhc_write32(&regs->irqsigen, 0);
  430. /* Send the command */
  431. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  432. #if defined(CONFIG_FSL_USDHC)
  433. esdhc_write32(&regs->mixctrl,
  434. (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
  435. | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
  436. esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
  437. #else
  438. esdhc_write32(&regs->xfertyp, xfertyp);
  439. #endif
  440. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  441. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
  442. flags = IRQSTAT_BRR;
  443. /* Wait for the command to complete */
  444. start = get_timer(0);
  445. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  446. if (get_timer(start) > 1000) {
  447. err = -ETIMEDOUT;
  448. goto out;
  449. }
  450. }
  451. irqstat = esdhc_read32(&regs->irqstat);
  452. if (irqstat & CMD_ERR) {
  453. err = -ECOMM;
  454. goto out;
  455. }
  456. if (irqstat & IRQSTAT_CTOE) {
  457. err = -ETIMEDOUT;
  458. goto out;
  459. }
  460. /* Switch voltage to 1.8V if CMD11 succeeded */
  461. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
  462. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  463. printf("Run CMD11 1.8V switch\n");
  464. /* Sleep for 5 ms - max time for card to switch to 1.8V */
  465. udelay(5000);
  466. }
  467. /* Workaround for ESDHC errata ENGcm03648 */
  468. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  469. int timeout = 50000;
  470. /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
  471. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  472. PRSSTAT_DAT0)) {
  473. udelay(100);
  474. timeout--;
  475. }
  476. if (timeout <= 0) {
  477. printf("Timeout waiting for DAT0 to go high!\n");
  478. err = -ETIMEDOUT;
  479. goto out;
  480. }
  481. }
  482. /* Copy the response to the response buffer */
  483. if (cmd->resp_type & MMC_RSP_136) {
  484. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  485. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  486. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  487. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  488. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  489. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  490. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  491. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  492. cmd->response[3] = (cmdrsp0 << 8);
  493. } else
  494. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  495. /* Wait until all of the blocks are transferred */
  496. if (data) {
  497. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  498. esdhc_pio_read_write(priv, data);
  499. #else
  500. flags = DATA_COMPLETE;
  501. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  502. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
  503. flags = IRQSTAT_BRR;
  504. }
  505. do {
  506. irqstat = esdhc_read32(&regs->irqstat);
  507. if (irqstat & IRQSTAT_DTOE) {
  508. err = -ETIMEDOUT;
  509. goto out;
  510. }
  511. if (irqstat & DATA_ERR) {
  512. err = -ECOMM;
  513. goto out;
  514. }
  515. } while ((irqstat & flags) != flags);
  516. /*
  517. * Need invalidate the dcache here again to avoid any
  518. * cache-fill during the DMA operations such as the
  519. * speculative pre-fetching etc.
  520. */
  521. if (data->flags & MMC_DATA_READ) {
  522. check_and_invalidate_dcache_range(cmd, data);
  523. #ifdef CONFIG_MCF5441x
  524. sd_swap_dma_buff(data);
  525. #endif
  526. }
  527. #endif
  528. }
  529. out:
  530. /* Reset CMD and DATA portions on error */
  531. if (err) {
  532. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  533. SYSCTL_RSTC);
  534. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  535. ;
  536. if (data) {
  537. esdhc_write32(&regs->sysctl,
  538. esdhc_read32(&regs->sysctl) |
  539. SYSCTL_RSTD);
  540. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  541. ;
  542. }
  543. /* If this was CMD11, then notify that power cycle is needed */
  544. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
  545. printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
  546. }
  547. esdhc_write32(&regs->irqstat, -1);
  548. return err;
  549. }
  550. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  551. {
  552. struct fsl_esdhc *regs = priv->esdhc_regs;
  553. int div = 1;
  554. #ifdef ARCH_MXC
  555. #ifdef CONFIG_MX53
  556. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  557. int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
  558. #else
  559. int pre_div = 1;
  560. #endif
  561. #else
  562. int pre_div = 2;
  563. #endif
  564. int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
  565. int sdhc_clk = priv->sdhc_clk;
  566. uint clk;
  567. while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
  568. pre_div *= 2;
  569. while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
  570. div++;
  571. pre_div >>= 1;
  572. div -= 1;
  573. clk = (pre_div << 8) | (div << 4);
  574. #ifdef CONFIG_FSL_USDHC
  575. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  576. #else
  577. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  578. #endif
  579. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  580. udelay(10000);
  581. #ifdef CONFIG_FSL_USDHC
  582. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
  583. #else
  584. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  585. #endif
  586. priv->clock = clock;
  587. }
  588. #ifdef MMC_SUPPORTS_TUNING
  589. static int esdhc_change_pinstate(struct udevice *dev)
  590. {
  591. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  592. int ret;
  593. switch (priv->mode) {
  594. case UHS_SDR50:
  595. case UHS_DDR50:
  596. ret = pinctrl_select_state(dev, "state_100mhz");
  597. break;
  598. case UHS_SDR104:
  599. case MMC_HS_200:
  600. case MMC_HS_400:
  601. case MMC_HS_400_ES:
  602. ret = pinctrl_select_state(dev, "state_200mhz");
  603. break;
  604. default:
  605. ret = pinctrl_select_state(dev, "default");
  606. break;
  607. }
  608. if (ret)
  609. printf("%s %d error\n", __func__, priv->mode);
  610. return ret;
  611. }
  612. static void esdhc_reset_tuning(struct mmc *mmc)
  613. {
  614. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  615. struct fsl_esdhc *regs = priv->esdhc_regs;
  616. if (priv->flags & ESDHC_FLAG_USDHC) {
  617. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  618. esdhc_clrbits32(&regs->autoc12err,
  619. MIX_CTRL_SMPCLK_SEL |
  620. MIX_CTRL_EXE_TUNE);
  621. }
  622. }
  623. }
  624. static void esdhc_set_strobe_dll(struct mmc *mmc)
  625. {
  626. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  627. struct fsl_esdhc *regs = priv->esdhc_regs;
  628. u32 val;
  629. if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  630. writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
  631. /*
  632. * enable strobe dll ctrl and adjust the delay target
  633. * for the uSDHC loopback read clock
  634. */
  635. val = ESDHC_STROBE_DLL_CTRL_ENABLE |
  636. (priv->strobe_dll_delay_target <<
  637. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  638. writel(val, &regs->strobe_dllctrl);
  639. /* wait 1us to make sure strobe dll status register stable */
  640. mdelay(1);
  641. val = readl(&regs->strobe_dllstat);
  642. if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
  643. pr_warn("HS400 strobe DLL status REF not lock!\n");
  644. if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  645. pr_warn("HS400 strobe DLL status SLV not lock!\n");
  646. }
  647. }
  648. static int esdhc_set_timing(struct mmc *mmc)
  649. {
  650. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  651. struct fsl_esdhc *regs = priv->esdhc_regs;
  652. u32 mixctrl;
  653. mixctrl = readl(&regs->mixctrl);
  654. mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
  655. switch (mmc->selected_mode) {
  656. case MMC_LEGACY:
  657. case SD_LEGACY:
  658. esdhc_reset_tuning(mmc);
  659. writel(mixctrl, &regs->mixctrl);
  660. break;
  661. case MMC_HS_400:
  662. case MMC_HS_400_ES:
  663. mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
  664. writel(mixctrl, &regs->mixctrl);
  665. esdhc_set_strobe_dll(mmc);
  666. break;
  667. case MMC_HS:
  668. case MMC_HS_52:
  669. case MMC_HS_200:
  670. case SD_HS:
  671. case UHS_SDR12:
  672. case UHS_SDR25:
  673. case UHS_SDR50:
  674. case UHS_SDR104:
  675. writel(mixctrl, &regs->mixctrl);
  676. break;
  677. case UHS_DDR50:
  678. case MMC_DDR_52:
  679. mixctrl |= MIX_CTRL_DDREN;
  680. writel(mixctrl, &regs->mixctrl);
  681. break;
  682. default:
  683. printf("Not supported %d\n", mmc->selected_mode);
  684. return -EINVAL;
  685. }
  686. priv->mode = mmc->selected_mode;
  687. return esdhc_change_pinstate(mmc->dev);
  688. }
  689. static int esdhc_set_voltage(struct mmc *mmc)
  690. {
  691. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  692. struct fsl_esdhc *regs = priv->esdhc_regs;
  693. int ret;
  694. priv->signal_voltage = mmc->signal_voltage;
  695. switch (mmc->signal_voltage) {
  696. case MMC_SIGNAL_VOLTAGE_330:
  697. if (priv->vs18_enable)
  698. return -EIO;
  699. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  700. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  701. ret = regulator_set_value(priv->vqmmc_dev, 3300000);
  702. if (ret) {
  703. printf("Setting to 3.3V error");
  704. return -EIO;
  705. }
  706. /* Wait for 5ms */
  707. mdelay(5);
  708. }
  709. #endif
  710. esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  711. if (!(esdhc_read32(&regs->vendorspec) &
  712. ESDHC_VENDORSPEC_VSELECT))
  713. return 0;
  714. return -EAGAIN;
  715. case MMC_SIGNAL_VOLTAGE_180:
  716. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  717. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  718. ret = regulator_set_value(priv->vqmmc_dev, 1800000);
  719. if (ret) {
  720. printf("Setting to 1.8V error");
  721. return -EIO;
  722. }
  723. }
  724. #endif
  725. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  726. if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
  727. return 0;
  728. return -EAGAIN;
  729. case MMC_SIGNAL_VOLTAGE_120:
  730. return -ENOTSUPP;
  731. default:
  732. return 0;
  733. }
  734. }
  735. static void esdhc_stop_tuning(struct mmc *mmc)
  736. {
  737. struct mmc_cmd cmd;
  738. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  739. cmd.cmdarg = 0;
  740. cmd.resp_type = MMC_RSP_R1b;
  741. dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
  742. }
  743. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  744. {
  745. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  746. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  747. struct fsl_esdhc *regs = priv->esdhc_regs;
  748. struct mmc *mmc = &plat->mmc;
  749. u32 irqstaten = readl(&regs->irqstaten);
  750. u32 irqsigen = readl(&regs->irqsigen);
  751. int i, ret = -ETIMEDOUT;
  752. u32 val, mixctrl;
  753. /* clock tuning is not needed for upto 52MHz */
  754. if (mmc->clock <= 52000000)
  755. return 0;
  756. /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
  757. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  758. val = readl(&regs->autoc12err);
  759. mixctrl = readl(&regs->mixctrl);
  760. val &= ~MIX_CTRL_SMPCLK_SEL;
  761. mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
  762. val |= MIX_CTRL_EXE_TUNE;
  763. mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
  764. writel(val, &regs->autoc12err);
  765. writel(mixctrl, &regs->mixctrl);
  766. }
  767. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
  768. mixctrl = readl(&regs->mixctrl);
  769. mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
  770. writel(mixctrl, &regs->mixctrl);
  771. writel(IRQSTATEN_BRR, &regs->irqstaten);
  772. writel(IRQSTATEN_BRR, &regs->irqsigen);
  773. /*
  774. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  775. * of loops reaches 40 times.
  776. */
  777. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  778. u32 ctrl;
  779. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  780. if (mmc->bus_width == 8)
  781. writel(0x7080, &regs->blkattr);
  782. else if (mmc->bus_width == 4)
  783. writel(0x7040, &regs->blkattr);
  784. } else {
  785. writel(0x7040, &regs->blkattr);
  786. }
  787. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
  788. val = readl(&regs->mixctrl);
  789. val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
  790. writel(val, &regs->mixctrl);
  791. /* We are using STD tuning, no need to check return value */
  792. mmc_send_tuning(mmc, opcode, NULL);
  793. ctrl = readl(&regs->autoc12err);
  794. if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
  795. (ctrl & MIX_CTRL_SMPCLK_SEL)) {
  796. /*
  797. * need to wait some time, make sure sd/mmc fininsh
  798. * send out tuning data, otherwise, the sd/mmc can't
  799. * response to any command when the card still out
  800. * put the tuning data.
  801. */
  802. mdelay(1);
  803. ret = 0;
  804. break;
  805. }
  806. /* Add 1ms delay for SD and eMMC */
  807. mdelay(1);
  808. }
  809. writel(irqstaten, &regs->irqstaten);
  810. writel(irqsigen, &regs->irqsigen);
  811. esdhc_stop_tuning(mmc);
  812. return ret;
  813. }
  814. #endif
  815. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  816. {
  817. struct fsl_esdhc *regs = priv->esdhc_regs;
  818. int ret __maybe_unused;
  819. u32 clock;
  820. /* Set the clock speed */
  821. clock = mmc->clock;
  822. if (clock < mmc->cfg->f_min)
  823. clock = mmc->cfg->f_min;
  824. if (priv->clock != clock)
  825. set_sysctl(priv, mmc, clock);
  826. #ifdef MMC_SUPPORTS_TUNING
  827. if (mmc->clk_disable) {
  828. #ifdef CONFIG_FSL_USDHC
  829. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  830. #else
  831. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  832. #endif
  833. } else {
  834. #ifdef CONFIG_FSL_USDHC
  835. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  836. VENDORSPEC_CKEN);
  837. #else
  838. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  839. #endif
  840. }
  841. if (priv->mode != mmc->selected_mode) {
  842. ret = esdhc_set_timing(mmc);
  843. if (ret) {
  844. printf("esdhc_set_timing error %d\n", ret);
  845. return ret;
  846. }
  847. }
  848. if (priv->signal_voltage != mmc->signal_voltage) {
  849. ret = esdhc_set_voltage(mmc);
  850. if (ret) {
  851. printf("esdhc_set_voltage error %d\n", ret);
  852. return ret;
  853. }
  854. }
  855. #endif
  856. /* Set the bus width */
  857. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  858. if (mmc->bus_width == 4)
  859. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  860. else if (mmc->bus_width == 8)
  861. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  862. return 0;
  863. }
  864. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  865. {
  866. struct fsl_esdhc *regs = priv->esdhc_regs;
  867. ulong start;
  868. /* Reset the entire host controller */
  869. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  870. /* Wait until the controller is available */
  871. start = get_timer(0);
  872. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  873. if (get_timer(start) > 1000)
  874. return -ETIMEDOUT;
  875. }
  876. #if defined(CONFIG_FSL_USDHC)
  877. /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
  878. esdhc_write32(&regs->mmcboot, 0x0);
  879. /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
  880. esdhc_write32(&regs->mixctrl, 0x0);
  881. esdhc_write32(&regs->clktunectrlstatus, 0x0);
  882. /* Put VEND_SPEC to default value */
  883. if (priv->vs18_enable)
  884. esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
  885. ESDHC_VENDORSPEC_VSELECT));
  886. else
  887. esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
  888. /* Disable DLL_CTRL delay line */
  889. esdhc_write32(&regs->dllctrl, 0x0);
  890. #endif
  891. #ifndef ARCH_MXC
  892. /* Enable cache snooping */
  893. esdhc_write32(&regs->scr, 0x00000040);
  894. #endif
  895. #ifndef CONFIG_FSL_USDHC
  896. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  897. #else
  898. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
  899. #endif
  900. /* Set the initial clock speed */
  901. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  902. /* Disable the BRR and BWR bits in IRQSTAT */
  903. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  904. #ifdef CONFIG_MCF5441x
  905. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  906. #else
  907. /* Put the PROCTL reg back to the default */
  908. esdhc_write32(&regs->proctl, PROCTL_INIT);
  909. #endif
  910. /* Set timout to the maximum value */
  911. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  912. return 0;
  913. }
  914. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  915. {
  916. struct fsl_esdhc *regs = priv->esdhc_regs;
  917. int timeout = 1000;
  918. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  919. if (CONFIG_ESDHC_DETECT_QUIRK)
  920. return 1;
  921. #endif
  922. #if CONFIG_IS_ENABLED(DM_MMC)
  923. if (priv->non_removable)
  924. return 1;
  925. if (priv->broken_cd)
  926. return 1;
  927. #if CONFIG_IS_ENABLED(DM_GPIO)
  928. if (dm_gpio_is_valid(&priv->cd_gpio))
  929. return dm_gpio_get_value(&priv->cd_gpio);
  930. #endif
  931. #endif
  932. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  933. udelay(1000);
  934. return timeout > 0;
  935. }
  936. static int esdhc_reset(struct fsl_esdhc *regs)
  937. {
  938. ulong start;
  939. /* reset the controller */
  940. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  941. /* hardware clears the bit when it is done */
  942. start = get_timer(0);
  943. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  944. if (get_timer(start) > 100) {
  945. printf("MMC/SD: Reset never completed.\n");
  946. return -ETIMEDOUT;
  947. }
  948. }
  949. return 0;
  950. }
  951. #if !CONFIG_IS_ENABLED(DM_MMC)
  952. static int esdhc_getcd(struct mmc *mmc)
  953. {
  954. struct fsl_esdhc_priv *priv = mmc->priv;
  955. return esdhc_getcd_common(priv);
  956. }
  957. static int esdhc_init(struct mmc *mmc)
  958. {
  959. struct fsl_esdhc_priv *priv = mmc->priv;
  960. return esdhc_init_common(priv, mmc);
  961. }
  962. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  963. struct mmc_data *data)
  964. {
  965. struct fsl_esdhc_priv *priv = mmc->priv;
  966. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  967. }
  968. static int esdhc_set_ios(struct mmc *mmc)
  969. {
  970. struct fsl_esdhc_priv *priv = mmc->priv;
  971. return esdhc_set_ios_common(priv, mmc);
  972. }
  973. static const struct mmc_ops esdhc_ops = {
  974. .getcd = esdhc_getcd,
  975. .init = esdhc_init,
  976. .send_cmd = esdhc_send_cmd,
  977. .set_ios = esdhc_set_ios,
  978. };
  979. #endif
  980. static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
  981. struct fsl_esdhc_plat *plat)
  982. {
  983. struct mmc_config *cfg;
  984. struct fsl_esdhc *regs;
  985. u32 caps, voltage_caps;
  986. int ret;
  987. if (!priv)
  988. return -EINVAL;
  989. regs = priv->esdhc_regs;
  990. /* First reset the eSDHC controller */
  991. ret = esdhc_reset(regs);
  992. if (ret)
  993. return ret;
  994. #ifdef CONFIG_MCF5441x
  995. /* ColdFire, using SDHC_DATA[3] for card detection */
  996. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  997. #endif
  998. #ifndef CONFIG_FSL_USDHC
  999. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
  1000. | SYSCTL_IPGEN | SYSCTL_CKEN);
  1001. /* Clearing tuning bits in case ROM has set it already */
  1002. esdhc_write32(&regs->mixctrl, 0);
  1003. esdhc_write32(&regs->autoc12err, 0);
  1004. esdhc_write32(&regs->clktunectrlstatus, 0);
  1005. #else
  1006. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  1007. VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
  1008. #endif
  1009. if (priv->vs18_enable)
  1010. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  1011. writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
  1012. cfg = &plat->cfg;
  1013. #ifndef CONFIG_DM_MMC
  1014. memset(cfg, '\0', sizeof(*cfg));
  1015. #endif
  1016. voltage_caps = 0;
  1017. caps = esdhc_read32(&regs->hostcapblt);
  1018. #ifdef CONFIG_MCF5441x
  1019. /*
  1020. * MCF5441x RM declares in more points that sdhc clock speed must
  1021. * never exceed 25 Mhz. From this, the HS bit needs to be disabled
  1022. * from host capabilities.
  1023. */
  1024. caps &= ~ESDHC_HOSTCAPBLT_HSS;
  1025. #endif
  1026. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  1027. caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
  1028. ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
  1029. #endif
  1030. /* T4240 host controller capabilities register should have VS33 bit */
  1031. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  1032. caps = caps | ESDHC_HOSTCAPBLT_VS33;
  1033. #endif
  1034. if (caps & ESDHC_HOSTCAPBLT_VS18)
  1035. voltage_caps |= MMC_VDD_165_195;
  1036. if (caps & ESDHC_HOSTCAPBLT_VS30)
  1037. voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
  1038. if (caps & ESDHC_HOSTCAPBLT_VS33)
  1039. voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
  1040. cfg->name = "FSL_SDHC";
  1041. #if !CONFIG_IS_ENABLED(DM_MMC)
  1042. cfg->ops = &esdhc_ops;
  1043. #endif
  1044. #ifdef CONFIG_SYS_SD_VOLTAGE
  1045. cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
  1046. #else
  1047. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1048. #endif
  1049. if ((cfg->voltages & voltage_caps) == 0) {
  1050. printf("voltage not supported by controller\n");
  1051. return -1;
  1052. }
  1053. if (priv->bus_width == 8)
  1054. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1055. else if (priv->bus_width == 4)
  1056. cfg->host_caps = MMC_MODE_4BIT;
  1057. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1058. #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  1059. cfg->host_caps |= MMC_MODE_DDR_52MHz;
  1060. #endif
  1061. if (priv->bus_width > 0) {
  1062. if (priv->bus_width < 8)
  1063. cfg->host_caps &= ~MMC_MODE_8BIT;
  1064. if (priv->bus_width < 4)
  1065. cfg->host_caps &= ~MMC_MODE_4BIT;
  1066. }
  1067. if (caps & ESDHC_HOSTCAPBLT_HSS)
  1068. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1069. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  1070. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  1071. cfg->host_caps &= ~MMC_MODE_8BIT;
  1072. #endif
  1073. cfg->host_caps |= priv->caps;
  1074. cfg->f_min = 400000;
  1075. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  1076. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1077. writel(0, &regs->dllctrl);
  1078. if (priv->flags & ESDHC_FLAG_USDHC) {
  1079. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  1080. u32 val = readl(&regs->tuning_ctrl);
  1081. val |= ESDHC_STD_TUNING_EN;
  1082. val &= ~ESDHC_TUNING_START_TAP_MASK;
  1083. val |= priv->tuning_start_tap;
  1084. val &= ~ESDHC_TUNING_STEP_MASK;
  1085. val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
  1086. writel(val, &regs->tuning_ctrl);
  1087. }
  1088. }
  1089. return 0;
  1090. }
  1091. #if !CONFIG_IS_ENABLED(DM_MMC)
  1092. static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
  1093. struct fsl_esdhc_priv *priv)
  1094. {
  1095. if (!cfg || !priv)
  1096. return -EINVAL;
  1097. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  1098. priv->bus_width = cfg->max_bus_width;
  1099. priv->sdhc_clk = cfg->sdhc_clk;
  1100. priv->wp_enable = cfg->wp_enable;
  1101. priv->vs18_enable = cfg->vs18_enable;
  1102. return 0;
  1103. };
  1104. int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
  1105. {
  1106. struct fsl_esdhc_plat *plat;
  1107. struct fsl_esdhc_priv *priv;
  1108. struct mmc *mmc;
  1109. int ret;
  1110. if (!cfg)
  1111. return -EINVAL;
  1112. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  1113. if (!priv)
  1114. return -ENOMEM;
  1115. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  1116. if (!plat) {
  1117. free(priv);
  1118. return -ENOMEM;
  1119. }
  1120. ret = fsl_esdhc_cfg_to_priv(cfg, priv);
  1121. if (ret) {
  1122. debug("%s xlate failure\n", __func__);
  1123. free(plat);
  1124. free(priv);
  1125. return ret;
  1126. }
  1127. ret = fsl_esdhc_init(priv, plat);
  1128. if (ret) {
  1129. debug("%s init failure\n", __func__);
  1130. free(plat);
  1131. free(priv);
  1132. return ret;
  1133. }
  1134. mmc = mmc_create(&plat->cfg, priv);
  1135. if (!mmc)
  1136. return -EIO;
  1137. priv->mmc = mmc;
  1138. return 0;
  1139. }
  1140. int fsl_esdhc_mmc_init(bd_t *bis)
  1141. {
  1142. struct fsl_esdhc_cfg *cfg;
  1143. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  1144. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  1145. cfg->sdhc_clk = gd->arch.sdhc_clk;
  1146. return fsl_esdhc_initialize(bis, cfg);
  1147. }
  1148. #endif
  1149. #ifdef CONFIG_OF_LIBFDT
  1150. __weak int esdhc_status_fixup(void *blob, const char *compat)
  1151. {
  1152. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  1153. if (!hwconfig("esdhc")) {
  1154. do_fixup_by_compat(blob, compat, "status", "disabled",
  1155. sizeof("disabled"), 1);
  1156. return 1;
  1157. }
  1158. #endif
  1159. return 0;
  1160. }
  1161. void fdt_fixup_esdhc(void *blob, bd_t *bd)
  1162. {
  1163. const char *compat = "fsl,esdhc";
  1164. if (esdhc_status_fixup(blob, compat))
  1165. return;
  1166. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  1167. gd->arch.sdhc_clk, 1);
  1168. }
  1169. #endif
  1170. #if CONFIG_IS_ENABLED(DM_MMC)
  1171. #include <asm/arch/clock.h>
  1172. __weak void init_clk_usdhc(u32 index)
  1173. {
  1174. }
  1175. static int fsl_esdhc_probe(struct udevice *dev)
  1176. {
  1177. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1178. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1179. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1180. const void *fdt = gd->fdt_blob;
  1181. int node = dev_of_offset(dev);
  1182. struct esdhc_soc_data *data =
  1183. (struct esdhc_soc_data *)dev_get_driver_data(dev);
  1184. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1185. struct udevice *vqmmc_dev;
  1186. #endif
  1187. fdt_addr_t addr;
  1188. unsigned int val;
  1189. struct mmc *mmc;
  1190. #if !CONFIG_IS_ENABLED(BLK)
  1191. struct blk_desc *bdesc;
  1192. #endif
  1193. int ret;
  1194. addr = dev_read_addr(dev);
  1195. if (addr == FDT_ADDR_T_NONE)
  1196. return -EINVAL;
  1197. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  1198. priv->dev = dev;
  1199. priv->mode = -1;
  1200. if (data)
  1201. priv->flags = data->flags;
  1202. val = dev_read_u32_default(dev, "bus-width", -1);
  1203. if (val == 8)
  1204. priv->bus_width = 8;
  1205. else if (val == 4)
  1206. priv->bus_width = 4;
  1207. else
  1208. priv->bus_width = 1;
  1209. val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
  1210. priv->tuning_step = val;
  1211. val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
  1212. ESDHC_TUNING_START_TAP_DEFAULT);
  1213. priv->tuning_start_tap = val;
  1214. val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
  1215. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
  1216. priv->strobe_dll_delay_target = val;
  1217. if (dev_read_bool(dev, "broken-cd"))
  1218. priv->broken_cd = 1;
  1219. if (dev_read_bool(dev, "non-removable")) {
  1220. priv->non_removable = 1;
  1221. } else {
  1222. priv->non_removable = 0;
  1223. #if CONFIG_IS_ENABLED(DM_GPIO)
  1224. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  1225. GPIOD_IS_IN);
  1226. #endif
  1227. }
  1228. if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
  1229. priv->wp_enable = 1;
  1230. } else {
  1231. priv->wp_enable = 0;
  1232. #if CONFIG_IS_ENABLED(DM_GPIO)
  1233. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
  1234. GPIOD_IS_IN);
  1235. #endif
  1236. }
  1237. priv->vs18_enable = 0;
  1238. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1239. /*
  1240. * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
  1241. * otherwise, emmc will work abnormally.
  1242. */
  1243. ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
  1244. if (ret) {
  1245. dev_dbg(dev, "no vqmmc-supply\n");
  1246. } else {
  1247. ret = regulator_set_enable(vqmmc_dev, true);
  1248. if (ret) {
  1249. dev_err(dev, "fail to enable vqmmc-supply\n");
  1250. return ret;
  1251. }
  1252. if (regulator_get_value(vqmmc_dev) == 1800000)
  1253. priv->vs18_enable = 1;
  1254. }
  1255. #endif
  1256. /*
  1257. * TODO:
  1258. * Because lack of clk driver, if SDHC clk is not enabled,
  1259. * need to enable it first before this driver is invoked.
  1260. *
  1261. * we use MXC_ESDHC_CLK to get clk freq.
  1262. * If one would like to make this function work,
  1263. * the aliases should be provided in dts as this:
  1264. *
  1265. * aliases {
  1266. * mmc0 = &usdhc1;
  1267. * mmc1 = &usdhc2;
  1268. * mmc2 = &usdhc3;
  1269. * mmc3 = &usdhc4;
  1270. * };
  1271. * Then if your board only supports mmc2 and mmc3, but we can
  1272. * correctly get the seq as 2 and 3, then let mxc_get_clock
  1273. * work as expected.
  1274. */
  1275. init_clk_usdhc(dev->seq);
  1276. #if CONFIG_IS_ENABLED(CLK)
  1277. /* Assigned clock already set clock */
  1278. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  1279. if (ret) {
  1280. printf("Failed to get per_clk\n");
  1281. return ret;
  1282. }
  1283. ret = clk_enable(&priv->per_clk);
  1284. if (ret) {
  1285. printf("Failed to enable per_clk\n");
  1286. return ret;
  1287. }
  1288. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  1289. #else
  1290. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
  1291. if (priv->sdhc_clk <= 0) {
  1292. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  1293. return -EINVAL;
  1294. }
  1295. #endif
  1296. ret = fsl_esdhc_init(priv, plat);
  1297. if (ret) {
  1298. dev_err(dev, "fsl_esdhc_init failure\n");
  1299. return ret;
  1300. }
  1301. ret = mmc_of_parse(dev, &plat->cfg);
  1302. if (ret)
  1303. return ret;
  1304. mmc = &plat->mmc;
  1305. mmc->cfg = &plat->cfg;
  1306. mmc->dev = dev;
  1307. #if !CONFIG_IS_ENABLED(BLK)
  1308. mmc->priv = priv;
  1309. /* Setup dsr related values */
  1310. mmc->dsr_imp = 0;
  1311. mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
  1312. /* Setup the universal parts of the block interface just once */
  1313. bdesc = mmc_get_blk_desc(mmc);
  1314. bdesc->if_type = IF_TYPE_MMC;
  1315. bdesc->removable = 1;
  1316. bdesc->devnum = mmc_get_next_devnum();
  1317. bdesc->block_read = mmc_bread;
  1318. bdesc->block_write = mmc_bwrite;
  1319. bdesc->block_erase = mmc_berase;
  1320. /* setup initial part type */
  1321. bdesc->part_type = mmc->cfg->part_type;
  1322. mmc_list_add(mmc);
  1323. #endif
  1324. upriv->mmc = mmc;
  1325. return esdhc_init_common(priv, mmc);
  1326. }
  1327. #if CONFIG_IS_ENABLED(DM_MMC)
  1328. static int fsl_esdhc_get_cd(struct udevice *dev)
  1329. {
  1330. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1331. return esdhc_getcd_common(priv);
  1332. }
  1333. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1334. struct mmc_data *data)
  1335. {
  1336. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1337. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1338. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  1339. }
  1340. static int fsl_esdhc_set_ios(struct udevice *dev)
  1341. {
  1342. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1343. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1344. return esdhc_set_ios_common(priv, &plat->mmc);
  1345. }
  1346. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1347. static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
  1348. {
  1349. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1350. struct fsl_esdhc *regs = priv->esdhc_regs;
  1351. u32 m;
  1352. m = readl(&regs->mixctrl);
  1353. m |= MIX_CTRL_HS400_ES;
  1354. writel(m, &regs->mixctrl);
  1355. return 0;
  1356. }
  1357. #endif
  1358. static const struct dm_mmc_ops fsl_esdhc_ops = {
  1359. .get_cd = fsl_esdhc_get_cd,
  1360. .send_cmd = fsl_esdhc_send_cmd,
  1361. .set_ios = fsl_esdhc_set_ios,
  1362. #ifdef MMC_SUPPORTS_TUNING
  1363. .execute_tuning = fsl_esdhc_execute_tuning,
  1364. #endif
  1365. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1366. .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
  1367. #endif
  1368. };
  1369. #endif
  1370. static struct esdhc_soc_data usdhc_imx7d_data = {
  1371. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  1372. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  1373. | ESDHC_FLAG_HS400,
  1374. };
  1375. static struct esdhc_soc_data usdhc_imx8qm_data = {
  1376. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
  1377. ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
  1378. ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
  1379. };
  1380. static const struct udevice_id fsl_esdhc_ids[] = {
  1381. { .compatible = "fsl,imx53-esdhc", },
  1382. { .compatible = "fsl,imx6ul-usdhc", },
  1383. { .compatible = "fsl,imx6sx-usdhc", },
  1384. { .compatible = "fsl,imx6sl-usdhc", },
  1385. { .compatible = "fsl,imx6q-usdhc", },
  1386. { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
  1387. { .compatible = "fsl,imx7ulp-usdhc", },
  1388. { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1389. { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1390. { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1391. { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1392. { .compatible = "fsl,imxrt-usdhc", },
  1393. { .compatible = "fsl,esdhc", },
  1394. { /* sentinel */ }
  1395. };
  1396. #if CONFIG_IS_ENABLED(BLK)
  1397. static int fsl_esdhc_bind(struct udevice *dev)
  1398. {
  1399. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1400. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1401. }
  1402. #endif
  1403. U_BOOT_DRIVER(fsl_esdhc) = {
  1404. .name = "fsl-esdhc-mmc",
  1405. .id = UCLASS_MMC,
  1406. .of_match = fsl_esdhc_ids,
  1407. .ops = &fsl_esdhc_ops,
  1408. #if CONFIG_IS_ENABLED(BLK)
  1409. .bind = fsl_esdhc_bind,
  1410. #endif
  1411. .probe = fsl_esdhc_probe,
  1412. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  1413. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  1414. };
  1415. #endif