designware_i2c.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <i2c.h>
  10. #include <pci.h>
  11. #include <reset.h>
  12. #include <asm/io.h>
  13. #include "designware_i2c.h"
  14. #include <linux/err.h>
  15. #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  16. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  17. {
  18. u32 ena = enable ? IC_ENABLE_0B : 0;
  19. writel(ena, &i2c_base->ic_enable);
  20. return 0;
  21. }
  22. #else
  23. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  24. {
  25. u32 ena = enable ? IC_ENABLE_0B : 0;
  26. int timeout = 100;
  27. do {
  28. writel(ena, &i2c_base->ic_enable);
  29. if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  30. return 0;
  31. /*
  32. * Wait 10 times the signaling period of the highest I2C
  33. * transfer supported by the driver (for 400KHz this is
  34. * 25us) as described in the DesignWare I2C databook.
  35. */
  36. udelay(25);
  37. } while (timeout--);
  38. printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  39. return -ETIMEDOUT;
  40. }
  41. #endif
  42. /* High and low times in different speed modes (in ns) */
  43. enum {
  44. /* SDA Hold Time */
  45. DEFAULT_SDA_HOLD_TIME = 300,
  46. };
  47. /**
  48. * calc_counts() - Convert a period to a number of IC clk cycles
  49. *
  50. * @ic_clk: Input clock in Hz
  51. * @period_ns: Period to represent, in ns
  52. * @return calculated count
  53. */
  54. static uint calc_counts(uint ic_clk, uint period_ns)
  55. {
  56. return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  57. }
  58. /**
  59. * struct i2c_mode_info - Information about an I2C speed mode
  60. *
  61. * Each speed mode has its own characteristics. This struct holds these to aid
  62. * calculations in dw_i2c_calc_timing().
  63. *
  64. * @speed: Speed in Hz
  65. * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  66. * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  67. * @def_rise_time_ns: Default rise time in ns
  68. * @def_fall_time_ns: Default fall time in ns
  69. */
  70. struct i2c_mode_info {
  71. int speed;
  72. int min_scl_hightime_ns;
  73. int min_scl_lowtime_ns;
  74. int def_rise_time_ns;
  75. int def_fall_time_ns;
  76. };
  77. static const struct i2c_mode_info info_for_mode[] = {
  78. [IC_SPEED_MODE_STANDARD] = {
  79. I2C_SPEED_STANDARD_RATE,
  80. MIN_SS_SCL_HIGHTIME,
  81. MIN_SS_SCL_LOWTIME,
  82. 1000,
  83. 300,
  84. },
  85. [IC_SPEED_MODE_FAST] = {
  86. I2C_SPEED_FAST_RATE,
  87. MIN_FS_SCL_HIGHTIME,
  88. MIN_FS_SCL_LOWTIME,
  89. 300,
  90. 300,
  91. },
  92. [IC_SPEED_MODE_FAST_PLUS] = {
  93. I2C_SPEED_FAST_PLUS_RATE,
  94. MIN_FP_SCL_HIGHTIME,
  95. MIN_FP_SCL_LOWTIME,
  96. 260,
  97. 500,
  98. },
  99. [IC_SPEED_MODE_HIGH] = {
  100. I2C_SPEED_HIGH_RATE,
  101. MIN_HS_SCL_HIGHTIME,
  102. MIN_HS_SCL_LOWTIME,
  103. 120,
  104. 120,
  105. },
  106. };
  107. /**
  108. * dw_i2c_calc_timing() - Calculate the timings to use for a bus
  109. *
  110. * @priv: Bus private information (NULL if not using driver model)
  111. * @mode: Speed mode to use
  112. * @ic_clk: IC clock speed in Hz
  113. * @spk_cnt: Spike-suppression count
  114. * @config: Returns value to use
  115. * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
  116. */
  117. static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
  118. int ic_clk, int spk_cnt,
  119. struct dw_i2c_speed_config *config)
  120. {
  121. int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
  122. int hcnt, lcnt, period_cnt, diff, tot;
  123. int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
  124. const struct i2c_mode_info *info;
  125. /*
  126. * Find the period, rise, fall, min tlow, and min thigh in terms of
  127. * counts of the IC clock
  128. */
  129. info = &info_for_mode[mode];
  130. period_cnt = ic_clk / info->speed;
  131. scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
  132. priv->scl_rise_time_ns : info->def_rise_time_ns;
  133. scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
  134. priv->scl_fall_time_ns : info->def_fall_time_ns;
  135. rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
  136. fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
  137. min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
  138. min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
  139. debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
  140. period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
  141. spk_cnt);
  142. /*
  143. * Back-solve for hcnt and lcnt according to the following equations:
  144. * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
  145. * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
  146. */
  147. hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
  148. lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
  149. if (hcnt < 0 || lcnt < 0) {
  150. debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
  151. return -EINVAL;
  152. }
  153. /*
  154. * Now add things back up to ensure the period is hit. If it is off,
  155. * split the difference and bias to lcnt for remainder
  156. */
  157. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  158. if (tot < period_cnt) {
  159. diff = (period_cnt - tot) / 2;
  160. hcnt += diff;
  161. lcnt += diff;
  162. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  163. lcnt += period_cnt - tot;
  164. }
  165. config->scl_lcnt = lcnt;
  166. config->scl_hcnt = hcnt;
  167. /* Use internal default unless other value is specified */
  168. sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
  169. priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
  170. config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
  171. debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
  172. config->sda_hold);
  173. return 0;
  174. }
  175. static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
  176. struct dw_i2c_speed_config *config)
  177. {
  178. const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
  179. struct i2c_regs *regs = priv->regs;
  180. enum i2c_speed_mode i2c_spd;
  181. int spk_cnt;
  182. int ret;
  183. if (priv)
  184. scl_sda_cfg = priv->scl_sda_cfg;
  185. /* Allow high speed if there is no config, or the config allows it */
  186. if (speed >= I2C_SPEED_HIGH_RATE &&
  187. (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
  188. i2c_spd = IC_SPEED_MODE_HIGH;
  189. else if (speed >= I2C_SPEED_FAST_RATE)
  190. i2c_spd = IC_SPEED_MODE_FAST_PLUS;
  191. else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
  192. i2c_spd = IC_SPEED_MODE_FAST;
  193. else
  194. i2c_spd = IC_SPEED_MODE_STANDARD;
  195. /* Get the proper spike-suppression count based on target speed */
  196. if (!priv || !priv->has_spk_cnt)
  197. spk_cnt = 0;
  198. else if (i2c_spd >= IC_SPEED_MODE_HIGH)
  199. spk_cnt = readl(&regs->hs_spklen);
  200. else
  201. spk_cnt = readl(&regs->fs_spklen);
  202. if (scl_sda_cfg) {
  203. config->sda_hold = scl_sda_cfg->sda_hold;
  204. if (i2c_spd == IC_SPEED_MODE_STANDARD) {
  205. config->scl_hcnt = scl_sda_cfg->ss_hcnt;
  206. config->scl_lcnt = scl_sda_cfg->ss_lcnt;
  207. } else {
  208. config->scl_hcnt = scl_sda_cfg->fs_hcnt;
  209. config->scl_lcnt = scl_sda_cfg->fs_lcnt;
  210. }
  211. } else {
  212. ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
  213. config);
  214. if (ret)
  215. return log_msg_ret("gen_confg", ret);
  216. }
  217. config->speed_mode = i2c_spd;
  218. return 0;
  219. }
  220. /*
  221. * _dw_i2c_set_bus_speed - Set the i2c speed
  222. * @speed: required i2c speed
  223. *
  224. * Set the i2c speed.
  225. */
  226. static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
  227. unsigned int speed, unsigned int bus_clk)
  228. {
  229. struct dw_i2c_speed_config config;
  230. unsigned int cntl;
  231. unsigned int ena;
  232. int ret;
  233. ret = calc_bus_speed(priv, speed, bus_clk, &config);
  234. if (ret)
  235. return ret;
  236. /* Get enable setting for restore later */
  237. ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
  238. /* to set speed cltr must be disabled */
  239. dw_i2c_enable(i2c_base, false);
  240. cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  241. switch (config.speed_mode) {
  242. case IC_SPEED_MODE_HIGH:
  243. cntl |= IC_CON_SPD_SS;
  244. writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
  245. writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
  246. break;
  247. case IC_SPEED_MODE_STANDARD:
  248. cntl |= IC_CON_SPD_SS;
  249. writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
  250. writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
  251. break;
  252. case IC_SPEED_MODE_FAST_PLUS:
  253. case IC_SPEED_MODE_FAST:
  254. default:
  255. cntl |= IC_CON_SPD_FS;
  256. writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
  257. writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
  258. break;
  259. }
  260. writel(cntl, &i2c_base->ic_con);
  261. /* Configure SDA Hold Time if required */
  262. if (config.sda_hold)
  263. writel(config.sda_hold, &i2c_base->ic_sda_hold);
  264. /* Restore back i2c now speed set */
  265. if (ena == IC_ENABLE_0B)
  266. dw_i2c_enable(i2c_base, true);
  267. return 0;
  268. }
  269. /*
  270. * i2c_setaddress - Sets the target slave address
  271. * @i2c_addr: target i2c address
  272. *
  273. * Sets the target slave address.
  274. */
  275. static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
  276. {
  277. /* Disable i2c */
  278. dw_i2c_enable(i2c_base, false);
  279. writel(i2c_addr, &i2c_base->ic_tar);
  280. /* Enable i2c */
  281. dw_i2c_enable(i2c_base, true);
  282. }
  283. /*
  284. * i2c_flush_rxfifo - Flushes the i2c RX FIFO
  285. *
  286. * Flushes the i2c RX FIFO
  287. */
  288. static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
  289. {
  290. while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
  291. readl(&i2c_base->ic_cmd_data);
  292. }
  293. /*
  294. * i2c_wait_for_bb - Waits for bus busy
  295. *
  296. * Waits for bus busy
  297. */
  298. static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
  299. {
  300. unsigned long start_time_bb = get_timer(0);
  301. while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
  302. !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
  303. /* Evaluate timeout */
  304. if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
  305. return 1;
  306. }
  307. return 0;
  308. }
  309. static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
  310. int alen)
  311. {
  312. if (i2c_wait_for_bb(i2c_base))
  313. return 1;
  314. i2c_setaddress(i2c_base, chip);
  315. while (alen) {
  316. alen--;
  317. /* high byte address going out first */
  318. writel((addr >> (alen * 8)) & 0xff,
  319. &i2c_base->ic_cmd_data);
  320. }
  321. return 0;
  322. }
  323. static int i2c_xfer_finish(struct i2c_regs *i2c_base)
  324. {
  325. ulong start_stop_det = get_timer(0);
  326. while (1) {
  327. if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
  328. readl(&i2c_base->ic_clr_stop_det);
  329. break;
  330. } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
  331. break;
  332. }
  333. }
  334. if (i2c_wait_for_bb(i2c_base)) {
  335. printf("Timed out waiting for bus\n");
  336. return 1;
  337. }
  338. i2c_flush_rxfifo(i2c_base);
  339. return 0;
  340. }
  341. /*
  342. * i2c_read - Read from i2c memory
  343. * @chip: target i2c address
  344. * @addr: address to read from
  345. * @alen:
  346. * @buffer: buffer for read data
  347. * @len: no of bytes to be read
  348. *
  349. * Read from i2c memory.
  350. */
  351. static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
  352. int alen, u8 *buffer, int len)
  353. {
  354. unsigned long start_time_rx;
  355. unsigned int active = 0;
  356. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  357. /*
  358. * EEPROM chips that implement "address overflow" are ones
  359. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  360. * address and the extra bits end up in the "chip address"
  361. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  362. * four 256 byte chips.
  363. *
  364. * Note that we consider the length of the address field to
  365. * still be one byte because the extra address bits are
  366. * hidden in the chip address.
  367. */
  368. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  369. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  370. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  371. addr);
  372. #endif
  373. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  374. return 1;
  375. start_time_rx = get_timer(0);
  376. while (len) {
  377. if (!active) {
  378. /*
  379. * Avoid writing to ic_cmd_data multiple times
  380. * in case this loop spins too quickly and the
  381. * ic_status RFNE bit isn't set after the first
  382. * write. Subsequent writes to ic_cmd_data can
  383. * trigger spurious i2c transfer.
  384. */
  385. if (len == 1)
  386. writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
  387. else
  388. writel(IC_CMD, &i2c_base->ic_cmd_data);
  389. active = 1;
  390. }
  391. if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
  392. *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
  393. len--;
  394. start_time_rx = get_timer(0);
  395. active = 0;
  396. } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
  397. return 1;
  398. }
  399. }
  400. return i2c_xfer_finish(i2c_base);
  401. }
  402. /*
  403. * i2c_write - Write to i2c memory
  404. * @chip: target i2c address
  405. * @addr: address to read from
  406. * @alen:
  407. * @buffer: buffer for read data
  408. * @len: no of bytes to be read
  409. *
  410. * Write to i2c memory.
  411. */
  412. static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
  413. int alen, u8 *buffer, int len)
  414. {
  415. int nb = len;
  416. unsigned long start_time_tx;
  417. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  418. /*
  419. * EEPROM chips that implement "address overflow" are ones
  420. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  421. * address and the extra bits end up in the "chip address"
  422. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  423. * four 256 byte chips.
  424. *
  425. * Note that we consider the length of the address field to
  426. * still be one byte because the extra address bits are
  427. * hidden in the chip address.
  428. */
  429. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  430. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  431. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  432. addr);
  433. #endif
  434. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  435. return 1;
  436. start_time_tx = get_timer(0);
  437. while (len) {
  438. if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
  439. if (--len == 0) {
  440. writel(*buffer | IC_STOP,
  441. &i2c_base->ic_cmd_data);
  442. } else {
  443. writel(*buffer, &i2c_base->ic_cmd_data);
  444. }
  445. buffer++;
  446. start_time_tx = get_timer(0);
  447. } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
  448. printf("Timed out. i2c write Failed\n");
  449. return 1;
  450. }
  451. }
  452. return i2c_xfer_finish(i2c_base);
  453. }
  454. /*
  455. * __dw_i2c_init - Init function
  456. * @speed: required i2c speed
  457. * @slaveaddr: slave address for the device
  458. *
  459. * Initialization function.
  460. */
  461. static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
  462. {
  463. int ret;
  464. /* Disable i2c */
  465. ret = dw_i2c_enable(i2c_base, false);
  466. if (ret)
  467. return ret;
  468. writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
  469. &i2c_base->ic_con);
  470. writel(IC_RX_TL, &i2c_base->ic_rx_tl);
  471. writel(IC_TX_TL, &i2c_base->ic_tx_tl);
  472. writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
  473. #ifndef CONFIG_DM_I2C
  474. _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
  475. writel(slaveaddr, &i2c_base->ic_sar);
  476. #endif
  477. /* Enable i2c */
  478. ret = dw_i2c_enable(i2c_base, true);
  479. if (ret)
  480. return ret;
  481. return 0;
  482. }
  483. #ifndef CONFIG_DM_I2C
  484. /*
  485. * The legacy I2C functions. These need to get removed once
  486. * all users of this driver are converted to DM.
  487. */
  488. static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
  489. {
  490. switch (adap->hwadapnr) {
  491. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  492. case 3:
  493. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
  494. #endif
  495. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  496. case 2:
  497. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
  498. #endif
  499. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  500. case 1:
  501. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
  502. #endif
  503. case 0:
  504. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
  505. default:
  506. printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
  507. }
  508. return NULL;
  509. }
  510. static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
  511. unsigned int speed)
  512. {
  513. adap->speed = speed;
  514. return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
  515. }
  516. static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  517. {
  518. __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
  519. }
  520. static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  521. int alen, u8 *buffer, int len)
  522. {
  523. return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
  524. }
  525. static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  526. int alen, u8 *buffer, int len)
  527. {
  528. return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
  529. }
  530. /* dw_i2c_probe - Probe the i2c chip */
  531. static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
  532. {
  533. struct i2c_regs *i2c_base = i2c_get_base(adap);
  534. u32 tmp;
  535. int ret;
  536. /*
  537. * Try to read the first location of the chip.
  538. */
  539. ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
  540. if (ret)
  541. dw_i2c_init(adap, adap->speed, adap->slaveaddr);
  542. return ret;
  543. }
  544. U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  545. dw_i2c_write, dw_i2c_set_bus_speed,
  546. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  547. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  548. U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  549. dw_i2c_write, dw_i2c_set_bus_speed,
  550. CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
  551. #endif
  552. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  553. U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  554. dw_i2c_write, dw_i2c_set_bus_speed,
  555. CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
  556. #endif
  557. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  558. U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  559. dw_i2c_write, dw_i2c_set_bus_speed,
  560. CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
  561. #endif
  562. #else /* CONFIG_DM_I2C */
  563. /* The DM I2C functions */
  564. static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  565. int nmsgs)
  566. {
  567. struct dw_i2c *i2c = dev_get_priv(bus);
  568. int ret;
  569. debug("i2c_xfer: %d messages\n", nmsgs);
  570. for (; nmsgs > 0; nmsgs--, msg++) {
  571. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  572. if (msg->flags & I2C_M_RD) {
  573. ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
  574. msg->buf, msg->len);
  575. } else {
  576. ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
  577. msg->buf, msg->len);
  578. }
  579. if (ret) {
  580. debug("i2c_write: error sending\n");
  581. return -EREMOTEIO;
  582. }
  583. }
  584. return 0;
  585. }
  586. static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  587. {
  588. struct dw_i2c *i2c = dev_get_priv(bus);
  589. ulong rate;
  590. #if CONFIG_IS_ENABLED(CLK)
  591. rate = clk_get_rate(&i2c->clk);
  592. if (IS_ERR_VALUE(rate))
  593. return -EINVAL;
  594. #else
  595. rate = IC_CLK;
  596. #endif
  597. return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
  598. }
  599. static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  600. uint chip_flags)
  601. {
  602. struct dw_i2c *i2c = dev_get_priv(bus);
  603. struct i2c_regs *i2c_base = i2c->regs;
  604. u32 tmp;
  605. int ret;
  606. /* Try to read the first location of the chip */
  607. ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
  608. if (ret)
  609. __dw_i2c_init(i2c_base, 0, 0);
  610. return ret;
  611. }
  612. int designware_i2c_ofdata_to_platdata(struct udevice *bus)
  613. {
  614. struct dw_i2c *priv = dev_get_priv(bus);
  615. int ret;
  616. if (!priv->regs)
  617. priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
  618. dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
  619. dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
  620. dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
  621. ret = reset_get_bulk(bus, &priv->resets);
  622. if (ret)
  623. dev_warn(bus, "Can't get reset: %d\n", ret);
  624. else
  625. reset_deassert_bulk(&priv->resets);
  626. #if CONFIG_IS_ENABLED(CLK)
  627. ret = clk_get_by_index(bus, 0, &priv->clk);
  628. if (ret)
  629. return ret;
  630. ret = clk_enable(&priv->clk);
  631. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  632. clk_free(&priv->clk);
  633. dev_err(bus, "failed to enable clock\n");
  634. return ret;
  635. }
  636. #endif
  637. return 0;
  638. }
  639. int designware_i2c_probe(struct udevice *bus)
  640. {
  641. struct dw_i2c *priv = dev_get_priv(bus);
  642. return __dw_i2c_init(priv->regs, 0, 0);
  643. }
  644. int designware_i2c_remove(struct udevice *dev)
  645. {
  646. struct dw_i2c *priv = dev_get_priv(dev);
  647. #if CONFIG_IS_ENABLED(CLK)
  648. clk_disable(&priv->clk);
  649. clk_free(&priv->clk);
  650. #endif
  651. return reset_release_bulk(&priv->resets);
  652. }
  653. const struct dm_i2c_ops designware_i2c_ops = {
  654. .xfer = designware_i2c_xfer,
  655. .probe_chip = designware_i2c_probe_chip,
  656. .set_bus_speed = designware_i2c_set_bus_speed,
  657. };
  658. static const struct udevice_id designware_i2c_ids[] = {
  659. { .compatible = "snps,designware-i2c" },
  660. { }
  661. };
  662. U_BOOT_DRIVER(i2c_designware) = {
  663. .name = "i2c_designware",
  664. .id = UCLASS_I2C,
  665. .of_match = designware_i2c_ids,
  666. .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
  667. .probe = designware_i2c_probe,
  668. .priv_auto_alloc_size = sizeof(struct dw_i2c),
  669. .remove = designware_i2c_remove,
  670. .flags = DM_FLAG_OS_PREPARE,
  671. .ops = &designware_i2c_ops,
  672. };
  673. #endif /* CONFIG_DM_I2C */