fu540-prci.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  4. *
  5. * Copyright (C) 2018 SiFive, Inc.
  6. * Wesley Terpstra
  7. * Paul Walmsley
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * The FU540 PRCI implements clock and reset control for the SiFive
  19. * FU540-C000 chip. This driver assumes that it has sole control
  20. * over all PRCI resources.
  21. *
  22. * This driver is based on the PRCI driver written by Wesley Terpstra.
  23. *
  24. * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
  25. * https://github.com/riscv/riscv-linux
  26. *
  27. * References:
  28. * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
  29. */
  30. #include <common.h>
  31. #include <asm/io.h>
  32. #include <clk-uclass.h>
  33. #include <clk.h>
  34. #include <div64.h>
  35. #include <dm.h>
  36. #include <errno.h>
  37. #include <linux/err.h>
  38. #include <linux/math64.h>
  39. #include <linux/clk/analogbits-wrpll-cln28hpc.h>
  40. #include <dt-bindings/clock/sifive-fu540-prci.h>
  41. /*
  42. * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
  43. * hfclk and rtcclk
  44. */
  45. #define EXPECTED_CLK_PARENT_COUNT 2
  46. /*
  47. * Register offsets and bitmasks
  48. */
  49. /* COREPLLCFG0 */
  50. #define PRCI_COREPLLCFG0_OFFSET 0x4
  51. #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
  52. #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
  53. #define PRCI_COREPLLCFG0_DIVF_SHIFT 6
  54. #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
  55. #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
  56. #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
  57. #define PRCI_COREPLLCFG0_RANGE_SHIFT 18
  58. #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
  59. #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
  60. #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
  61. #define PRCI_COREPLLCFG0_FSE_SHIFT 25
  62. #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
  63. #define PRCI_COREPLLCFG0_LOCK_SHIFT 31
  64. #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
  65. /* DDRPLLCFG0 */
  66. #define PRCI_DDRPLLCFG0_OFFSET 0xc
  67. #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
  68. #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
  69. #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
  70. #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
  71. #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
  72. #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
  73. #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
  74. #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
  75. #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
  76. #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
  77. #define PRCI_DDRPLLCFG0_FSE_SHIFT 25
  78. #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
  79. #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
  80. #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
  81. /* DDRPLLCFG1 */
  82. #define PRCI_DDRPLLCFG1_OFFSET 0x10
  83. #define PRCI_DDRPLLCFG1_CKE_SHIFT 24
  84. #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
  85. /* GEMGXLPLLCFG0 */
  86. #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
  87. #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
  88. #define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
  89. (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
  90. #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
  91. #define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
  92. (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
  93. #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
  94. #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
  95. #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
  96. #define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
  97. (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
  98. #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
  99. #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
  100. (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
  101. #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
  102. #define PRCI_GEMGXLPLLCFG0_FSE_MASK \
  103. (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
  104. #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
  105. #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
  106. /* GEMGXLPLLCFG1 */
  107. #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
  108. #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
  109. #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
  110. /* CORECLKSEL */
  111. #define PRCI_CORECLKSEL_OFFSET 0x24
  112. #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
  113. #define PRCI_CORECLKSEL_CORECLKSEL_MASK \
  114. (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
  115. /* DEVICESRESETREG */
  116. #define PRCI_DEVICESRESETREG_OFFSET 0x28
  117. #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
  118. #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
  119. (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
  120. #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
  121. #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
  122. (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
  123. #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
  124. #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
  125. (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
  126. #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
  127. #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
  128. (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
  129. #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
  130. #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
  131. (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
  132. /* CLKMUXSTATUSREG */
  133. #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
  134. #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
  135. #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
  136. (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
  137. /*
  138. * Private structures
  139. */
  140. /**
  141. * struct __prci_data - per-device-instance data
  142. * @va: base virtual address of the PRCI IP block
  143. * @parent: parent clk instance
  144. *
  145. * PRCI per-device instance data
  146. */
  147. struct __prci_data {
  148. void *va;
  149. struct clk parent_hfclk;
  150. struct clk parent_rtcclk;
  151. };
  152. /**
  153. * struct __prci_wrpll_data - WRPLL configuration and integration data
  154. * @c: WRPLL current configuration record
  155. * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
  156. * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
  157. * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
  158. *
  159. * @enable_bypass and @disable_bypass are used for WRPLL instances
  160. * that contain a separate external glitchless clock mux downstream
  161. * from the PLL. The WRPLL internal bypass mux is not glitchless.
  162. */
  163. struct __prci_wrpll_data {
  164. struct wrpll_cfg c;
  165. void (*enable_bypass)(struct __prci_data *pd);
  166. void (*disable_bypass)(struct __prci_data *pd);
  167. u8 cfg0_offs;
  168. };
  169. struct __prci_clock;
  170. /* struct __prci_clock_ops - clock operations */
  171. struct __prci_clock_ops {
  172. int (*set_rate)(struct __prci_clock *pc,
  173. unsigned long rate,
  174. unsigned long parent_rate);
  175. unsigned long (*round_rate)(struct __prci_clock *pc,
  176. unsigned long rate,
  177. unsigned long *parent_rate);
  178. unsigned long (*recalc_rate)(struct __prci_clock *pc,
  179. unsigned long parent_rate);
  180. };
  181. /**
  182. * struct __prci_clock - describes a clock device managed by PRCI
  183. * @name: user-readable clock name string - should match the manual
  184. * @parent_name: parent name for this clock
  185. * @ops: struct __prci_clock_ops for control
  186. * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
  187. * @pd: PRCI-specific data associated with this clock (if not NULL)
  188. *
  189. * PRCI clock data. Used by the PRCI driver to register PRCI-provided
  190. * clocks to the Linux clock infrastructure.
  191. */
  192. struct __prci_clock {
  193. const char *name;
  194. const char *parent_name;
  195. const struct __prci_clock_ops *ops;
  196. struct __prci_wrpll_data *pwd;
  197. struct __prci_data *pd;
  198. };
  199. /*
  200. * Private functions
  201. */
  202. /**
  203. * __prci_readl() - read from a PRCI register
  204. * @pd: PRCI context
  205. * @offs: register offset to read from (in bytes, from PRCI base address)
  206. *
  207. * Read the register located at offset @offs from the base virtual
  208. * address of the PRCI register target described by @pd, and return
  209. * the value to the caller.
  210. *
  211. * Context: Any context.
  212. *
  213. * Return: the contents of the register described by @pd and @offs.
  214. */
  215. static u32 __prci_readl(struct __prci_data *pd, u32 offs)
  216. {
  217. return readl(pd->va + offs);
  218. }
  219. static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
  220. {
  221. writel(v, pd->va + offs);
  222. }
  223. /* WRPLL-related private functions */
  224. /**
  225. * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
  226. * @c: ptr to a struct wrpll_cfg record to write config into
  227. * @r: value read from the PRCI PLL configuration register
  228. *
  229. * Given a value @r read from an FU540 PRCI PLL configuration register,
  230. * split it into fields and populate it into the WRPLL configuration record
  231. * pointed to by @c.
  232. *
  233. * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
  234. * have the same register layout.
  235. *
  236. * Context: Any context.
  237. */
  238. static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
  239. {
  240. u32 v;
  241. v = r & PRCI_COREPLLCFG0_DIVR_MASK;
  242. v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
  243. c->divr = v;
  244. v = r & PRCI_COREPLLCFG0_DIVF_MASK;
  245. v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
  246. c->divf = v;
  247. v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
  248. v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
  249. c->divq = v;
  250. v = r & PRCI_COREPLLCFG0_RANGE_MASK;
  251. v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
  252. c->range = v;
  253. c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
  254. WRPLL_FLAGS_EXT_FEEDBACK_MASK);
  255. /* external feedback mode not supported */
  256. c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
  257. }
  258. /**
  259. * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
  260. * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
  261. *
  262. * Using a set of WRPLL configuration values pointed to by @c,
  263. * assemble a PRCI PLL configuration register value, and return it to
  264. * the caller.
  265. *
  266. * Context: Any context. Caller must ensure that the contents of the
  267. * record pointed to by @c do not change during the execution
  268. * of this function.
  269. *
  270. * Returns: a value suitable for writing into a PRCI PLL configuration
  271. * register
  272. */
  273. static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
  274. {
  275. u32 r = 0;
  276. r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
  277. r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
  278. r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
  279. r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
  280. /* external feedback mode not supported */
  281. r |= PRCI_COREPLLCFG0_FSE_MASK;
  282. return r;
  283. }
  284. /**
  285. * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
  286. * @pd: PRCI context
  287. * @pwd: PRCI WRPLL metadata
  288. *
  289. * Read the current configuration of the PLL identified by @pwd from
  290. * the PRCI identified by @pd, and store it into the local configuration
  291. * cache in @pwd.
  292. *
  293. * Context: Any context. Caller must prevent the records pointed to by
  294. * @pd and @pwd from changing during execution.
  295. */
  296. static void __prci_wrpll_read_cfg(struct __prci_data *pd,
  297. struct __prci_wrpll_data *pwd)
  298. {
  299. __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
  300. }
  301. /**
  302. * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
  303. * @pd: PRCI context
  304. * @pwd: PRCI WRPLL metadata
  305. * @c: WRPLL configuration record to write
  306. *
  307. * Write the WRPLL configuration described by @c into the WRPLL
  308. * configuration register identified by @pwd in the PRCI instance
  309. * described by @c. Make a cached copy of the WRPLL's current
  310. * configuration so it can be used by other code.
  311. *
  312. * Context: Any context. Caller must prevent the records pointed to by
  313. * @pd and @pwd from changing during execution.
  314. */
  315. static void __prci_wrpll_write_cfg(struct __prci_data *pd,
  316. struct __prci_wrpll_data *pwd,
  317. struct wrpll_cfg *c)
  318. {
  319. __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
  320. memcpy(&pwd->c, c, sizeof(*c));
  321. }
  322. /* Core clock mux control */
  323. /**
  324. * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
  325. * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
  326. *
  327. * Switch the CORECLK mux to the HFCLK input source; return once complete.
  328. *
  329. * Context: Any context. Caller must prevent concurrent changes to the
  330. * PRCI_CORECLKSEL_OFFSET register.
  331. */
  332. static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
  333. {
  334. u32 r;
  335. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
  336. r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
  337. __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
  338. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
  339. }
  340. /**
  341. * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
  342. * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
  343. *
  344. * Switch the CORECLK mux to the PLL output clock; return once complete.
  345. *
  346. * Context: Any context. Caller must prevent concurrent changes to the
  347. * PRCI_CORECLKSEL_OFFSET register.
  348. */
  349. static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
  350. {
  351. u32 r;
  352. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
  353. r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
  354. __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
  355. r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
  356. }
  357. static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
  358. struct __prci_clock *pc,
  359. unsigned long parent_rate)
  360. {
  361. struct __prci_wrpll_data *pwd = pc->pwd;
  362. return wrpll_calc_output_rate(&pwd->c, parent_rate);
  363. }
  364. static unsigned long sifive_fu540_prci_wrpll_round_rate(
  365. struct __prci_clock *pc,
  366. unsigned long rate,
  367. unsigned long *parent_rate)
  368. {
  369. struct __prci_wrpll_data *pwd = pc->pwd;
  370. struct wrpll_cfg c;
  371. memcpy(&c, &pwd->c, sizeof(c));
  372. wrpll_configure_for_rate(&c, rate, *parent_rate);
  373. return wrpll_calc_output_rate(&c, *parent_rate);
  374. }
  375. static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
  376. unsigned long rate,
  377. unsigned long parent_rate)
  378. {
  379. struct __prci_wrpll_data *pwd = pc->pwd;
  380. struct __prci_data *pd = pc->pd;
  381. int r;
  382. r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
  383. if (r)
  384. return r;
  385. if (pwd->enable_bypass)
  386. pwd->enable_bypass(pd);
  387. __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
  388. udelay(wrpll_calc_max_lock_us(&pwd->c));
  389. if (pwd->disable_bypass)
  390. pwd->disable_bypass(pd);
  391. return 0;
  392. }
  393. static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
  394. .set_rate = sifive_fu540_prci_wrpll_set_rate,
  395. .round_rate = sifive_fu540_prci_wrpll_round_rate,
  396. .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
  397. };
  398. static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
  399. .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
  400. };
  401. /* TLCLKSEL clock integration */
  402. static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
  403. struct __prci_clock *pc,
  404. unsigned long parent_rate)
  405. {
  406. struct __prci_data *pd = pc->pd;
  407. u32 v;
  408. u8 div;
  409. v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
  410. v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
  411. div = v ? 1 : 2;
  412. return div_u64(parent_rate, div);
  413. }
  414. static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
  415. .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
  416. };
  417. /*
  418. * PRCI integration data for each WRPLL instance
  419. */
  420. static struct __prci_wrpll_data __prci_corepll_data = {
  421. .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
  422. .enable_bypass = __prci_coreclksel_use_hfclk,
  423. .disable_bypass = __prci_coreclksel_use_corepll,
  424. };
  425. static struct __prci_wrpll_data __prci_ddrpll_data = {
  426. .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
  427. };
  428. static struct __prci_wrpll_data __prci_gemgxlpll_data = {
  429. .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
  430. };
  431. /*
  432. * List of clock controls provided by the PRCI
  433. */
  434. static struct __prci_clock __prci_init_clocks[] = {
  435. [PRCI_CLK_COREPLL] = {
  436. .name = "corepll",
  437. .parent_name = "hfclk",
  438. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  439. .pwd = &__prci_corepll_data,
  440. },
  441. [PRCI_CLK_DDRPLL] = {
  442. .name = "ddrpll",
  443. .parent_name = "hfclk",
  444. .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
  445. .pwd = &__prci_ddrpll_data,
  446. },
  447. [PRCI_CLK_GEMGXLPLL] = {
  448. .name = "gemgxlpll",
  449. .parent_name = "hfclk",
  450. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  451. .pwd = &__prci_gemgxlpll_data,
  452. },
  453. [PRCI_CLK_TLCLK] = {
  454. .name = "tlclk",
  455. .parent_name = "corepll",
  456. .ops = &sifive_fu540_prci_tlclksel_clk_ops,
  457. },
  458. };
  459. static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc)
  460. {
  461. ulong parent_rate;
  462. struct __prci_clock *p;
  463. if (strcmp(pc->parent_name, "corepll") == 0) {
  464. p = &__prci_init_clocks[PRCI_CLK_COREPLL];
  465. if (!p->pd || !p->ops->recalc_rate)
  466. return -ENXIO;
  467. return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p));
  468. }
  469. if (strcmp(pc->parent_name, "rtcclk") == 0)
  470. parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
  471. else
  472. parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
  473. return parent_rate;
  474. }
  475. static ulong sifive_fu540_prci_get_rate(struct clk *clk)
  476. {
  477. struct __prci_clock *pc;
  478. if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
  479. return -ENXIO;
  480. pc = &__prci_init_clocks[clk->id];
  481. if (!pc->pd || !pc->ops->recalc_rate)
  482. return -ENXIO;
  483. return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc));
  484. }
  485. static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
  486. {
  487. int err;
  488. struct __prci_clock *pc;
  489. if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
  490. return -ENXIO;
  491. pc = &__prci_init_clocks[clk->id];
  492. if (!pc->pd || !pc->ops->set_rate)
  493. return -ENXIO;
  494. err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc));
  495. if (err)
  496. return err;
  497. return rate;
  498. }
  499. static int sifive_fu540_prci_probe(struct udevice *dev)
  500. {
  501. int i, err;
  502. struct __prci_clock *pc;
  503. struct __prci_data *pd = dev_get_priv(dev);
  504. pd->va = (void *)dev_read_addr(dev);
  505. if (IS_ERR(pd->va))
  506. return PTR_ERR(pd->va);
  507. err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
  508. if (err)
  509. return err;
  510. err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
  511. if (err)
  512. return err;
  513. for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
  514. pc = &__prci_init_clocks[i];
  515. pc->pd = pd;
  516. if (pc->pwd)
  517. __prci_wrpll_read_cfg(pd, pc->pwd);
  518. }
  519. return 0;
  520. }
  521. static struct clk_ops sifive_fu540_prci_ops = {
  522. .set_rate = sifive_fu540_prci_set_rate,
  523. .get_rate = sifive_fu540_prci_get_rate,
  524. };
  525. static const struct udevice_id sifive_fu540_prci_ids[] = {
  526. { .compatible = "sifive,fu540-c000-prci" },
  527. { }
  528. };
  529. U_BOOT_DRIVER(sifive_fu540_prci) = {
  530. .name = "sifive-fu540-prci",
  531. .id = UCLASS_CLK,
  532. .of_match = sifive_fu540_prci_ids,
  533. .probe = sifive_fu540_prci_probe,
  534. .ops = &sifive_fu540_prci_ops,
  535. .priv_auto_alloc_size = sizeof(struct __prci_data),
  536. };