clk_rk3188.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <dt-structs.h>
  10. #include <errno.h>
  11. #include <mapmem.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/cru_rk3188.h>
  16. #include <asm/arch-rockchip/grf_rk3188.h>
  17. #include <asm/arch-rockchip/hardware.h>
  18. #include <dt-bindings/clock/rk3188-cru.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/lists.h>
  21. #include <dm/uclass-internal.h>
  22. #include <linux/err.h>
  23. #include <linux/log2.h>
  24. enum rk3188_clk_type {
  25. RK3188_CRU,
  26. RK3188A_CRU,
  27. };
  28. struct rk3188_clk_plat {
  29. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  30. struct dtd_rockchip_rk3188_cru dtd;
  31. #endif
  32. };
  33. struct pll_div {
  34. u32 nr;
  35. u32 nf;
  36. u32 no;
  37. };
  38. enum {
  39. VCO_MAX_HZ = 2200U * 1000000,
  40. VCO_MIN_HZ = 440 * 1000000,
  41. OUTPUT_MAX_HZ = 2200U * 1000000,
  42. OUTPUT_MIN_HZ = 30 * 1000000,
  43. FREF_MAX_HZ = 2200U * 1000000,
  44. FREF_MIN_HZ = 30 * 1000,
  45. };
  46. enum {
  47. /* PLL CON0 */
  48. PLL_OD_MASK = 0x0f,
  49. /* PLL CON1 */
  50. PLL_NF_MASK = 0x1fff,
  51. /* PLL CON2 */
  52. PLL_BWADJ_MASK = 0x0fff,
  53. /* PLL CON3 */
  54. PLL_RESET_SHIFT = 5,
  55. /* GRF_SOC_STATUS0 */
  56. SOCSTS_DPLL_LOCK = 1 << 5,
  57. SOCSTS_APLL_LOCK = 1 << 6,
  58. SOCSTS_CPLL_LOCK = 1 << 7,
  59. SOCSTS_GPLL_LOCK = 1 << 8,
  60. };
  61. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  62. #define PLL_DIVISORS(hz, _nr, _no) {\
  63. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  64. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  65. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  66. "divisors on line " __stringify(__LINE__));
  67. /* Keep divisors as low as possible to reduce jitter and power usage */
  68. #ifdef CONFIG_SPL_BUILD
  69. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  70. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  71. #endif
  72. static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
  73. const struct pll_div *div, bool has_bwadj)
  74. {
  75. int pll_id = rk_pll_id(clk_id);
  76. struct rk3188_pll *pll = &cru->pll[pll_id];
  77. /* All PLLs have same VCO and output frequency range restrictions. */
  78. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  79. uint output_hz = vco_hz / div->no;
  80. debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  81. (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  82. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  83. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
  84. (div->no == 1 || !(div->no % 2)));
  85. /* enter reset */
  86. rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  87. rk_clrsetreg(&pll->con0,
  88. CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
  89. ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
  90. rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
  91. if (has_bwadj)
  92. rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  93. udelay(10);
  94. /* return from reset */
  95. rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  96. return 0;
  97. }
  98. static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
  99. unsigned int hz, bool has_bwadj)
  100. {
  101. static const struct pll_div dpll_cfg[] = {
  102. {.nf = 75, .nr = 1, .no = 6},
  103. {.nf = 400, .nr = 9, .no = 2},
  104. {.nf = 500, .nr = 9, .no = 2},
  105. {.nf = 100, .nr = 3, .no = 1},
  106. };
  107. int cfg;
  108. switch (hz) {
  109. case 300000000:
  110. cfg = 0;
  111. break;
  112. case 533000000: /* actually 533.3P MHz */
  113. cfg = 1;
  114. break;
  115. case 666000000: /* actually 666.6P MHz */
  116. cfg = 2;
  117. break;
  118. case 800000000:
  119. cfg = 3;
  120. break;
  121. default:
  122. debug("Unsupported SDRAM frequency");
  123. return -EINVAL;
  124. }
  125. /* pll enter slow-mode */
  126. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
  127. DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  128. rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
  129. /* wait for pll lock */
  130. while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
  131. udelay(1);
  132. /* PLL enter normal-mode */
  133. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
  134. DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
  135. return 0;
  136. }
  137. static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
  138. unsigned int hz, bool has_bwadj)
  139. {
  140. static const struct pll_div apll_cfg[] = {
  141. {.nf = 50, .nr = 1, .no = 2},
  142. {.nf = 67, .nr = 1, .no = 1},
  143. };
  144. int div_core_peri, div_aclk_core, cfg;
  145. /*
  146. * We support two possible frequencies, the safe 600MHz
  147. * which will work with default pmic settings and will
  148. * be set in SPL to get away from the 24MHz default and
  149. * the maximum of 1.6Ghz, which boards can set if they
  150. * were able to get pmic support for it.
  151. */
  152. switch (hz) {
  153. case APLL_SAFE_HZ:
  154. cfg = 0;
  155. div_core_peri = 1;
  156. div_aclk_core = 3;
  157. break;
  158. case APLL_HZ:
  159. cfg = 1;
  160. div_core_peri = 2;
  161. div_aclk_core = 3;
  162. break;
  163. default:
  164. debug("Unsupported ARMCLK frequency");
  165. return -EINVAL;
  166. }
  167. /* pll enter slow-mode */
  168. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
  169. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  170. rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
  171. /* waiting for pll lock */
  172. while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
  173. udelay(1);
  174. /* Set divider for peripherals attached to the cpu core. */
  175. rk_clrsetreg(&cru->cru_clksel_con[0],
  176. CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
  177. div_core_peri << CORE_PERI_DIV_SHIFT);
  178. /* set up dependent divisor for aclk_core */
  179. rk_clrsetreg(&cru->cru_clksel_con[1],
  180. CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
  181. div_aclk_core << CORE_ACLK_DIV_SHIFT);
  182. /* PLL enter normal-mode */
  183. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
  184. APLL_MODE_NORMAL << APLL_MODE_SHIFT);
  185. return hz;
  186. }
  187. /* Get pll rate by id */
  188. static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
  189. enum rk_clk_id clk_id)
  190. {
  191. uint32_t nr, no, nf;
  192. uint32_t con;
  193. int pll_id = rk_pll_id(clk_id);
  194. struct rk3188_pll *pll = &cru->pll[pll_id];
  195. static u8 clk_shift[CLK_COUNT] = {
  196. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
  197. GPLL_MODE_SHIFT
  198. };
  199. uint shift;
  200. con = readl(&cru->cru_mode_con);
  201. shift = clk_shift[clk_id];
  202. switch ((con >> shift) & APLL_MODE_MASK) {
  203. case APLL_MODE_SLOW:
  204. return OSC_HZ;
  205. case APLL_MODE_NORMAL:
  206. /* normal mode */
  207. con = readl(&pll->con0);
  208. no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
  209. nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
  210. con = readl(&pll->con1);
  211. nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
  212. return (24 * nf / (nr * no)) * 1000000;
  213. case APLL_MODE_DEEP:
  214. default:
  215. return 32768;
  216. }
  217. }
  218. static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
  219. int periph)
  220. {
  221. uint div;
  222. u32 con;
  223. switch (periph) {
  224. case HCLK_EMMC:
  225. case SCLK_EMMC:
  226. con = readl(&cru->cru_clksel_con[12]);
  227. div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
  228. break;
  229. case HCLK_SDMMC:
  230. case SCLK_SDMMC:
  231. con = readl(&cru->cru_clksel_con[11]);
  232. div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
  233. break;
  234. case HCLK_SDIO:
  235. case SCLK_SDIO:
  236. con = readl(&cru->cru_clksel_con[12]);
  237. div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
  238. break;
  239. default:
  240. return -EINVAL;
  241. }
  242. return DIV_TO_RATE(gclk_rate, div) / 2;
  243. }
  244. static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
  245. int periph, uint freq)
  246. {
  247. int src_clk_div;
  248. debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
  249. /* mmc clock defaulg div 2 internal, need provide double in cru */
  250. src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
  251. assert(src_clk_div <= 0x3f);
  252. switch (periph) {
  253. case HCLK_EMMC:
  254. case SCLK_EMMC:
  255. rk_clrsetreg(&cru->cru_clksel_con[12],
  256. EMMC_DIV_MASK << EMMC_DIV_SHIFT,
  257. src_clk_div << EMMC_DIV_SHIFT);
  258. break;
  259. case HCLK_SDMMC:
  260. case SCLK_SDMMC:
  261. rk_clrsetreg(&cru->cru_clksel_con[11],
  262. MMC0_DIV_MASK << MMC0_DIV_SHIFT,
  263. src_clk_div << MMC0_DIV_SHIFT);
  264. break;
  265. case HCLK_SDIO:
  266. case SCLK_SDIO:
  267. rk_clrsetreg(&cru->cru_clksel_con[12],
  268. SDIO_DIV_MASK << SDIO_DIV_SHIFT,
  269. src_clk_div << SDIO_DIV_SHIFT);
  270. break;
  271. default:
  272. return -EINVAL;
  273. }
  274. return rockchip_mmc_get_clk(cru, gclk_rate, periph);
  275. }
  276. static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
  277. int periph)
  278. {
  279. uint div;
  280. u32 con;
  281. switch (periph) {
  282. case SCLK_SPI0:
  283. con = readl(&cru->cru_clksel_con[25]);
  284. div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
  285. break;
  286. case SCLK_SPI1:
  287. con = readl(&cru->cru_clksel_con[25]);
  288. div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
  289. break;
  290. default:
  291. return -EINVAL;
  292. }
  293. return DIV_TO_RATE(gclk_rate, div);
  294. }
  295. static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
  296. int periph, uint freq)
  297. {
  298. int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
  299. assert(src_clk_div < 128);
  300. switch (periph) {
  301. case SCLK_SPI0:
  302. assert(src_clk_div <= SPI0_DIV_MASK);
  303. rk_clrsetreg(&cru->cru_clksel_con[25],
  304. SPI0_DIV_MASK << SPI0_DIV_SHIFT,
  305. src_clk_div << SPI0_DIV_SHIFT);
  306. break;
  307. case SCLK_SPI1:
  308. assert(src_clk_div <= SPI1_DIV_MASK);
  309. rk_clrsetreg(&cru->cru_clksel_con[25],
  310. SPI1_DIV_MASK << SPI1_DIV_SHIFT,
  311. src_clk_div << SPI1_DIV_SHIFT);
  312. break;
  313. default:
  314. return -EINVAL;
  315. }
  316. return rockchip_spi_get_clk(cru, gclk_rate, periph);
  317. }
  318. #ifdef CONFIG_SPL_BUILD
  319. static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
  320. bool has_bwadj)
  321. {
  322. u32 aclk_div, hclk_div, pclk_div, h2p_div;
  323. /* pll enter slow-mode */
  324. rk_clrsetreg(&cru->cru_mode_con,
  325. GPLL_MODE_MASK << GPLL_MODE_SHIFT |
  326. CPLL_MODE_MASK << CPLL_MODE_SHIFT,
  327. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  328. CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
  329. /* init pll */
  330. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
  331. rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
  332. /* waiting for pll lock */
  333. while ((readl(&grf->soc_status0) &
  334. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
  335. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
  336. udelay(1);
  337. /*
  338. * cpu clock pll source selection and
  339. * reparent aclk_cpu_pre from apll to gpll
  340. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  341. */
  342. aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
  343. assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  344. rk_clrsetreg(&cru->cru_clksel_con[0],
  345. CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
  346. A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
  347. CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
  348. aclk_div << A9_CPU_DIV_SHIFT);
  349. hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
  350. assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
  351. pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
  352. assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
  353. h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
  354. assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
  355. rk_clrsetreg(&cru->cru_clksel_con[1],
  356. AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
  357. CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
  358. CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
  359. h2p_div << AHB2APB_DIV_SHIFT |
  360. pclk_div << CPU_PCLK_DIV_SHIFT |
  361. hclk_div << CPU_HCLK_DIV_SHIFT);
  362. /*
  363. * peri clock pll source selection and
  364. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  365. */
  366. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  367. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  368. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  369. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  370. PERI_ACLK_HZ && (hclk_div < 0x4));
  371. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  372. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  373. PERI_ACLK_HZ && (pclk_div < 0x4));
  374. rk_clrsetreg(&cru->cru_clksel_con[10],
  375. PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
  376. PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
  377. PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
  378. PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
  379. pclk_div << PERI_PCLK_DIV_SHIFT |
  380. hclk_div << PERI_HCLK_DIV_SHIFT |
  381. aclk_div << PERI_ACLK_DIV_SHIFT);
  382. /* PLL enter normal-mode */
  383. rk_clrsetreg(&cru->cru_mode_con,
  384. GPLL_MODE_MASK << GPLL_MODE_SHIFT |
  385. CPLL_MODE_MASK << CPLL_MODE_SHIFT,
  386. GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
  387. CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
  388. rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
  389. }
  390. #endif
  391. static ulong rk3188_clk_get_rate(struct clk *clk)
  392. {
  393. struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
  394. ulong new_rate, gclk_rate;
  395. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  396. switch (clk->id) {
  397. case 1 ... 4:
  398. new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
  399. break;
  400. case HCLK_EMMC:
  401. case HCLK_SDMMC:
  402. case HCLK_SDIO:
  403. case SCLK_EMMC:
  404. case SCLK_SDMMC:
  405. case SCLK_SDIO:
  406. new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
  407. clk->id);
  408. break;
  409. case SCLK_SPI0:
  410. case SCLK_SPI1:
  411. new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
  412. clk->id);
  413. break;
  414. case PCLK_I2C0:
  415. case PCLK_I2C1:
  416. case PCLK_I2C2:
  417. case PCLK_I2C3:
  418. case PCLK_I2C4:
  419. return gclk_rate;
  420. default:
  421. return -ENOENT;
  422. }
  423. return new_rate;
  424. }
  425. static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
  426. {
  427. struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
  428. struct rk3188_cru *cru = priv->cru;
  429. ulong new_rate;
  430. switch (clk->id) {
  431. case PLL_APLL:
  432. new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
  433. priv->has_bwadj);
  434. break;
  435. case CLK_DDR:
  436. new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
  437. priv->has_bwadj);
  438. break;
  439. case HCLK_EMMC:
  440. case HCLK_SDMMC:
  441. case HCLK_SDIO:
  442. case SCLK_EMMC:
  443. case SCLK_SDMMC:
  444. case SCLK_SDIO:
  445. new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
  446. clk->id, rate);
  447. break;
  448. case SCLK_SPI0:
  449. case SCLK_SPI1:
  450. new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
  451. clk->id, rate);
  452. break;
  453. default:
  454. return -ENOENT;
  455. }
  456. return new_rate;
  457. }
  458. static struct clk_ops rk3188_clk_ops = {
  459. .get_rate = rk3188_clk_get_rate,
  460. .set_rate = rk3188_clk_set_rate,
  461. };
  462. static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
  463. {
  464. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  465. struct rk3188_clk_priv *priv = dev_get_priv(dev);
  466. priv->cru = dev_read_addr_ptr(dev);
  467. #endif
  468. return 0;
  469. }
  470. static int rk3188_clk_probe(struct udevice *dev)
  471. {
  472. struct rk3188_clk_priv *priv = dev_get_priv(dev);
  473. enum rk3188_clk_type type = dev_get_driver_data(dev);
  474. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  475. if (IS_ERR(priv->grf))
  476. return PTR_ERR(priv->grf);
  477. priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
  478. #ifdef CONFIG_SPL_BUILD
  479. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  480. struct rk3188_clk_plat *plat = dev_get_platdata(dev);
  481. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  482. #endif
  483. rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
  484. /* Init CPU frequency */
  485. rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
  486. #endif
  487. return 0;
  488. }
  489. static int rk3188_clk_bind(struct udevice *dev)
  490. {
  491. int ret;
  492. struct udevice *sys_child;
  493. struct sysreset_reg *priv;
  494. /* The reset driver does not have a device node, so bind it here */
  495. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  496. &sys_child);
  497. if (ret) {
  498. debug("Warning: No sysreset driver: ret=%d\n", ret);
  499. } else {
  500. priv = malloc(sizeof(struct sysreset_reg));
  501. priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
  502. cru_glb_srst_fst_value);
  503. priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
  504. cru_glb_srst_snd_value);
  505. sys_child->priv = priv;
  506. }
  507. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  508. ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
  509. ret = rockchip_reset_bind(dev, ret, 9);
  510. if (ret)
  511. debug("Warning: software reset driver bind faile\n");
  512. #endif
  513. return 0;
  514. }
  515. static const struct udevice_id rk3188_clk_ids[] = {
  516. { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
  517. { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
  518. { }
  519. };
  520. U_BOOT_DRIVER(rockchip_rk3188_cru) = {
  521. .name = "rockchip_rk3188_cru",
  522. .id = UCLASS_CLK,
  523. .of_match = rk3188_clk_ids,
  524. .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
  525. .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
  526. .ops = &rk3188_clk_ops,
  527. .bind = rk3188_clk_bind,
  528. .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata,
  529. .probe = rk3188_clk_probe,
  530. };