clk-pllv3.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <div64.h>
  9. #include <malloc.h>
  10. #include <clk-uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/devres.h>
  13. #include <dm/uclass.h>
  14. #include <clk.h>
  15. #include "clk.h"
  16. #include <linux/err.h>
  17. #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
  18. #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
  19. #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
  20. #define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
  21. #define PLL_NUM_OFFSET 0x10
  22. #define PLL_DENOM_OFFSET 0x20
  23. #define BM_PLL_POWER (0x1 << 12)
  24. #define BM_PLL_LOCK (0x1 << 31)
  25. struct clk_pllv3 {
  26. struct clk clk;
  27. void __iomem *base;
  28. u32 power_bit;
  29. bool powerup_set;
  30. u32 div_mask;
  31. u32 div_shift;
  32. };
  33. #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
  34. static ulong clk_pllv3_generic_get_rate(struct clk *clk)
  35. {
  36. struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
  37. unsigned long parent_rate = clk_get_parent_rate(clk);
  38. u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
  39. return (div == 1) ? parent_rate * 22 : parent_rate * 20;
  40. }
  41. static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
  42. {
  43. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  44. unsigned long parent_rate = clk_get_parent_rate(clk);
  45. u32 val, div;
  46. if (rate == parent_rate * 22)
  47. div = 1;
  48. else if (rate == parent_rate * 20)
  49. div = 0;
  50. else
  51. return -EINVAL;
  52. val = readl(pll->base);
  53. val &= ~(pll->div_mask << pll->div_shift);
  54. val |= (div << pll->div_shift);
  55. writel(val, pll->base);
  56. /* Wait for PLL to lock */
  57. while (!(readl(pll->base) & BM_PLL_LOCK))
  58. ;
  59. return 0;
  60. }
  61. static int clk_pllv3_generic_enable(struct clk *clk)
  62. {
  63. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  64. u32 val;
  65. val = readl(pll->base);
  66. if (pll->powerup_set)
  67. val |= pll->power_bit;
  68. else
  69. val &= ~pll->power_bit;
  70. writel(val, pll->base);
  71. return 0;
  72. }
  73. static int clk_pllv3_generic_disable(struct clk *clk)
  74. {
  75. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  76. u32 val;
  77. val = readl(pll->base);
  78. if (pll->powerup_set)
  79. val &= ~pll->power_bit;
  80. else
  81. val |= pll->power_bit;
  82. writel(val, pll->base);
  83. return 0;
  84. }
  85. static const struct clk_ops clk_pllv3_generic_ops = {
  86. .get_rate = clk_pllv3_generic_get_rate,
  87. .enable = clk_pllv3_generic_enable,
  88. .disable = clk_pllv3_generic_disable,
  89. .set_rate = clk_pllv3_generic_set_rate,
  90. };
  91. static ulong clk_pllv3_sys_get_rate(struct clk *clk)
  92. {
  93. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  94. unsigned long parent_rate = clk_get_parent_rate(clk);
  95. u32 div = readl(pll->base) & pll->div_mask;
  96. return parent_rate * div / 2;
  97. }
  98. static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
  99. {
  100. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  101. unsigned long parent_rate = clk_get_parent_rate(clk);
  102. unsigned long min_rate;
  103. unsigned long max_rate;
  104. u32 val, div;
  105. if (parent_rate == 0)
  106. return -EINVAL;
  107. min_rate = parent_rate * 54 / 2;
  108. max_rate = parent_rate * 108 / 2;
  109. if (rate < min_rate || rate > max_rate)
  110. return -EINVAL;
  111. div = rate * 2 / parent_rate;
  112. val = readl(pll->base);
  113. val &= ~pll->div_mask;
  114. val |= div;
  115. writel(val, pll->base);
  116. /* Wait for PLL to lock */
  117. while (!(readl(pll->base) & BM_PLL_LOCK))
  118. ;
  119. return 0;
  120. }
  121. static const struct clk_ops clk_pllv3_sys_ops = {
  122. .enable = clk_pllv3_generic_enable,
  123. .disable = clk_pllv3_generic_disable,
  124. .get_rate = clk_pllv3_sys_get_rate,
  125. .set_rate = clk_pllv3_sys_set_rate,
  126. };
  127. static ulong clk_pllv3_av_get_rate(struct clk *clk)
  128. {
  129. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  130. unsigned long parent_rate = clk_get_parent_rate(clk);
  131. u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
  132. u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
  133. u32 div = readl(pll->base) & pll->div_mask;
  134. u64 temp64 = (u64)parent_rate;
  135. if (mfd == 0)
  136. return -EIO;
  137. temp64 *= mfn;
  138. do_div(temp64, mfd);
  139. return parent_rate * div + (unsigned long)temp64;
  140. }
  141. static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
  142. {
  143. struct clk_pllv3 *pll = to_clk_pllv3(clk);
  144. unsigned long parent_rate = clk_get_parent_rate(clk);
  145. unsigned long min_rate;
  146. unsigned long max_rate;
  147. u32 val, div;
  148. u32 mfn, mfd = 1000000;
  149. u32 max_mfd = 0x3FFFFFFF;
  150. u64 temp64;
  151. if (parent_rate == 0)
  152. return -EINVAL;
  153. min_rate = parent_rate * 27;
  154. max_rate = parent_rate * 54;
  155. if (rate < min_rate || rate > max_rate)
  156. return -EINVAL;
  157. if (parent_rate <= max_mfd)
  158. mfd = parent_rate;
  159. div = rate / parent_rate;
  160. temp64 = (u64)(rate - div * parent_rate);
  161. temp64 *= mfd;
  162. do_div(temp64, parent_rate);
  163. mfn = temp64;
  164. val = readl(pll->base);
  165. val &= ~pll->div_mask;
  166. val |= div;
  167. writel(val, pll->base);
  168. writel(mfn, pll->base + PLL_NUM_OFFSET);
  169. writel(mfd, pll->base + PLL_DENOM_OFFSET);
  170. /* Wait for PLL to lock */
  171. while (!(readl(pll->base) & BM_PLL_LOCK))
  172. ;
  173. return 0;
  174. }
  175. static const struct clk_ops clk_pllv3_av_ops = {
  176. .enable = clk_pllv3_generic_enable,
  177. .disable = clk_pllv3_generic_disable,
  178. .get_rate = clk_pllv3_av_get_rate,
  179. .set_rate = clk_pllv3_av_set_rate,
  180. };
  181. struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  182. const char *parent_name, void __iomem *base,
  183. u32 div_mask)
  184. {
  185. struct clk_pllv3 *pll;
  186. struct clk *clk;
  187. char *drv_name;
  188. int ret;
  189. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  190. if (!pll)
  191. return ERR_PTR(-ENOMEM);
  192. pll->power_bit = BM_PLL_POWER;
  193. switch (type) {
  194. case IMX_PLLV3_GENERIC:
  195. drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
  196. pll->div_shift = 0;
  197. pll->powerup_set = false;
  198. break;
  199. case IMX_PLLV3_SYS:
  200. drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
  201. pll->div_shift = 0;
  202. pll->powerup_set = false;
  203. break;
  204. case IMX_PLLV3_USB:
  205. drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
  206. pll->div_shift = 1;
  207. pll->powerup_set = true;
  208. break;
  209. case IMX_PLLV3_AV:
  210. drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
  211. pll->div_shift = 0;
  212. pll->powerup_set = false;
  213. break;
  214. default:
  215. kfree(pll);
  216. return ERR_PTR(-ENOTSUPP);
  217. }
  218. pll->base = base;
  219. pll->div_mask = div_mask;
  220. clk = &pll->clk;
  221. ret = clk_register(clk, drv_name, name, parent_name);
  222. if (ret) {
  223. kfree(pll);
  224. return ERR_PTR(ret);
  225. }
  226. return clk;
  227. }
  228. U_BOOT_DRIVER(clk_pllv3_generic) = {
  229. .name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
  230. .id = UCLASS_CLK,
  231. .ops = &clk_pllv3_generic_ops,
  232. .flags = DM_FLAG_PRE_RELOC,
  233. };
  234. U_BOOT_DRIVER(clk_pllv3_sys) = {
  235. .name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
  236. .id = UCLASS_CLK,
  237. .ops = &clk_pllv3_sys_ops,
  238. .flags = DM_FLAG_PRE_RELOC,
  239. };
  240. U_BOOT_DRIVER(clk_pllv3_usb) = {
  241. .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
  242. .id = UCLASS_CLK,
  243. .ops = &clk_pllv3_generic_ops,
  244. .flags = DM_FLAG_PRE_RELOC,
  245. };
  246. U_BOOT_DRIVER(clk_pllv3_av) = {
  247. .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
  248. .id = UCLASS_CLK,
  249. .ops = &clk_pllv3_av_ops,
  250. .flags = DM_FLAG_PRE_RELOC,
  251. };