clk-pll14xx.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2017-2019 NXP.
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <malloc.h>
  10. #include <clk-uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/devres.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/err.h>
  15. #include <linux/iopoll.h>
  16. #include <clk.h>
  17. #include <div64.h>
  18. #include "clk.h"
  19. #define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
  20. #define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
  21. #define GNRL_CTL 0x0
  22. #define DIV_CTL 0x4
  23. #define LOCK_STATUS BIT(31)
  24. #define LOCK_SEL_MASK BIT(29)
  25. #define CLKE_MASK BIT(11)
  26. #define RST_MASK BIT(9)
  27. #define BYPASS_MASK BIT(4)
  28. #define MDIV_SHIFT 12
  29. #define MDIV_MASK GENMASK(21, 12)
  30. #define PDIV_SHIFT 4
  31. #define PDIV_MASK GENMASK(9, 4)
  32. #define SDIV_SHIFT 0
  33. #define SDIV_MASK GENMASK(2, 0)
  34. #define KDIV_SHIFT 0
  35. #define KDIV_MASK GENMASK(15, 0)
  36. #define LOCK_TIMEOUT_US 10000
  37. struct clk_pll14xx {
  38. struct clk clk;
  39. void __iomem *base;
  40. enum imx_pll14xx_type type;
  41. const struct imx_pll14xx_rate_table *rate_table;
  42. int rate_count;
  43. };
  44. #define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
  45. static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
  46. struct clk_pll14xx *pll, unsigned long rate)
  47. {
  48. const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  49. int i;
  50. for (i = 0; i < pll->rate_count; i++)
  51. if (rate == rate_table[i].rate)
  52. return &rate_table[i];
  53. return NULL;
  54. }
  55. static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
  56. {
  57. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  58. u64 fvco = clk_get_parent_rate(clk);
  59. u32 mdiv, pdiv, sdiv, pll_div;
  60. pll_div = readl(pll->base + 4);
  61. mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  62. pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  63. sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
  64. fvco *= mdiv;
  65. do_div(fvco, pdiv << sdiv);
  66. return fvco;
  67. }
  68. static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
  69. {
  70. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  71. u64 fvco = clk_get_parent_rate(clk);
  72. u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
  73. short int kdiv;
  74. pll_div_ctl0 = readl(pll->base + 4);
  75. pll_div_ctl1 = readl(pll->base + 8);
  76. mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  77. pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  78. sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
  79. kdiv = pll_div_ctl1 & KDIV_MASK;
  80. /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
  81. fvco *= (mdiv * 65536 + kdiv);
  82. pdiv *= 65536;
  83. do_div(fvco, pdiv << sdiv);
  84. return fvco;
  85. }
  86. static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
  87. u32 pll_div)
  88. {
  89. u32 old_mdiv, old_pdiv;
  90. old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  91. old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  92. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
  93. }
  94. static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
  95. u32 pll_div_ctl0, u32 pll_div_ctl1)
  96. {
  97. u32 old_mdiv, old_pdiv, old_kdiv;
  98. old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  99. old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  100. old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
  101. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
  102. rate->kdiv != old_kdiv;
  103. }
  104. static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
  105. u32 pll_div_ctl0, u32 pll_div_ctl1)
  106. {
  107. u32 old_mdiv, old_pdiv, old_kdiv;
  108. old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  109. old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  110. old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
  111. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
  112. rate->kdiv != old_kdiv;
  113. }
  114. static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
  115. {
  116. u32 val;
  117. return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
  118. LOCK_TIMEOUT_US);
  119. }
  120. static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
  121. {
  122. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  123. const struct imx_pll14xx_rate_table *rate;
  124. u32 tmp, div_val;
  125. int ret;
  126. rate = imx_get_pll_settings(pll, drate);
  127. if (!rate) {
  128. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  129. drate, "xxxx");
  130. return -EINVAL;
  131. }
  132. tmp = readl(pll->base + 4);
  133. if (!clk_pll1416x_mp_change(rate, tmp)) {
  134. tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
  135. tmp |= rate->sdiv << SDIV_SHIFT;
  136. writel(tmp, pll->base + 4);
  137. return clk_pll1416x_recalc_rate(clk);
  138. }
  139. /* Bypass clock and set lock to pll output lock */
  140. tmp = readl(pll->base);
  141. tmp |= LOCK_SEL_MASK;
  142. writel(tmp, pll->base);
  143. /* Enable RST */
  144. tmp &= ~RST_MASK;
  145. writel(tmp, pll->base);
  146. /* Enable BYPASS */
  147. tmp |= BYPASS_MASK;
  148. writel(tmp, pll->base);
  149. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  150. (rate->sdiv << SDIV_SHIFT);
  151. writel(div_val, pll->base + 0x4);
  152. /*
  153. * According to SPEC, t3 - t2 need to be greater than
  154. * 1us and 1/FREF, respectively.
  155. * FREF is FIN / Prediv, the prediv is [1, 63], so choose
  156. * 3us.
  157. */
  158. udelay(3);
  159. /* Disable RST */
  160. tmp |= RST_MASK;
  161. writel(tmp, pll->base);
  162. /* Wait Lock */
  163. ret = clk_pll14xx_wait_lock(pll);
  164. if (ret)
  165. return ret;
  166. /* Bypass */
  167. tmp &= ~BYPASS_MASK;
  168. writel(tmp, pll->base);
  169. return clk_pll1416x_recalc_rate(clk);
  170. }
  171. static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
  172. {
  173. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  174. const struct imx_pll14xx_rate_table *rate;
  175. u32 tmp, div_val;
  176. int ret;
  177. rate = imx_get_pll_settings(pll, drate);
  178. if (!rate) {
  179. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  180. drate, "===");
  181. return -EINVAL;
  182. }
  183. tmp = readl(pll->base + 4);
  184. div_val = readl(pll->base + 8);
  185. if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
  186. tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
  187. tmp |= rate->sdiv << SDIV_SHIFT;
  188. writel(tmp, pll->base + 4);
  189. return clk_pll1443x_recalc_rate(clk);
  190. }
  191. tmp = readl(pll->base);
  192. /* Enable RST */
  193. tmp &= ~RST_MASK;
  194. writel(tmp, pll->base);
  195. /* Enable BYPASS */
  196. tmp |= BYPASS_MASK;
  197. writel(tmp, pll->base);
  198. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  199. (rate->sdiv << SDIV_SHIFT);
  200. writel(div_val, pll->base + 0x4);
  201. writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
  202. /*
  203. * According to SPEC, t3 - t2 need to be greater than
  204. * 1us and 1/FREF, respectively.
  205. * FREF is FIN / Prediv, the prediv is [1, 63], so choose
  206. * 3us.
  207. */
  208. udelay(3);
  209. /* Disable RST */
  210. tmp |= RST_MASK;
  211. writel(tmp, pll->base);
  212. /* Wait Lock*/
  213. ret = clk_pll14xx_wait_lock(pll);
  214. if (ret)
  215. return ret;
  216. /* Bypass */
  217. tmp &= ~BYPASS_MASK;
  218. writel(tmp, pll->base);
  219. return clk_pll1443x_recalc_rate(clk);
  220. }
  221. static int clk_pll14xx_prepare(struct clk *clk)
  222. {
  223. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  224. u32 val;
  225. /*
  226. * RESETB = 1 from 0, PLL starts its normal
  227. * operation after lock time
  228. */
  229. val = readl(pll->base + GNRL_CTL);
  230. val |= RST_MASK;
  231. writel(val, pll->base + GNRL_CTL);
  232. return clk_pll14xx_wait_lock(pll);
  233. }
  234. static int clk_pll14xx_unprepare(struct clk *clk)
  235. {
  236. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  237. u32 val;
  238. /*
  239. * Set RST to 0, power down mode is enabled and
  240. * every digital block is reset
  241. */
  242. val = readl(pll->base + GNRL_CTL);
  243. val &= ~RST_MASK;
  244. writel(val, pll->base + GNRL_CTL);
  245. return 0;
  246. }
  247. static const struct clk_ops clk_pll1416x_ops = {
  248. .enable = clk_pll14xx_prepare,
  249. .disable = clk_pll14xx_unprepare,
  250. .set_rate = clk_pll1416x_set_rate,
  251. .get_rate = clk_pll1416x_recalc_rate,
  252. };
  253. static const struct clk_ops clk_pll1443x_ops = {
  254. .enable = clk_pll14xx_prepare,
  255. .disable = clk_pll14xx_unprepare,
  256. .set_rate = clk_pll1443x_set_rate,
  257. .get_rate = clk_pll1443x_recalc_rate,
  258. };
  259. struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
  260. void __iomem *base,
  261. const struct imx_pll14xx_clk *pll_clk)
  262. {
  263. struct clk_pll14xx *pll;
  264. struct clk *clk;
  265. char *type_name;
  266. int ret;
  267. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  268. if (!pll)
  269. return ERR_PTR(-ENOMEM);
  270. switch (pll_clk->type) {
  271. case PLL_1416X:
  272. type_name = UBOOT_DM_CLK_IMX_PLL1416X;
  273. break;
  274. case PLL_1443X:
  275. type_name = UBOOT_DM_CLK_IMX_PLL1443X;
  276. break;
  277. default:
  278. pr_err("%s: Unknown pll type for pll clk %s\n",
  279. __func__, name);
  280. return ERR_PTR(-EINVAL);
  281. };
  282. pll->base = base;
  283. pll->type = pll_clk->type;
  284. pll->rate_table = pll_clk->rate_table;
  285. pll->rate_count = pll_clk->rate_count;
  286. clk = &pll->clk;
  287. ret = clk_register(clk, type_name, name, parent_name);
  288. if (ret) {
  289. pr_err("%s: failed to register pll %s %d\n",
  290. __func__, name, ret);
  291. kfree(pll);
  292. return ERR_PTR(ret);
  293. }
  294. return clk;
  295. }
  296. U_BOOT_DRIVER(clk_pll1443x) = {
  297. .name = UBOOT_DM_CLK_IMX_PLL1443X,
  298. .id = UCLASS_CLK,
  299. .ops = &clk_pll1443x_ops,
  300. .flags = DM_FLAG_PRE_RELOC,
  301. };
  302. U_BOOT_DRIVER(clk_pll1416x) = {
  303. .name = UBOOT_DM_CLK_IMX_PLL1416X,
  304. .id = UCLASS_CLK,
  305. .ops = &clk_pll1416x_ops,
  306. .flags = DM_FLAG_PRE_RELOC,
  307. };