clk_zynqmp.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ZynqMP clock driver
  4. *
  5. * Copyright (C) 2016 Xilinx, Inc.
  6. */
  7. #include <common.h>
  8. #include <linux/bitops.h>
  9. #include <clk-uclass.h>
  10. #include <clk.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <dm.h>
  13. #include <linux/err.h>
  14. static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  15. static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  16. /* Full power domain clocks */
  17. #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
  18. #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
  19. #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
  20. #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
  21. #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
  22. #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
  23. #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
  24. /* Peripheral clocks */
  25. #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
  26. #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
  27. #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
  28. #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
  29. #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
  30. #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
  31. #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
  32. #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
  33. #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
  34. #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
  35. #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
  36. #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
  37. #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
  38. #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
  39. #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
  40. #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
  41. /* Low power domain clocks */
  42. #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
  43. #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
  44. #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
  45. #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
  46. #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
  47. /* Peripheral clocks */
  48. #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
  49. #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
  50. #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
  51. #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
  52. #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
  53. #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
  54. #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
  55. #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
  56. #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
  57. #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
  58. #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
  59. #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
  60. #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
  61. #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
  62. #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
  63. #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
  64. #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
  65. #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
  66. #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
  67. #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
  68. #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
  69. #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
  70. #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
  71. #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
  72. #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
  73. #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
  74. #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
  75. #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
  76. #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
  77. #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
  78. #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
  79. #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
  80. #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
  81. #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
  82. #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
  83. #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
  84. #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
  85. #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
  86. #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
  87. #define ZYNQ_CLK_MAXDIV 0x3f
  88. #define CLK_CTRL_DIV1_SHIFT 16
  89. #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  90. #define CLK_CTRL_DIV0_SHIFT 8
  91. #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  92. #define CLK_CTRL_SRCSEL_SHIFT 0
  93. #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  94. #define PLLCTRL_FBDIV_MASK 0x7f00
  95. #define PLLCTRL_FBDIV_SHIFT 8
  96. #define PLLCTRL_RESET_MASK 1
  97. #define PLLCTRL_RESET_SHIFT 0
  98. #define PLLCTRL_BYPASS_MASK 0x8
  99. #define PLLCTRL_BYPASS_SHFT 3
  100. #define PLLCTRL_POST_SRC_SHFT 24
  101. #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
  102. #define PLLCTRL_PRE_SRC_SHFT 20
  103. #define PLLCTRL_PRE_SRC_MASK (0x7 << PLLCTRL_PRE_SRC_SHFT)
  104. #define NUM_MIO_PINS 77
  105. enum zynqmp_clk {
  106. iopll, rpll,
  107. apll, dpll, vpll,
  108. iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
  109. acpu, acpu_half,
  110. dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
  111. dp_video_ref, dp_audio_ref,
  112. dp_stc_ref, gdma_ref, dpdma_ref,
  113. ddr_ref, sata_ref, pcie_ref,
  114. gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
  115. topsw_main, topsw_lsbus,
  116. gtgref0_ref,
  117. lpd_switch, lpd_lsbus,
  118. usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
  119. cpu_r5, cpu_r5_core,
  120. csu_spb, csu_pll, pcap,
  121. iou_switch,
  122. gem_tsu_ref, gem_tsu,
  123. gem0_ref, gem1_ref, gem2_ref, gem3_ref,
  124. gem0_rx, gem1_rx, gem2_rx, gem3_rx,
  125. qspi_ref,
  126. sdio0_ref, sdio1_ref,
  127. uart0_ref, uart1_ref,
  128. spi0_ref, spi1_ref,
  129. nand_ref,
  130. i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
  131. dll_ref,
  132. adma_ref,
  133. timestamp_ref,
  134. ams_ref,
  135. pl0, pl1, pl2, pl3,
  136. wdt,
  137. clk_max,
  138. };
  139. static const char * const clk_names[clk_max] = {
  140. "iopll", "rpll", "apll", "dpll",
  141. "vpll", "iopll_to_fpd", "rpll_to_fpd",
  142. "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
  143. "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
  144. "dbg_trace", "dbg_tstmp", "dp_video_ref",
  145. "dp_audio_ref", "dp_stc_ref", "gdma_ref",
  146. "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
  147. "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
  148. "topsw_main", "topsw_lsbus", "gtgref0_ref",
  149. "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
  150. "usb1_bus_ref", "usb3_dual_ref", "usb0",
  151. "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
  152. "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
  153. "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
  154. "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
  155. "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
  156. "uart0_ref", "uart1_ref", "spi0_ref",
  157. "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
  158. "can0_ref", "can1_ref", "can0", "can1",
  159. "dll_ref", "adma_ref", "timestamp_ref",
  160. "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
  161. };
  162. struct zynqmp_clk_priv {
  163. unsigned long ps_clk_freq;
  164. unsigned long video_clk;
  165. unsigned long pss_alt_ref_clk;
  166. unsigned long gt_crx_ref_clk;
  167. unsigned long aux_ref_clk;
  168. };
  169. static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
  170. {
  171. switch (id) {
  172. case iopll:
  173. return CRL_APB_IOPLL_CTRL;
  174. case rpll:
  175. return CRL_APB_RPLL_CTRL;
  176. case apll:
  177. return CRF_APB_APLL_CTRL;
  178. case dpll:
  179. return CRF_APB_DPLL_CTRL;
  180. case vpll:
  181. return CRF_APB_VPLL_CTRL;
  182. case acpu:
  183. return CRF_APB_ACPU_CTRL;
  184. case ddr_ref:
  185. return CRF_APB_DDR_CTRL;
  186. case qspi_ref:
  187. return CRL_APB_QSPI_REF_CTRL;
  188. case gem0_ref:
  189. return CRL_APB_GEM0_REF_CTRL;
  190. case gem1_ref:
  191. return CRL_APB_GEM1_REF_CTRL;
  192. case gem2_ref:
  193. return CRL_APB_GEM2_REF_CTRL;
  194. case gem3_ref:
  195. return CRL_APB_GEM3_REF_CTRL;
  196. case uart0_ref:
  197. return CRL_APB_UART0_REF_CTRL;
  198. case uart1_ref:
  199. return CRL_APB_UART1_REF_CTRL;
  200. case sdio0_ref:
  201. return CRL_APB_SDIO0_REF_CTRL;
  202. case sdio1_ref:
  203. return CRL_APB_SDIO1_REF_CTRL;
  204. case spi0_ref:
  205. return CRL_APB_SPI0_REF_CTRL;
  206. case spi1_ref:
  207. return CRL_APB_SPI1_REF_CTRL;
  208. case nand_ref:
  209. return CRL_APB_NAND_REF_CTRL;
  210. case i2c0_ref:
  211. return CRL_APB_I2C0_REF_CTRL;
  212. case i2c1_ref:
  213. return CRL_APB_I2C1_REF_CTRL;
  214. case can0_ref:
  215. return CRL_APB_CAN0_REF_CTRL;
  216. case can1_ref:
  217. return CRL_APB_CAN1_REF_CTRL;
  218. case pl0:
  219. return CRL_APB_PL0_REF_CTRL;
  220. case pl1:
  221. return CRL_APB_PL1_REF_CTRL;
  222. case pl2:
  223. return CRL_APB_PL2_REF_CTRL;
  224. case pl3:
  225. return CRL_APB_PL3_REF_CTRL;
  226. case wdt:
  227. return CRF_APB_TOPSW_LSBUS_CTRL;
  228. case iopll_to_fpd:
  229. return CRL_APB_IOPLL_TO_FPD_CTRL;
  230. default:
  231. debug("Invalid clk id%d\n", id);
  232. }
  233. return 0;
  234. }
  235. static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
  236. {
  237. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  238. CLK_CTRL_SRCSEL_SHIFT;
  239. switch (srcsel) {
  240. case 2:
  241. return dpll;
  242. case 3:
  243. return vpll;
  244. case 0 ... 1:
  245. default:
  246. return apll;
  247. }
  248. }
  249. static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
  250. {
  251. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  252. CLK_CTRL_SRCSEL_SHIFT;
  253. switch (srcsel) {
  254. case 1:
  255. return vpll;
  256. case 0:
  257. default:
  258. return dpll;
  259. }
  260. }
  261. static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
  262. {
  263. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  264. CLK_CTRL_SRCSEL_SHIFT;
  265. switch (srcsel) {
  266. case 2:
  267. return rpll;
  268. case 3:
  269. return dpll;
  270. case 0 ... 1:
  271. default:
  272. return iopll;
  273. }
  274. }
  275. static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
  276. {
  277. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
  278. CLK_CTRL_SRCSEL_SHIFT;
  279. switch (srcsel) {
  280. case 2:
  281. return iopll_to_fpd;
  282. case 3:
  283. return dpll;
  284. case 0 ... 1:
  285. default:
  286. return apll;
  287. }
  288. }
  289. static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
  290. struct zynqmp_clk_priv *priv,
  291. bool is_pre_src)
  292. {
  293. u32 src_sel;
  294. if (is_pre_src)
  295. src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
  296. PLLCTRL_PRE_SRC_SHFT;
  297. else
  298. src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
  299. PLLCTRL_POST_SRC_SHFT;
  300. switch (src_sel) {
  301. case 4:
  302. return priv->video_clk;
  303. case 5:
  304. return priv->pss_alt_ref_clk;
  305. case 6:
  306. return priv->aux_ref_clk;
  307. case 7:
  308. return priv->gt_crx_ref_clk;
  309. case 0 ... 3:
  310. default:
  311. return priv->ps_clk_freq;
  312. }
  313. }
  314. static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
  315. enum zynqmp_clk id)
  316. {
  317. u32 clk_ctrl, reset, mul;
  318. ulong freq;
  319. int ret;
  320. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  321. if (ret) {
  322. printf("%s mio read fail\n", __func__);
  323. return -EIO;
  324. }
  325. if (clk_ctrl & PLLCTRL_BYPASS_MASK)
  326. freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
  327. else
  328. freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
  329. reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
  330. if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
  331. return 0;
  332. mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
  333. freq *= mul;
  334. if (clk_ctrl & (1 << 16))
  335. freq /= 2;
  336. return freq;
  337. }
  338. static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
  339. enum zynqmp_clk id)
  340. {
  341. u32 clk_ctrl, div;
  342. enum zynqmp_clk pll;
  343. int ret;
  344. unsigned long pllrate;
  345. ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
  346. if (ret) {
  347. printf("%s mio read fail\n", __func__);
  348. return -EIO;
  349. }
  350. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  351. pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
  352. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  353. if (IS_ERR_VALUE(pllrate))
  354. return pllrate;
  355. return DIV_ROUND_CLOSEST(pllrate, div);
  356. }
  357. static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
  358. {
  359. u32 clk_ctrl, div;
  360. enum zynqmp_clk pll;
  361. int ret;
  362. ulong pllrate;
  363. ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
  364. if (ret) {
  365. printf("%s mio read fail\n", __func__);
  366. return -EIO;
  367. }
  368. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  369. pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
  370. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  371. if (IS_ERR_VALUE(pllrate))
  372. return pllrate;
  373. return DIV_ROUND_CLOSEST(pllrate, div);
  374. }
  375. static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
  376. enum zynqmp_clk id, bool two_divs)
  377. {
  378. enum zynqmp_clk pll;
  379. u32 clk_ctrl, div0;
  380. u32 div1 = 1;
  381. int ret;
  382. ulong pllrate;
  383. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  384. if (ret) {
  385. printf("%s mio read fail\n", __func__);
  386. return -EIO;
  387. }
  388. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  389. if (!div0)
  390. div0 = 1;
  391. if (two_divs) {
  392. div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
  393. if (!div1)
  394. div1 = 1;
  395. }
  396. pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
  397. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  398. if (IS_ERR_VALUE(pllrate))
  399. return pllrate;
  400. return
  401. DIV_ROUND_CLOSEST(
  402. DIV_ROUND_CLOSEST(pllrate, div0), div1);
  403. }
  404. static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
  405. enum zynqmp_clk id, bool two_divs)
  406. {
  407. enum zynqmp_clk pll;
  408. u32 clk_ctrl, div0;
  409. u32 div1 = 1;
  410. int ret;
  411. ulong pllrate;
  412. ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
  413. if (ret) {
  414. printf("%d %s mio read fail\n", __LINE__, __func__);
  415. return -EIO;
  416. }
  417. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  418. if (!div0)
  419. div0 = 1;
  420. pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
  421. if (two_divs) {
  422. ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
  423. if (ret) {
  424. printf("%d %s mio read fail\n", __LINE__, __func__);
  425. return -EIO;
  426. }
  427. div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  428. if (!div1)
  429. div1 = 1;
  430. }
  431. if (pll == iopll_to_fpd)
  432. pll = iopll;
  433. pllrate = zynqmp_clk_get_pll_rate(priv, pll);
  434. if (IS_ERR_VALUE(pllrate))
  435. return pllrate;
  436. return
  437. DIV_ROUND_CLOSEST(
  438. DIV_ROUND_CLOSEST(pllrate, div0), div1);
  439. }
  440. static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
  441. ulong pll_rate,
  442. u32 *div0, u32 *div1)
  443. {
  444. long new_err, best_err = (long)(~0UL >> 1);
  445. ulong new_rate, best_rate = 0;
  446. u32 d0, d1;
  447. for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
  448. for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
  449. new_rate = DIV_ROUND_CLOSEST(
  450. DIV_ROUND_CLOSEST(pll_rate, d0), d1);
  451. new_err = abs(new_rate - rate);
  452. if (new_err < best_err) {
  453. *div0 = d0;
  454. *div1 = d1;
  455. best_err = new_err;
  456. best_rate = new_rate;
  457. }
  458. }
  459. }
  460. return best_rate;
  461. }
  462. static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
  463. enum zynqmp_clk id, ulong rate,
  464. bool two_divs)
  465. {
  466. enum zynqmp_clk pll;
  467. u32 clk_ctrl, div0 = 0, div1 = 0;
  468. ulong pll_rate, new_rate;
  469. u32 reg;
  470. int ret;
  471. u32 mask;
  472. reg = zynqmp_clk_get_register(id);
  473. ret = zynqmp_mmio_read(reg, &clk_ctrl);
  474. if (ret) {
  475. printf("%s mio read fail\n", __func__);
  476. return -EIO;
  477. }
  478. pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
  479. pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
  480. if (IS_ERR_VALUE(pll_rate))
  481. return pll_rate;
  482. clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
  483. if (two_divs) {
  484. clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
  485. new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
  486. &div0, &div1);
  487. clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
  488. } else {
  489. div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
  490. if (div0 > ZYNQ_CLK_MAXDIV)
  491. div0 = ZYNQ_CLK_MAXDIV;
  492. new_rate = DIV_ROUND_CLOSEST(rate, div0);
  493. }
  494. clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
  495. mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
  496. (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
  497. ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
  498. if (ret) {
  499. printf("%s mio write fail\n", __func__);
  500. return -EIO;
  501. }
  502. return new_rate;
  503. }
  504. static ulong zynqmp_clk_get_rate(struct clk *clk)
  505. {
  506. struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
  507. enum zynqmp_clk id = clk->id;
  508. bool two_divs = false;
  509. switch (id) {
  510. case iopll ... vpll:
  511. return zynqmp_clk_get_pll_rate(priv, id);
  512. case acpu:
  513. return zynqmp_clk_get_cpu_rate(priv, id);
  514. case ddr_ref:
  515. return zynqmp_clk_get_ddr_rate(priv);
  516. case gem0_ref ... gem3_ref:
  517. case qspi_ref ... can1_ref:
  518. case pl0 ... pl3:
  519. two_divs = true;
  520. return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
  521. case wdt:
  522. two_divs = true;
  523. return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
  524. default:
  525. return -ENXIO;
  526. }
  527. }
  528. static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
  529. {
  530. struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
  531. enum zynqmp_clk id = clk->id;
  532. bool two_divs = true;
  533. switch (id) {
  534. case gem0_ref ... gem3_ref:
  535. case qspi_ref ... can1_ref:
  536. return zynqmp_clk_set_peripheral_rate(priv, id,
  537. rate, two_divs);
  538. default:
  539. return -ENXIO;
  540. }
  541. }
  542. int soc_clk_dump(void)
  543. {
  544. struct udevice *dev;
  545. int i, ret;
  546. ret = uclass_get_device_by_driver(UCLASS_CLK,
  547. DM_GET_DRIVER(zynqmp_clk), &dev);
  548. if (ret)
  549. return ret;
  550. printf("clk\t\tfrequency\n");
  551. for (i = 0; i < clk_max; i++) {
  552. const char *name = clk_names[i];
  553. if (name) {
  554. struct clk clk;
  555. unsigned long rate;
  556. clk.id = i;
  557. ret = clk_request(dev, &clk);
  558. if (ret < 0)
  559. return ret;
  560. rate = clk_get_rate(&clk);
  561. clk_free(&clk);
  562. if ((rate == (unsigned long)-ENOSYS) ||
  563. (rate == (unsigned long)-ENXIO) ||
  564. (rate == (unsigned long)-EIO))
  565. printf("%10s%20s\n", name, "unknown");
  566. else
  567. printf("%10s%20lu\n", name, rate);
  568. }
  569. }
  570. return 0;
  571. }
  572. static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
  573. {
  574. struct clk clk;
  575. int ret;
  576. ret = clk_get_by_name(dev, name, &clk);
  577. if (ret < 0) {
  578. dev_err(dev, "failed to get %s\n", name);
  579. return ret;
  580. }
  581. *freq = clk_get_rate(&clk);
  582. if (IS_ERR_VALUE(*freq)) {
  583. dev_err(dev, "failed to get rate %s\n", name);
  584. return -EINVAL;
  585. }
  586. return 0;
  587. }
  588. static int zynqmp_clk_probe(struct udevice *dev)
  589. {
  590. int ret;
  591. struct zynqmp_clk_priv *priv = dev_get_priv(dev);
  592. debug("%s\n", __func__);
  593. ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
  594. if (ret < 0)
  595. return -EINVAL;
  596. ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
  597. if (ret < 0)
  598. return -EINVAL;
  599. ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
  600. &priv->pss_alt_ref_clk);
  601. if (ret < 0)
  602. return -EINVAL;
  603. ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
  604. if (ret < 0)
  605. return -EINVAL;
  606. ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
  607. &priv->gt_crx_ref_clk);
  608. if (ret < 0)
  609. return -EINVAL;
  610. return 0;
  611. }
  612. static struct clk_ops zynqmp_clk_ops = {
  613. .set_rate = zynqmp_clk_set_rate,
  614. .get_rate = zynqmp_clk_get_rate,
  615. };
  616. static const struct udevice_id zynqmp_clk_ids[] = {
  617. { .compatible = "xlnx,zynqmp-clk" },
  618. { }
  619. };
  620. U_BOOT_DRIVER(zynqmp_clk) = {
  621. .name = "zynqmp-clk",
  622. .id = UCLASS_CLK,
  623. .of_match = zynqmp_clk_ids,
  624. .probe = zynqmp_clk_probe,
  625. .ops = &zynqmp_clk_ops,
  626. .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
  627. };