clk_versal.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Xilinx, Inc.
  4. * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <linux/bitops.h>
  8. #include <linux/bitfield.h>
  9. #include <malloc.h>
  10. #include <clk-uclass.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <zynqmp_firmware.h>
  15. #include <linux/err.h>
  16. #define MAX_PARENT 100
  17. #define MAX_NODES 6
  18. #define MAX_NAME_LEN 50
  19. #define CLK_TYPE_SHIFT 2
  20. #define PM_API_PAYLOAD_LEN 3
  21. #define NA_PARENT 0xFFFFFFFF
  22. #define DUMMY_PARENT 0xFFFFFFFE
  23. #define CLK_TYPE_FIELD_LEN 4
  24. #define CLK_TOPOLOGY_NODE_OFFSET 16
  25. #define NODES_PER_RESP 3
  26. #define CLK_TYPE_FIELD_MASK 0xF
  27. #define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
  28. #define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
  29. #define CLK_TYPE_FLAG2_FIELD_MASK GENMASK(7, 4)
  30. #define CLK_TYPE_FLAG_BITS 8
  31. #define CLK_PARENTS_ID_LEN 16
  32. #define CLK_PARENTS_ID_MASK 0xFFFF
  33. #define END_OF_TOPOLOGY_NODE 1
  34. #define END_OF_PARENTS 1
  35. #define CLK_VALID_MASK 0x1
  36. #define NODE_CLASS_SHIFT 26U
  37. #define NODE_SUBCLASS_SHIFT 20U
  38. #define NODE_TYPE_SHIFT 14U
  39. #define NODE_INDEX_SHIFT 0U
  40. #define CLK_GET_NAME_RESP_LEN 16
  41. #define CLK_GET_TOPOLOGY_RESP_WORDS 3
  42. #define CLK_GET_PARENTS_RESP_WORDS 3
  43. #define CLK_GET_ATTR_RESP_WORDS 1
  44. #define NODE_SUBCLASS_CLOCK_PLL 1
  45. #define NODE_SUBCLASS_CLOCK_OUT 2
  46. #define NODE_SUBCLASS_CLOCK_REF 3
  47. #define NODE_CLASS_CLOCK 2
  48. #define NODE_CLASS_MASK 0x3F
  49. #define CLOCK_NODE_TYPE_MUX 1
  50. #define CLOCK_NODE_TYPE_DIV 4
  51. #define CLOCK_NODE_TYPE_GATE 6
  52. enum pm_query_id {
  53. PM_QID_INVALID,
  54. PM_QID_CLOCK_GET_NAME,
  55. PM_QID_CLOCK_GET_TOPOLOGY,
  56. PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
  57. PM_QID_CLOCK_GET_PARENTS,
  58. PM_QID_CLOCK_GET_ATTRIBUTES,
  59. PM_QID_PINCTRL_GET_NUM_PINS,
  60. PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
  61. PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
  62. PM_QID_PINCTRL_GET_FUNCTION_NAME,
  63. PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
  64. PM_QID_PINCTRL_GET_PIN_GROUPS,
  65. PM_QID_CLOCK_GET_NUM_CLOCKS,
  66. PM_QID_CLOCK_GET_MAX_DIVISOR,
  67. };
  68. enum clk_type {
  69. CLK_TYPE_OUTPUT,
  70. CLK_TYPE_EXTERNAL,
  71. };
  72. struct clock_parent {
  73. char name[MAX_NAME_LEN];
  74. int id;
  75. u32 flag;
  76. };
  77. struct clock_topology {
  78. u32 type;
  79. u32 flag;
  80. u32 type_flag;
  81. };
  82. struct versal_clock {
  83. char clk_name[MAX_NAME_LEN];
  84. u32 valid;
  85. enum clk_type type;
  86. struct clock_topology node[MAX_NODES];
  87. u32 num_nodes;
  88. struct clock_parent parent[MAX_PARENT];
  89. u32 num_parents;
  90. u32 clk_id;
  91. };
  92. struct versal_clk_priv {
  93. struct versal_clock *clk;
  94. };
  95. static ulong alt_ref_clk;
  96. static ulong pl_alt_ref_clk;
  97. static ulong ref_clk;
  98. struct versal_pm_query_data {
  99. u32 qid;
  100. u32 arg1;
  101. u32 arg2;
  102. u32 arg3;
  103. };
  104. static struct versal_clock *clock;
  105. static unsigned int clock_max_idx;
  106. #define PM_QUERY_DATA 35
  107. static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload)
  108. {
  109. struct pt_regs regs;
  110. regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA;
  111. regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid;
  112. regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2;
  113. smc_call(&regs);
  114. if (ret_payload) {
  115. ret_payload[0] = (u32)regs.regs[0];
  116. ret_payload[1] = upper_32_bits(regs.regs[0]);
  117. ret_payload[2] = (u32)regs.regs[1];
  118. ret_payload[3] = upper_32_bits(regs.regs[1]);
  119. ret_payload[4] = (u32)regs.regs[2];
  120. }
  121. return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0];
  122. }
  123. static inline int versal_is_valid_clock(u32 clk_id)
  124. {
  125. if (clk_id >= clock_max_idx)
  126. return -ENODEV;
  127. return clock[clk_id].valid;
  128. }
  129. static int versal_get_clock_name(u32 clk_id, char *clk_name)
  130. {
  131. int ret;
  132. ret = versal_is_valid_clock(clk_id);
  133. if (ret == 1) {
  134. strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
  135. return 0;
  136. }
  137. return ret == 0 ? -EINVAL : ret;
  138. }
  139. static int versal_get_clock_type(u32 clk_id, u32 *type)
  140. {
  141. int ret;
  142. ret = versal_is_valid_clock(clk_id);
  143. if (ret == 1) {
  144. *type = clock[clk_id].type;
  145. return 0;
  146. }
  147. return ret == 0 ? -EINVAL : ret;
  148. }
  149. static int versal_pm_clock_get_num_clocks(u32 *nclocks)
  150. {
  151. struct versal_pm_query_data qdata = {0};
  152. u32 ret_payload[PAYLOAD_ARG_CNT];
  153. int ret;
  154. qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
  155. ret = versal_pm_query(qdata, ret_payload);
  156. *nclocks = ret_payload[1];
  157. return ret;
  158. }
  159. static int versal_pm_clock_get_name(u32 clock_id, char *name)
  160. {
  161. struct versal_pm_query_data qdata = {0};
  162. u32 ret_payload[PAYLOAD_ARG_CNT];
  163. int ret;
  164. qdata.qid = PM_QID_CLOCK_GET_NAME;
  165. qdata.arg1 = clock_id;
  166. ret = versal_pm_query(qdata, ret_payload);
  167. if (ret)
  168. return ret;
  169. memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
  170. return 0;
  171. }
  172. static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
  173. {
  174. struct versal_pm_query_data qdata = {0};
  175. u32 ret_payload[PAYLOAD_ARG_CNT];
  176. int ret;
  177. qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
  178. qdata.arg1 = clock_id;
  179. qdata.arg2 = index;
  180. ret = versal_pm_query(qdata, ret_payload);
  181. memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
  182. return ret;
  183. }
  184. static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
  185. {
  186. struct versal_pm_query_data qdata = {0};
  187. u32 ret_payload[PAYLOAD_ARG_CNT];
  188. int ret;
  189. qdata.qid = PM_QID_CLOCK_GET_PARENTS;
  190. qdata.arg1 = clock_id;
  191. qdata.arg2 = index;
  192. ret = versal_pm_query(qdata, ret_payload);
  193. memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
  194. return ret;
  195. }
  196. static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr)
  197. {
  198. struct versal_pm_query_data qdata = {0};
  199. u32 ret_payload[PAYLOAD_ARG_CNT];
  200. int ret;
  201. qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
  202. qdata.arg1 = clock_id;
  203. ret = versal_pm_query(qdata, ret_payload);
  204. memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
  205. return ret;
  206. }
  207. static int __versal_clock_get_topology(struct clock_topology *topology,
  208. u32 *data, u32 *nnodes)
  209. {
  210. int i;
  211. for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
  212. if (!(data[i] & CLK_TYPE_FIELD_MASK))
  213. return END_OF_TOPOLOGY_NODE;
  214. topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
  215. topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
  216. data[i]);
  217. topology[*nnodes].type_flag =
  218. FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
  219. topology[*nnodes].type_flag |=
  220. FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) <<
  221. CLK_TYPE_FLAG_BITS;
  222. debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n",
  223. topology[*nnodes].type, topology[*nnodes].flag,
  224. topology[*nnodes].type_flag);
  225. (*nnodes)++;
  226. }
  227. return 0;
  228. }
  229. static int versal_clock_get_topology(u32 clk_id,
  230. struct clock_topology *topology,
  231. u32 *num_nodes)
  232. {
  233. int j, ret;
  234. u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
  235. *num_nodes = 0;
  236. for (j = 0; j <= MAX_NODES; j += 3) {
  237. ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j,
  238. pm_resp);
  239. if (ret)
  240. return ret;
  241. ret = __versal_clock_get_topology(topology, pm_resp, num_nodes);
  242. if (ret == END_OF_TOPOLOGY_NODE)
  243. return 0;
  244. }
  245. return 0;
  246. }
  247. static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data,
  248. u32 *nparent)
  249. {
  250. int i;
  251. struct clock_parent *parent;
  252. for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
  253. if (data[i] == NA_PARENT)
  254. return END_OF_PARENTS;
  255. parent = &parents[i];
  256. parent->id = data[i] & CLK_PARENTS_ID_MASK;
  257. if (data[i] == DUMMY_PARENT) {
  258. strcpy(parent->name, "dummy_name");
  259. parent->flag = 0;
  260. } else {
  261. parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
  262. if (versal_get_clock_name(parent->id, parent->name))
  263. continue;
  264. }
  265. debug("parent name:%s\n", parent->name);
  266. *nparent += 1;
  267. }
  268. return 0;
  269. }
  270. static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents,
  271. u32 *num_parents)
  272. {
  273. int j = 0, ret;
  274. u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
  275. *num_parents = 0;
  276. do {
  277. /* Get parents from firmware */
  278. ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j,
  279. pm_resp);
  280. if (ret)
  281. return ret;
  282. ret = __versal_clock_get_parents(&parents[j], pm_resp,
  283. num_parents);
  284. if (ret == END_OF_PARENTS)
  285. return 0;
  286. j += PM_API_PAYLOAD_LEN;
  287. } while (*num_parents <= MAX_PARENT);
  288. return 0;
  289. }
  290. static u32 versal_clock_get_div(u32 clk_id)
  291. {
  292. u32 ret_payload[PAYLOAD_ARG_CNT];
  293. u32 div;
  294. xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
  295. div = ret_payload[1];
  296. return div;
  297. }
  298. static u32 versal_clock_set_div(u32 clk_id, u32 div)
  299. {
  300. u32 ret_payload[PAYLOAD_ARG_CNT];
  301. xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
  302. return div;
  303. }
  304. static u64 versal_clock_ref(u32 clk_id)
  305. {
  306. u32 ret_payload[PAYLOAD_ARG_CNT];
  307. int ref;
  308. xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
  309. ref = ret_payload[0];
  310. if (!(ref & 1))
  311. return ref_clk;
  312. if (ref & 2)
  313. return pl_alt_ref_clk;
  314. return 0;
  315. }
  316. static u64 versal_clock_get_pll_rate(u32 clk_id)
  317. {
  318. u32 ret_payload[PAYLOAD_ARG_CNT];
  319. u32 fbdiv;
  320. u32 res;
  321. u32 frac;
  322. u64 freq;
  323. u32 parent_rate, parent_id;
  324. u32 id = clk_id & 0xFFF;
  325. xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
  326. res = ret_payload[1];
  327. if (!res) {
  328. printf("0%x PLL not enabled\n", clk_id);
  329. return 0;
  330. }
  331. parent_id = clock[clock[id].parent[0].id].clk_id;
  332. parent_rate = versal_clock_ref(parent_id);
  333. xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
  334. fbdiv = ret_payload[1];
  335. xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
  336. frac = ret_payload[1];
  337. freq = (fbdiv * parent_rate) >> (1 << frac);
  338. return freq;
  339. }
  340. static u32 versal_clock_mux(u32 clk_id)
  341. {
  342. int i;
  343. u32 id = clk_id & 0xFFF;
  344. for (i = 0; i < clock[id].num_nodes; i++)
  345. if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX)
  346. return 1;
  347. return 0;
  348. }
  349. static u32 versal_clock_get_parentid(u32 clk_id)
  350. {
  351. u32 parent_id = 0;
  352. u32 ret_payload[PAYLOAD_ARG_CNT];
  353. u32 id = clk_id & 0xFFF;
  354. if (versal_clock_mux(clk_id)) {
  355. xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
  356. ret_payload);
  357. parent_id = ret_payload[1];
  358. }
  359. debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);
  360. return clock[clock[id].parent[parent_id].id].clk_id;
  361. }
  362. static u32 versal_clock_gate(u32 clk_id)
  363. {
  364. u32 id = clk_id & 0xFFF;
  365. int i;
  366. for (i = 0; i < clock[id].num_nodes; i++)
  367. if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE)
  368. return 1;
  369. return 0;
  370. }
  371. static u32 versal_clock_div(u32 clk_id)
  372. {
  373. int i;
  374. u32 id = clk_id & 0xFFF;
  375. for (i = 0; i < clock[id].num_nodes; i++)
  376. if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV)
  377. return 1;
  378. return 0;
  379. }
  380. static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate)
  381. {
  382. if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) ==
  383. NODE_SUBCLASS_CLOCK_PLL &&
  384. ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) ==
  385. NODE_CLASS_CLOCK) {
  386. *clk_rate = versal_clock_get_pll_rate(clk_id);
  387. return 1;
  388. }
  389. return 0;
  390. }
  391. static u64 versal_clock_calc(u32 clk_id)
  392. {
  393. u32 parent_id;
  394. u64 clk_rate;
  395. u32 div;
  396. if (versal_clock_pll(clk_id, &clk_rate))
  397. return clk_rate;
  398. parent_id = versal_clock_get_parentid(clk_id);
  399. if (((parent_id >> NODE_SUBCLASS_SHIFT) &
  400. NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
  401. return versal_clock_ref(clk_id);
  402. clk_rate = versal_clock_calc(parent_id);
  403. if (versal_clock_div(clk_id)) {
  404. div = versal_clock_get_div(clk_id);
  405. clk_rate = DIV_ROUND_CLOSEST(clk_rate, div);
  406. }
  407. return clk_rate;
  408. }
  409. static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
  410. {
  411. if (((clk_id >> NODE_SUBCLASS_SHIFT) &
  412. NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
  413. *clk_rate = versal_clock_ref(clk_id);
  414. if (versal_clock_pll(clk_id, clk_rate))
  415. return 0;
  416. if (((clk_id >> NODE_SUBCLASS_SHIFT) &
  417. NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
  418. ((clk_id >> NODE_CLASS_SHIFT) &
  419. NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
  420. if (!versal_clock_gate(clk_id))
  421. return -EINVAL;
  422. *clk_rate = versal_clock_calc(clk_id);
  423. return 0;
  424. }
  425. return 0;
  426. }
  427. int soc_clk_dump(void)
  428. {
  429. u64 clk_rate = 0;
  430. u32 type, ret, i = 0;
  431. printf("\n ****** VERSAL CLOCKS *****\n");
  432. printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
  433. alt_ref_clk, pl_alt_ref_clk, ref_clk);
  434. for (i = 0; i < clock_max_idx; i++) {
  435. debug("%s\n", clock[i].clk_name);
  436. ret = versal_get_clock_type(i, &type);
  437. if (ret || type != CLK_TYPE_OUTPUT)
  438. continue;
  439. ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate);
  440. if (ret != -EINVAL)
  441. printf("clk: %s freq:%lld\n",
  442. clock[i].clk_name, clk_rate);
  443. }
  444. return 0;
  445. }
  446. static void versal_get_clock_info(void)
  447. {
  448. int i, ret;
  449. u32 attr, type = 0, nodetype, subclass, class;
  450. for (i = 0; i < clock_max_idx; i++) {
  451. ret = versal_pm_clock_get_attributes(i, &attr);
  452. if (ret)
  453. continue;
  454. clock[i].valid = attr & CLK_VALID_MASK;
  455. clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
  456. CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
  457. nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
  458. subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK;
  459. class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK;
  460. clock[i].clk_id = (class << NODE_CLASS_SHIFT) |
  461. (subclass << NODE_SUBCLASS_SHIFT) |
  462. (nodetype << NODE_TYPE_SHIFT) |
  463. (i << NODE_INDEX_SHIFT);
  464. ret = versal_pm_clock_get_name(clock[i].clk_id,
  465. clock[i].clk_name);
  466. if (ret)
  467. continue;
  468. debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n",
  469. clock[i].clk_name, clock[i].valid,
  470. clock[i].type, clock[i].clk_id);
  471. }
  472. /* Get topology of all clock */
  473. for (i = 0; i < clock_max_idx; i++) {
  474. ret = versal_get_clock_type(i, &type);
  475. if (ret || type != CLK_TYPE_OUTPUT)
  476. continue;
  477. debug("clk name:%s\n", clock[i].clk_name);
  478. ret = versal_clock_get_topology(i, clock[i].node,
  479. &clock[i].num_nodes);
  480. if (ret)
  481. continue;
  482. ret = versal_clock_get_parents(i, clock[i].parent,
  483. &clock[i].num_parents);
  484. if (ret)
  485. continue;
  486. }
  487. }
  488. int versal_clock_setup(void)
  489. {
  490. int ret;
  491. ret = versal_pm_clock_get_num_clocks(&clock_max_idx);
  492. if (ret)
  493. return ret;
  494. debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx);
  495. clock = calloc(clock_max_idx, sizeof(*clock));
  496. if (!clock)
  497. return -ENOMEM;
  498. versal_get_clock_info();
  499. return 0;
  500. }
  501. static int versal_clock_get_freq_by_name(char *name, struct udevice *dev,
  502. ulong *freq)
  503. {
  504. struct clk clk;
  505. int ret;
  506. ret = clk_get_by_name(dev, name, &clk);
  507. if (ret < 0) {
  508. dev_err(dev, "failed to get %s\n", name);
  509. return ret;
  510. }
  511. *freq = clk_get_rate(&clk);
  512. if (IS_ERR_VALUE(*freq)) {
  513. dev_err(dev, "failed to get rate %s\n", name);
  514. return -EINVAL;
  515. }
  516. return 0;
  517. }
  518. static int versal_clk_probe(struct udevice *dev)
  519. {
  520. int ret;
  521. struct versal_clk_priv *priv = dev_get_priv(dev);
  522. debug("%s\n", __func__);
  523. ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
  524. if (ret < 0)
  525. return -EINVAL;
  526. ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
  527. dev, &pl_alt_ref_clk);
  528. if (ret < 0)
  529. return -EINVAL;
  530. ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
  531. if (ret < 0)
  532. return -EINVAL;
  533. versal_clock_setup();
  534. priv->clk = clock;
  535. return ret;
  536. }
  537. static ulong versal_clk_get_rate(struct clk *clk)
  538. {
  539. struct versal_clk_priv *priv = dev_get_priv(clk->dev);
  540. u32 id = clk->id;
  541. u32 clk_id;
  542. u64 clk_rate = 0;
  543. debug("%s\n", __func__);
  544. clk_id = priv->clk[id].clk_id;
  545. versal_clock_get_rate(clk_id, &clk_rate);
  546. return clk_rate;
  547. }
  548. static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
  549. {
  550. struct versal_clk_priv *priv = dev_get_priv(clk->dev);
  551. u32 id = clk->id;
  552. u32 clk_id;
  553. u64 clk_rate = 0;
  554. u32 div;
  555. int ret;
  556. debug("%s\n", __func__);
  557. clk_id = priv->clk[id].clk_id;
  558. ret = versal_clock_get_rate(clk_id, &clk_rate);
  559. if (ret) {
  560. printf("Clock is not a Gate:0x%x\n", clk_id);
  561. return 0;
  562. }
  563. do {
  564. if (versal_clock_div(clk_id)) {
  565. div = versal_clock_get_div(clk_id);
  566. clk_rate *= div;
  567. div = DIV_ROUND_CLOSEST(clk_rate, rate);
  568. versal_clock_set_div(clk_id, div);
  569. debug("%s, div:%d, newrate:%lld\n", __func__,
  570. div, DIV_ROUND_CLOSEST(clk_rate, div));
  571. return DIV_ROUND_CLOSEST(clk_rate, div);
  572. }
  573. clk_id = versal_clock_get_parentid(clk_id);
  574. } while (((clk_id >> NODE_SUBCLASS_SHIFT) &
  575. NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
  576. printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
  577. return clk_rate;
  578. }
  579. static struct clk_ops versal_clk_ops = {
  580. .set_rate = versal_clk_set_rate,
  581. .get_rate = versal_clk_get_rate,
  582. };
  583. static const struct udevice_id versal_clk_ids[] = {
  584. { .compatible = "xlnx,versal-clk" },
  585. { }
  586. };
  587. U_BOOT_DRIVER(versal_clk) = {
  588. .name = "versal-clk",
  589. .id = UCLASS_CLK,
  590. .of_match = versal_clk_ids,
  591. .probe = versal_clk_probe,
  592. .ops = &versal_clk_ops,
  593. .priv_auto_alloc_size = sizeof(struct versal_clk_priv),
  594. };