clk_sandbox_ccf.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Common Clock Framework [CCF] driver for Sandbox
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <clk.h>
  11. #include <asm/clk.h>
  12. #include <clk-uclass.h>
  13. #include <dm/devres.h>
  14. #include <linux/clk-provider.h>
  15. #include <sandbox-clk.h>
  16. #include <linux/err.h>
  17. /*
  18. * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  19. *
  20. * --- Sandbox PLLv3 ---
  21. */
  22. struct clk_pllv3 {
  23. struct clk clk;
  24. u32 div_mask;
  25. u32 div_shift;
  26. };
  27. int sandbox_clk_enable_count(struct clk *clk)
  28. {
  29. struct clk *clkp = NULL;
  30. int ret;
  31. ret = clk_get_by_id(clk->id, &clkp);
  32. if (ret)
  33. return 0;
  34. return clkp->enable_count;
  35. }
  36. static ulong clk_pllv3_get_rate(struct clk *clk)
  37. {
  38. unsigned long parent_rate = clk_get_parent_rate(clk);
  39. return parent_rate * 24;
  40. }
  41. static const struct clk_ops clk_pllv3_generic_ops = {
  42. .get_rate = clk_pllv3_get_rate,
  43. };
  44. struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  45. const char *parent_name, void __iomem *base,
  46. u32 div_mask)
  47. {
  48. struct clk_pllv3 *pll;
  49. struct clk *clk;
  50. char *drv_name = "sandbox_clk_pllv3";
  51. int ret;
  52. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  53. if (!pll)
  54. return ERR_PTR(-ENOMEM);
  55. pll->div_mask = div_mask;
  56. clk = &pll->clk;
  57. ret = clk_register(clk, drv_name, name, parent_name);
  58. if (ret) {
  59. kfree(pll);
  60. return ERR_PTR(ret);
  61. }
  62. return clk;
  63. }
  64. U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  65. .name = "sandbox_clk_pllv3",
  66. .id = UCLASS_CLK,
  67. .ops = &clk_pllv3_generic_ops,
  68. };
  69. /* --- Sandbox PLLv3 --- */
  70. /* --- Sandbox Gate --- */
  71. struct clk_gate2 {
  72. struct clk clk;
  73. bool state;
  74. };
  75. #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  76. static int clk_gate2_enable(struct clk *clk)
  77. {
  78. struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  79. gate->state = 1;
  80. return 0;
  81. }
  82. static int clk_gate2_disable(struct clk *clk)
  83. {
  84. struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  85. gate->state = 0;
  86. return 0;
  87. }
  88. static const struct clk_ops clk_gate2_ops = {
  89. .enable = clk_gate2_enable,
  90. .disable = clk_gate2_disable,
  91. .get_rate = clk_generic_get_rate,
  92. };
  93. struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
  94. const char *parent_name,
  95. unsigned long flags, void __iomem *reg,
  96. u8 bit_idx, u8 cgr_val,
  97. u8 clk_gate2_flags)
  98. {
  99. struct clk_gate2 *gate;
  100. struct clk *clk;
  101. int ret;
  102. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  103. if (!gate)
  104. return ERR_PTR(-ENOMEM);
  105. gate->state = 0;
  106. clk = &gate->clk;
  107. ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
  108. if (ret) {
  109. kfree(gate);
  110. return ERR_PTR(ret);
  111. }
  112. return clk;
  113. }
  114. U_BOOT_DRIVER(sandbox_clk_gate2) = {
  115. .name = "sandbox_clk_gate2",
  116. .id = UCLASS_CLK,
  117. .ops = &clk_gate2_ops,
  118. };
  119. static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
  120. {
  121. struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  122. struct clk_composite *composite = (struct clk_composite *)clk->data;
  123. ulong parent_rate = clk_get_parent_rate(&composite->clk);
  124. unsigned int val;
  125. val = divider->io_divider_val;
  126. val >>= divider->shift;
  127. val &= clk_div_mask(divider->width);
  128. return divider_recalc_rate(clk, parent_rate, val, divider->table,
  129. divider->flags, divider->width);
  130. }
  131. static const struct clk_ops sandbox_clk_composite_divider_ops = {
  132. .get_rate = sandbox_clk_composite_divider_recalc_rate,
  133. };
  134. struct clk *sandbox_clk_composite(const char *name,
  135. const char * const *parent_names,
  136. int num_parents, void __iomem *reg,
  137. unsigned long flags)
  138. {
  139. struct clk *clk = ERR_PTR(-ENOMEM);
  140. struct clk_divider *div = NULL;
  141. struct clk_gate *gate = NULL;
  142. struct clk_mux *mux = NULL;
  143. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  144. if (!mux)
  145. goto fail;
  146. mux->reg = reg;
  147. mux->shift = 24;
  148. mux->mask = 0x7;
  149. mux->num_parents = num_parents;
  150. mux->flags = flags;
  151. mux->parent_names = parent_names;
  152. div = kzalloc(sizeof(*div), GFP_KERNEL);
  153. if (!div)
  154. goto fail;
  155. div->reg = reg;
  156. div->shift = 16;
  157. div->width = 3;
  158. div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
  159. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  160. if (!gate)
  161. goto fail;
  162. gate->reg = reg;
  163. gate->bit_idx = 28;
  164. gate->flags = flags;
  165. clk = clk_register_composite(NULL, name,
  166. parent_names, num_parents,
  167. &mux->clk, &clk_mux_ops, &div->clk,
  168. &sandbox_clk_composite_divider_ops,
  169. &gate->clk, &clk_gate_ops, flags);
  170. if (IS_ERR(clk))
  171. goto fail;
  172. return clk;
  173. fail:
  174. kfree(gate);
  175. kfree(div);
  176. kfree(mux);
  177. return ERR_CAST(clk);
  178. }
  179. /* --- Sandbox Gate --- */
  180. /* The CCF core driver itself */
  181. static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
  182. { .compatible = "sandbox,clk-ccf" },
  183. { }
  184. };
  185. static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
  186. static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
  187. static int sandbox_clk_ccf_probe(struct udevice *dev)
  188. {
  189. void *base = NULL;
  190. u32 reg;
  191. clk_dm(SANDBOX_CLK_PLL3,
  192. sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
  193. base + 0x10, 0x3));
  194. clk_dm(SANDBOX_CLK_PLL3_60M,
  195. sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
  196. clk_dm(SANDBOX_CLK_PLL3_80M,
  197. sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
  198. /* The HW adds +1 to the divider value (2+1) is the divider */
  199. reg = (2 << 19);
  200. clk_dm(SANDBOX_CLK_ECSPI_ROOT,
  201. sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
  202. clk_dm(SANDBOX_CLK_ECSPI1,
  203. sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
  204. /* Select 'pll3_60m' */
  205. reg = 0;
  206. clk_dm(SANDBOX_CLK_USDHC1_SEL,
  207. sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
  208. ARRAY_SIZE(usdhc_sels)));
  209. /* Select 'pll3_80m' */
  210. reg = BIT(17);
  211. clk_dm(SANDBOX_CLK_USDHC2_SEL,
  212. sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
  213. ARRAY_SIZE(usdhc_sels)));
  214. reg = BIT(28) | BIT(24) | BIT(16);
  215. clk_dm(SANDBOX_CLK_I2C,
  216. sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
  217. &reg, 0));
  218. clk_dm(SANDBOX_CLK_I2C_ROOT,
  219. sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
  220. return 0;
  221. }
  222. U_BOOT_DRIVER(sandbox_clk_ccf) = {
  223. .name = "sandbox_clk_ccf",
  224. .id = UCLASS_CLK,
  225. .probe = sandbox_clk_ccf_probe,
  226. .of_match = sandbox_clk_ccf_test_ids,
  227. };