clk-gate.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
  4. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  5. * Copyright 2019 NXP
  6. *
  7. * Gated clock implementation
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <malloc.h>
  12. #include <clk-uclass.h>
  13. #include <dm/device.h>
  14. #include <dm/devres.h>
  15. #include <linux/clk-provider.h>
  16. #include <clk.h>
  17. #include "clk.h"
  18. #include <linux/err.h>
  19. #define UBOOT_DM_CLK_GATE "clk_gate"
  20. /**
  21. * DOC: basic gatable clock which can gate and ungate it's output
  22. *
  23. * Traits of this clock:
  24. * prepare - clk_(un)prepare only ensures parent is (un)prepared
  25. * enable - clk_enable and clk_disable are functional & control gating
  26. * rate - inherits rate from parent. No clk_set_rate support
  27. * parent - fixed parent. No clk_set_parent support
  28. */
  29. /*
  30. * It works on following logic:
  31. *
  32. * For enabling clock, enable = 1
  33. * set2dis = 1 -> clear bit -> set = 0
  34. * set2dis = 0 -> set bit -> set = 1
  35. *
  36. * For disabling clock, enable = 0
  37. * set2dis = 1 -> set bit -> set = 1
  38. * set2dis = 0 -> clear bit -> set = 0
  39. *
  40. * So, result is always: enable xor set2dis.
  41. */
  42. static void clk_gate_endisable(struct clk *clk, int enable)
  43. {
  44. struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
  45. dev_get_clk_ptr(clk->dev) : clk);
  46. int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
  47. u32 reg;
  48. set ^= enable;
  49. if (gate->flags & CLK_GATE_HIWORD_MASK) {
  50. reg = BIT(gate->bit_idx + 16);
  51. if (set)
  52. reg |= BIT(gate->bit_idx);
  53. } else {
  54. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  55. reg = gate->io_gate_val;
  56. #else
  57. reg = readl(gate->reg);
  58. #endif
  59. if (set)
  60. reg |= BIT(gate->bit_idx);
  61. else
  62. reg &= ~BIT(gate->bit_idx);
  63. }
  64. writel(reg, gate->reg);
  65. }
  66. static int clk_gate_enable(struct clk *clk)
  67. {
  68. clk_gate_endisable(clk, 1);
  69. return 0;
  70. }
  71. static int clk_gate_disable(struct clk *clk)
  72. {
  73. clk_gate_endisable(clk, 0);
  74. return 0;
  75. }
  76. int clk_gate_is_enabled(struct clk *clk)
  77. {
  78. struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
  79. dev_get_clk_ptr(clk->dev) : clk);
  80. u32 reg;
  81. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  82. reg = gate->io_gate_val;
  83. #else
  84. reg = readl(gate->reg);
  85. #endif
  86. /* if a set bit disables this clk, flip it before masking */
  87. if (gate->flags & CLK_GATE_SET_TO_DISABLE)
  88. reg ^= BIT(gate->bit_idx);
  89. reg &= BIT(gate->bit_idx);
  90. return reg ? 1 : 0;
  91. }
  92. const struct clk_ops clk_gate_ops = {
  93. .enable = clk_gate_enable,
  94. .disable = clk_gate_disable,
  95. .get_rate = clk_generic_get_rate,
  96. };
  97. struct clk *clk_register_gate(struct device *dev, const char *name,
  98. const char *parent_name, unsigned long flags,
  99. void __iomem *reg, u8 bit_idx,
  100. u8 clk_gate_flags, spinlock_t *lock)
  101. {
  102. struct clk_gate *gate;
  103. struct clk *clk;
  104. int ret;
  105. if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
  106. if (bit_idx > 15) {
  107. pr_err("gate bit exceeds LOWORD field\n");
  108. return ERR_PTR(-EINVAL);
  109. }
  110. }
  111. /* allocate the gate */
  112. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  113. if (!gate)
  114. return ERR_PTR(-ENOMEM);
  115. /* struct clk_gate assignments */
  116. gate->reg = reg;
  117. gate->bit_idx = bit_idx;
  118. gate->flags = clk_gate_flags;
  119. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  120. gate->io_gate_val = *(u32 *)reg;
  121. #endif
  122. clk = &gate->clk;
  123. ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
  124. if (ret) {
  125. kfree(gate);
  126. return ERR_PTR(ret);
  127. }
  128. return clk;
  129. }
  130. U_BOOT_DRIVER(clk_gate) = {
  131. .name = UBOOT_DM_CLK_GATE,
  132. .id = UCLASS_CLK,
  133. .ops = &clk_gate_ops,
  134. .flags = DM_FLAG_PRE_RELOC,
  135. };