clk_ast2500.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/scu_ast2500.h>
  10. #include <dm/lists.h>
  11. #include <dt-bindings/clock/ast2500-scu.h>
  12. #include <linux/err.h>
  13. /*
  14. * MAC Clock Delay settings, taken from Aspeed SDK
  15. */
  16. #define RGMII_TXCLK_ODLY 8
  17. #define RMII_RXCLK_IDLY 2
  18. /*
  19. * TGMII Clock Duty constants, taken from Aspeed SDK
  20. */
  21. #define RGMII2_TXCK_DUTY 0x66
  22. #define RGMII1_TXCK_DUTY 0x64
  23. #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /*
  26. * Clock divider/multiplier configuration struct.
  27. * For H-PLL and M-PLL the formula is
  28. * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
  29. * M - Numerator
  30. * N - Denumerator
  31. * P - Post Divider
  32. * They have the same layout in their control register.
  33. *
  34. * D-PLL and D2-PLL have extra divider (OD + 1), which is not
  35. * yet needed and ignored by clock configurations.
  36. */
  37. struct ast2500_div_config {
  38. unsigned int num;
  39. unsigned int denum;
  40. unsigned int post_div;
  41. };
  42. /*
  43. * Get the rate of the M-PLL clock from input clock frequency and
  44. * the value of the M-PLL Parameter Register.
  45. */
  46. static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
  47. {
  48. const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
  49. const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
  50. >> SCU_MPLL_DENUM_SHIFT;
  51. const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
  52. >> SCU_MPLL_POST_SHIFT;
  53. return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
  54. }
  55. /*
  56. * Get the rate of the H-PLL clock from input clock frequency and
  57. * the value of the H-PLL Parameter Register.
  58. */
  59. static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
  60. {
  61. const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
  62. const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
  63. >> SCU_HPLL_DENUM_SHIFT;
  64. const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
  65. >> SCU_HPLL_POST_SHIFT;
  66. return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
  67. }
  68. static ulong ast2500_get_clkin(struct ast2500_scu *scu)
  69. {
  70. return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
  71. ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
  72. }
  73. /**
  74. * Get current rate or uart clock
  75. *
  76. * @scu SCU registers
  77. * @uart_index UART index, 1-5
  78. *
  79. * @return current setting for uart clock rate
  80. */
  81. static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
  82. {
  83. /*
  84. * ast2500 datasheet is very confusing when it comes to UART clocks,
  85. * especially when CLKIN = 25 MHz. The settings are in
  86. * different registers and it is unclear how they interact.
  87. *
  88. * This has only been tested with default settings and CLKIN = 24 MHz.
  89. */
  90. ulong uart_clkin;
  91. if (readl(&scu->misc_ctrl2) &
  92. (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
  93. uart_clkin = 192 * 1000 * 1000;
  94. else
  95. uart_clkin = 24 * 1000 * 1000;
  96. if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
  97. uart_clkin /= 13;
  98. return uart_clkin;
  99. }
  100. static ulong ast2500_clk_get_rate(struct clk *clk)
  101. {
  102. struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
  103. ulong clkin = ast2500_get_clkin(priv->scu);
  104. ulong rate;
  105. switch (clk->id) {
  106. case PLL_HPLL:
  107. case ARMCLK:
  108. /*
  109. * This ignores dynamic/static slowdown of ARMCLK and may
  110. * be inaccurate.
  111. */
  112. rate = ast2500_get_hpll_rate(clkin,
  113. readl(&priv->scu->h_pll_param));
  114. break;
  115. case MCLK_DDR:
  116. rate = ast2500_get_mpll_rate(clkin,
  117. readl(&priv->scu->m_pll_param));
  118. break;
  119. case BCLK_PCLK:
  120. {
  121. ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
  122. & SCU_PCLK_DIV_MASK)
  123. >> SCU_PCLK_DIV_SHIFT);
  124. rate = ast2500_get_hpll_rate(clkin,
  125. readl(&priv->
  126. scu->h_pll_param));
  127. rate = rate / apb_div;
  128. }
  129. break;
  130. case BCLK_SDCLK:
  131. {
  132. ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
  133. & SCU_SDCLK_DIV_MASK)
  134. >> SCU_SDCLK_DIV_SHIFT);
  135. rate = ast2500_get_hpll_rate(clkin,
  136. readl(&priv->
  137. scu->h_pll_param));
  138. rate = rate / apb_div;
  139. }
  140. break;
  141. case PCLK_UART1:
  142. rate = ast2500_get_uart_clk_rate(priv->scu, 1);
  143. break;
  144. case PCLK_UART2:
  145. rate = ast2500_get_uart_clk_rate(priv->scu, 2);
  146. break;
  147. case PCLK_UART3:
  148. rate = ast2500_get_uart_clk_rate(priv->scu, 3);
  149. break;
  150. case PCLK_UART4:
  151. rate = ast2500_get_uart_clk_rate(priv->scu, 4);
  152. break;
  153. case PCLK_UART5:
  154. rate = ast2500_get_uart_clk_rate(priv->scu, 5);
  155. break;
  156. default:
  157. return -ENOENT;
  158. }
  159. return rate;
  160. }
  161. struct ast2500_clock_config {
  162. ulong input_rate;
  163. ulong rate;
  164. struct ast2500_div_config cfg;
  165. };
  166. static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
  167. { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
  168. };
  169. static bool ast2500_get_clock_config_default(ulong input_rate,
  170. ulong requested_rate,
  171. struct ast2500_div_config *cfg)
  172. {
  173. int i;
  174. for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
  175. const struct ast2500_clock_config *default_cfg =
  176. &ast2500_clock_config_defaults[i];
  177. if (default_cfg->input_rate == input_rate &&
  178. default_cfg->rate == requested_rate) {
  179. *cfg = default_cfg->cfg;
  180. return true;
  181. }
  182. }
  183. return false;
  184. }
  185. /*
  186. * @input_rate - the rate of input clock in Hz
  187. * @requested_rate - desired output rate in Hz
  188. * @div - this is an IN/OUT parameter, at input all fields of the config
  189. * need to be set to their maximum allowed values.
  190. * The result (the best config we could find), would also be returned
  191. * in this structure.
  192. *
  193. * @return The clock rate, when the resulting div_config is used.
  194. */
  195. static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
  196. struct ast2500_div_config *cfg)
  197. {
  198. /*
  199. * The assumption is that kHz precision is good enough and
  200. * also enough to avoid overflow when multiplying.
  201. */
  202. const ulong input_rate_khz = input_rate / 1000;
  203. const ulong rate_khz = requested_rate / 1000;
  204. const struct ast2500_div_config max_vals = *cfg;
  205. struct ast2500_div_config it = { 0, 0, 0 };
  206. ulong delta = rate_khz;
  207. ulong new_rate_khz = 0;
  208. /*
  209. * Look for a well known frequency first.
  210. */
  211. if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
  212. return requested_rate;
  213. for (; it.denum <= max_vals.denum; ++it.denum) {
  214. for (it.post_div = 0; it.post_div <= max_vals.post_div;
  215. ++it.post_div) {
  216. it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
  217. * (it.denum + 1);
  218. if (it.num > max_vals.num)
  219. continue;
  220. new_rate_khz = (input_rate_khz
  221. * ((it.num + 1) / (it.denum + 1)))
  222. / (it.post_div + 1);
  223. /* Keep the rate below requested one. */
  224. if (new_rate_khz > rate_khz)
  225. continue;
  226. if (new_rate_khz - rate_khz < delta) {
  227. delta = new_rate_khz - rate_khz;
  228. *cfg = it;
  229. if (delta == 0)
  230. return new_rate_khz * 1000;
  231. }
  232. }
  233. }
  234. return new_rate_khz * 1000;
  235. }
  236. static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
  237. {
  238. ulong clkin = ast2500_get_clkin(scu);
  239. u32 mpll_reg;
  240. struct ast2500_div_config div_cfg = {
  241. .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
  242. .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
  243. .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
  244. };
  245. ast2500_calc_clock_config(clkin, rate, &div_cfg);
  246. mpll_reg = readl(&scu->m_pll_param);
  247. mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
  248. | SCU_MPLL_DENUM_MASK);
  249. mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
  250. | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
  251. | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
  252. ast_scu_unlock(scu);
  253. writel(mpll_reg, &scu->m_pll_param);
  254. ast_scu_lock(scu);
  255. return ast2500_get_mpll_rate(clkin, mpll_reg);
  256. }
  257. static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
  258. {
  259. ulong clkin = ast2500_get_clkin(scu);
  260. ulong hpll_rate = ast2500_get_hpll_rate(clkin,
  261. readl(&scu->h_pll_param));
  262. ulong required_rate;
  263. u32 hwstrap;
  264. u32 divisor;
  265. u32 reset_bit;
  266. u32 clkstop_bit;
  267. /*
  268. * According to data sheet, for 10/100 mode the MAC clock frequency
  269. * should be at least 25MHz and for 1000 mode at least 100MHz
  270. */
  271. hwstrap = readl(&scu->hwstrap);
  272. if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
  273. required_rate = 100 * 1000 * 1000;
  274. else
  275. required_rate = 25 * 1000 * 1000;
  276. divisor = hpll_rate / required_rate;
  277. if (divisor < 4) {
  278. /* Clock can't run fast enough, but let's try anyway */
  279. debug("MAC clock too slow\n");
  280. divisor = 4;
  281. } else if (divisor > 16) {
  282. /* Can't slow down the clock enough, but let's try anyway */
  283. debug("MAC clock too fast\n");
  284. divisor = 16;
  285. }
  286. switch (index) {
  287. case 1:
  288. reset_bit = SCU_SYSRESET_MAC1;
  289. clkstop_bit = SCU_CLKSTOP_MAC1;
  290. break;
  291. case 2:
  292. reset_bit = SCU_SYSRESET_MAC2;
  293. clkstop_bit = SCU_CLKSTOP_MAC2;
  294. break;
  295. default:
  296. return -EINVAL;
  297. }
  298. ast_scu_unlock(scu);
  299. clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
  300. ((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
  301. /*
  302. * Disable MAC, start its clock and re-enable it.
  303. * The procedure and the delays (100us & 10ms) are
  304. * specified in the datasheet.
  305. */
  306. setbits_le32(&scu->sysreset_ctrl1, reset_bit);
  307. udelay(100);
  308. clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
  309. mdelay(10);
  310. clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
  311. writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
  312. | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
  313. &scu->clk_duty_sel);
  314. ast_scu_lock(scu);
  315. return required_rate;
  316. }
  317. static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
  318. {
  319. /*
  320. * The values and the meaning of the next three
  321. * parameters are undocumented. Taken from Aspeed SDK.
  322. *
  323. * TODO(clg@kaod.org): the SIP and SIC values depend on the
  324. * Numerator value
  325. */
  326. const u32 d2_pll_ext_param = 0x2c;
  327. const u32 d2_pll_sip = 0x11;
  328. const u32 d2_pll_sic = 0x18;
  329. u32 clk_delay_settings =
  330. (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
  331. | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
  332. | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
  333. | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
  334. struct ast2500_div_config div_cfg = {
  335. .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
  336. .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
  337. .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
  338. };
  339. ulong clkin = ast2500_get_clkin(scu);
  340. ulong new_rate;
  341. ast_scu_unlock(scu);
  342. writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
  343. | SCU_D2PLL_EXT1_OFF
  344. | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
  345. /*
  346. * Select USB2.0 port1 PHY clock as a clock source for GCRT.
  347. * This would disconnect it from D2-PLL.
  348. */
  349. clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
  350. SCU_MISC_GCRT_USB20CLK);
  351. new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
  352. writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
  353. | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
  354. | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
  355. | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
  356. | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
  357. &scu->d2_pll_param);
  358. clrbits_le32(&scu->d2_pll_ext_param[0],
  359. SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
  360. clrsetbits_le32(&scu->misc_ctrl2,
  361. SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
  362. | SCU_MISC2_RGMII_CLKDIV_MASK |
  363. SCU_MISC2_RMII_CLKDIV_MASK,
  364. (4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
  365. writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
  366. writel(clk_delay_settings, &scu->mac_clk_delay_100M);
  367. writel(clk_delay_settings, &scu->mac_clk_delay_10M);
  368. ast_scu_lock(scu);
  369. return new_rate;
  370. }
  371. static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
  372. {
  373. struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
  374. ulong new_rate;
  375. switch (clk->id) {
  376. case PLL_MPLL:
  377. case MCLK_DDR:
  378. new_rate = ast2500_configure_ddr(priv->scu, rate);
  379. break;
  380. case PLL_D2PLL:
  381. new_rate = ast2500_configure_d2pll(priv->scu, rate);
  382. break;
  383. default:
  384. return -ENOENT;
  385. }
  386. return new_rate;
  387. }
  388. static int ast2500_clk_enable(struct clk *clk)
  389. {
  390. struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
  391. switch (clk->id) {
  392. case BCLK_SDCLK:
  393. if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
  394. ast_scu_unlock(priv->scu);
  395. setbits_le32(&priv->scu->sysreset_ctrl1,
  396. SCU_SYSRESET_SDIO);
  397. udelay(100);
  398. clrbits_le32(&priv->scu->clk_stop_ctrl1,
  399. SCU_CLKSTOP_SDCLK);
  400. mdelay(10);
  401. clrbits_le32(&priv->scu->sysreset_ctrl1,
  402. SCU_SYSRESET_SDIO);
  403. ast_scu_lock(priv->scu);
  404. }
  405. break;
  406. /*
  407. * For MAC clocks the clock rate is
  408. * configured based on whether RGMII or RMII mode has been selected
  409. * through hardware strapping.
  410. */
  411. case PCLK_MAC1:
  412. ast2500_configure_mac(priv->scu, 1);
  413. break;
  414. case PCLK_MAC2:
  415. ast2500_configure_mac(priv->scu, 2);
  416. break;
  417. case PLL_D2PLL:
  418. ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
  419. break;
  420. default:
  421. return -ENOENT;
  422. }
  423. return 0;
  424. }
  425. struct clk_ops ast2500_clk_ops = {
  426. .get_rate = ast2500_clk_get_rate,
  427. .set_rate = ast2500_clk_set_rate,
  428. .enable = ast2500_clk_enable,
  429. };
  430. static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
  431. {
  432. struct ast2500_clk_priv *priv = dev_get_priv(dev);
  433. priv->scu = devfdt_get_addr_ptr(dev);
  434. if (IS_ERR(priv->scu))
  435. return PTR_ERR(priv->scu);
  436. return 0;
  437. }
  438. static int ast2500_clk_bind(struct udevice *dev)
  439. {
  440. int ret;
  441. /* The reset driver does not have a device node, so bind it here */
  442. ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
  443. if (ret)
  444. debug("Warning: No reset driver: ret=%d\n", ret);
  445. return 0;
  446. }
  447. static const struct udevice_id ast2500_clk_ids[] = {
  448. { .compatible = "aspeed,ast2500-scu" },
  449. { }
  450. };
  451. U_BOOT_DRIVER(aspeed_ast2500_scu) = {
  452. .name = "aspeed_ast2500_scu",
  453. .id = UCLASS_CLK,
  454. .of_match = ast2500_clk_ids,
  455. .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
  456. .ops = &ast2500_clk_ops,
  457. .bind = ast2500_clk_bind,
  458. .ofdata_to_platdata = ast2500_clk_ofdata_to_platdata,
  459. };