veyron.c 2.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <clk.h>
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <asm/arch-rockchip/clock.h>
  9. #include <dt-bindings/clock/rk3288-cru.h>
  10. #include <linux/err.h>
  11. #include <power/regulator.h>
  12. /*
  13. * We should increase the DDR voltage to 1.2V using the PWM regulator.
  14. * There is a U-Boot driver for this but it may need to add support for the
  15. * 'voltage-table' property.
  16. */
  17. #ifndef CONFIG_SPL_BUILD
  18. #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
  19. static int veyron_init(void)
  20. {
  21. struct udevice *dev;
  22. struct clk clk;
  23. int ret;
  24. ret = regulator_get_by_platname("vdd_arm", &dev);
  25. if (ret) {
  26. debug("Cannot set regulator name\n");
  27. return ret;
  28. }
  29. /* Slowly raise to max CPU voltage to prevent overshoot */
  30. ret = regulator_set_value(dev, 1200000);
  31. if (ret)
  32. return ret;
  33. udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
  34. ret = regulator_set_value(dev, 1400000);
  35. if (ret)
  36. return ret;
  37. udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
  38. ret = rockchip_get_clk(&clk.dev);
  39. if (ret)
  40. return ret;
  41. clk.id = PLL_APLL;
  42. ret = clk_set_rate(&clk, 1800000000);
  43. if (IS_ERR_VALUE(ret))
  44. return ret;
  45. ret = regulator_get_by_platname("vcc33_sd", &dev);
  46. if (ret) {
  47. debug("Cannot get regulator name\n");
  48. return ret;
  49. }
  50. ret = regulator_set_value(dev, 3300000);
  51. if (ret)
  52. return ret;
  53. ret = regulators_enable_boot_on(false);
  54. if (ret) {
  55. debug("%s: Cannot enable boot on regulators\n", __func__);
  56. return ret;
  57. }
  58. return 0;
  59. }
  60. #endif
  61. int board_early_init_f(void)
  62. {
  63. struct udevice *dev;
  64. int ret;
  65. #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
  66. if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
  67. ret = veyron_init();
  68. if (ret)
  69. return ret;
  70. }
  71. #endif
  72. /*
  73. * This init is done in SPL, but when chain-loading U-Boot SPL will
  74. * have been skipped. Allow the clock driver to check if it needs
  75. * setting up.
  76. */
  77. ret = rockchip_get_clk(&dev);
  78. if (ret) {
  79. debug("CLK init failed: %d\n", ret);
  80. return ret;
  81. }
  82. return 0;
  83. }
  84. #endif