km83xx.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. *
  6. * Copyright (C) 2007 Logic Product Development, Inc.
  7. * Peter Barada <peterb@logicpd.com>
  8. *
  9. * Copyright (C) 2007 MontaVista Software, Inc.
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * (C) Copyright 2008 - 2010
  13. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14. */
  15. #include <common.h>
  16. #include <ioports.h>
  17. #include <mpc83xx.h>
  18. #include <i2c.h>
  19. #include <miiphy.h>
  20. #include <asm/io.h>
  21. #include <asm/mmu.h>
  22. #include <asm/processor.h>
  23. #include <pci.h>
  24. #include <linux/libfdt.h>
  25. #include <post.h>
  26. #include "../common/common.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  29. const qe_iop_conf_t qe_iop_conf_tab[] = {
  30. /* port pin dir open_drain assign */
  31. #if defined(CONFIG_ARCH_MPC8360)
  32. /* MDIO */
  33. {0, 1, 3, 0, 2}, /* MDIO */
  34. {0, 2, 1, 0, 1}, /* MDC */
  35. /* UCC4 - UEC */
  36. {1, 14, 1, 0, 1}, /* TxD0 */
  37. {1, 15, 1, 0, 1}, /* TxD1 */
  38. {1, 20, 2, 0, 1}, /* RxD0 */
  39. {1, 21, 2, 0, 1}, /* RxD1 */
  40. {1, 18, 1, 0, 1}, /* TX_EN */
  41. {1, 26, 2, 0, 1}, /* RX_DV */
  42. {1, 27, 2, 0, 1}, /* RX_ER */
  43. {1, 24, 2, 0, 1}, /* COL */
  44. {1, 25, 2, 0, 1}, /* CRS */
  45. {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
  46. {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
  47. /* DUART - UART2 */
  48. {5, 0, 1, 0, 2}, /* UART2_SOUT */
  49. {5, 2, 1, 0, 1}, /* UART2_RTS */
  50. {5, 3, 2, 0, 2}, /* UART2_SIN */
  51. {5, 1, 2, 0, 3}, /* UART2_CTS */
  52. #elif !defined(CONFIG_ARCH_MPC8309)
  53. /* Local Bus */
  54. {0, 16, 1, 0, 3}, /* LA00 */
  55. {0, 17, 1, 0, 3}, /* LA01 */
  56. {0, 18, 1, 0, 3}, /* LA02 */
  57. {0, 19, 1, 0, 3}, /* LA03 */
  58. {0, 20, 1, 0, 3}, /* LA04 */
  59. {0, 21, 1, 0, 3}, /* LA05 */
  60. {0, 22, 1, 0, 3}, /* LA06 */
  61. {0, 23, 1, 0, 3}, /* LA07 */
  62. {0, 24, 1, 0, 3}, /* LA08 */
  63. {0, 25, 1, 0, 3}, /* LA09 */
  64. {0, 26, 1, 0, 3}, /* LA10 */
  65. {0, 27, 1, 0, 3}, /* LA11 */
  66. {0, 28, 1, 0, 3}, /* LA12 */
  67. {0, 29, 1, 0, 3}, /* LA13 */
  68. {0, 30, 1, 0, 3}, /* LA14 */
  69. {0, 31, 1, 0, 3}, /* LA15 */
  70. /* MDIO */
  71. {3, 4, 3, 0, 2}, /* MDIO */
  72. {3, 5, 1, 0, 2}, /* MDC */
  73. /* UCC4 - UEC */
  74. {1, 18, 1, 0, 1}, /* TxD0 */
  75. {1, 19, 1, 0, 1}, /* TxD1 */
  76. {1, 22, 2, 0, 1}, /* RxD0 */
  77. {1, 23, 2, 0, 1}, /* RxD1 */
  78. {1, 26, 2, 0, 1}, /* RxER */
  79. {1, 28, 2, 0, 1}, /* Rx_DV */
  80. {1, 30, 1, 0, 1}, /* TxEN */
  81. {1, 31, 2, 0, 1}, /* CRS */
  82. {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
  83. #endif
  84. /* END of table */
  85. {0, 0, 0, 0, QE_IOP_TAB_END},
  86. };
  87. #if defined(CONFIG_SUVD3)
  88. const uint upma_table[] = {
  89. 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
  90. 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
  91. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
  92. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
  93. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
  94. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
  95. 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
  96. 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
  97. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
  98. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
  99. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
  100. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
  101. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
  102. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
  103. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
  104. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
  105. };
  106. #endif
  107. static int piggy_present(void)
  108. {
  109. struct km_bec_fpga __iomem *base =
  110. (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
  111. return in_8(&base->bprth) & PIGGY_PRESENT;
  112. }
  113. #if defined(CONFIG_KMVECT1)
  114. int ethernet_present(void)
  115. {
  116. /* ethernet port connected to simple switch without piggy */
  117. return 1;
  118. }
  119. #else
  120. int ethernet_present(void)
  121. {
  122. return piggy_present();
  123. }
  124. #endif
  125. int board_early_init_r(void)
  126. {
  127. struct km_bec_fpga *base =
  128. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  129. #if defined(CONFIG_SUVD3)
  130. immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  131. fsl_lbc_t *lbc = &immap->im_lbc;
  132. u32 *mxmr = &lbc->mamr;
  133. #endif
  134. #if defined(CONFIG_ARCH_MPC8360)
  135. unsigned short svid;
  136. /*
  137. * Because of errata in the UCCs, we have to write to the reserved
  138. * registers to slow the clocks down.
  139. */
  140. svid = SVR_REV(mfspr(SVR));
  141. switch (svid) {
  142. case 0x0020:
  143. /*
  144. * MPC8360ECE.pdf QE_ENET10 table 4:
  145. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  146. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  147. */
  148. setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
  149. break;
  150. case 0x0021:
  151. /*
  152. * MPC8360ECE.pdf QE_ENET10 table 4:
  153. * IMMR + 0x14AC[24:27] = 1010
  154. */
  155. clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
  156. 0x00000050, 0x000000a0);
  157. break;
  158. }
  159. #endif
  160. /* enable the PHY on the PIGGY */
  161. setbits_8(&base->pgy_eth, 0x01);
  162. /* enable the Unit LED (green) */
  163. setbits_8(&base->oprth, WRL_BOOT);
  164. /* enable Application Buffer */
  165. setbits_8(&base->oprtl, OPRTL_XBUFENA);
  166. #if defined(CONFIG_SUVD3)
  167. /* configure UPMA for APP1 */
  168. upmconfig(UPMA, (uint *) upma_table,
  169. sizeof(upma_table) / sizeof(uint));
  170. out_be32(mxmr, CONFIG_SYS_MAMR);
  171. #endif
  172. return 0;
  173. }
  174. int misc_init_r(void)
  175. {
  176. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  177. return 0;
  178. }
  179. #if defined(CONFIG_KMVECT1)
  180. #include <mv88e6352.h>
  181. /* Marvell MV88E6122 switch configuration */
  182. static struct mv88e_sw_reg extsw_conf[] = {
  183. /* port 1, FRONT_MDI, autoneg */
  184. { PORT(1), PORT_PHY, NO_SPEED_FOR },
  185. { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  186. { PHY(1), PHY_1000_CTRL, NO_ADV },
  187. { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
  188. { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
  189. FULL_DUPLEX },
  190. /* port 2, unused */
  191. { PORT(2), PORT_CTRL, PORT_DIS },
  192. { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
  193. { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  194. /* port 3, BP_MII (CPU), PHY mode, 100BASE */
  195. { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  196. /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
  197. { PORT(4), PORT_STATUS, NO_PHY_DETECT },
  198. { PORT(4), PORT_PHY, SPEED_1000_FOR },
  199. { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  200. /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
  201. { PORT(5), PORT_STATUS, NO_PHY_DETECT },
  202. { PORT(5), PORT_PHY, SPEED_1000_FOR },
  203. { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  204. /*
  205. * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
  206. * acc . MV-S300889-00D.pdf , clause 4.5
  207. */
  208. { PORT(5), 0x1A, 0xADB1 },
  209. /* port 6, unused, this port has no phy */
  210. { PORT(6), PORT_CTRL, PORT_DIS },
  211. /*
  212. * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
  213. * acc . MV-S300889-00D.pdf , clause 4.5
  214. */
  215. { PORT(5), 0x1A, 0xADB1 },
  216. };
  217. #endif
  218. int last_stage_init(void)
  219. {
  220. #if defined(CONFIG_KMVECT1)
  221. struct km_bec_fpga __iomem *base =
  222. (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
  223. u8 tmp_reg;
  224. /* Release mv88e6122 from reset */
  225. tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
  226. out_8(&base->res1[0], tmp_reg); /* GP28 as output */
  227. tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
  228. out_8(&base->gprt3, tmp_reg);
  229. /* configure MV88E6122 switch */
  230. char *name = "UEC2";
  231. if (miiphy_set_current_dev(name))
  232. return 0;
  233. mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
  234. ARRAY_SIZE(extsw_conf));
  235. mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
  236. if (piggy_present()) {
  237. env_set("ethact", "UEC2");
  238. env_set("netdev", "eth1");
  239. puts("using PIGGY for network boot\n");
  240. } else {
  241. env_set("netdev", "eth0");
  242. puts("using frontport for network boot\n");
  243. }
  244. #endif
  245. #if defined(CONFIG_KMCOGE5NE)
  246. struct bfticu_iomap *base =
  247. (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
  248. u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
  249. if (dip_switch != 0) {
  250. /* start bootloader */
  251. puts("DIP: Enabled\n");
  252. env_set("actual_bank", "0");
  253. }
  254. #endif
  255. set_km_env();
  256. return 0;
  257. }
  258. static int fixed_sdram(void)
  259. {
  260. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  261. u32 msize = 0;
  262. u32 ddr_size;
  263. u32 ddr_size_log2;
  264. out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
  265. out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
  266. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  267. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  268. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  269. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  270. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  271. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  272. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  273. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  274. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  275. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  276. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  277. udelay(200);
  278. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  279. msize = CONFIG_SYS_DDR_SIZE << 20;
  280. disable_addr_trans();
  281. msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
  282. enable_addr_trans();
  283. msize /= (1024 * 1024);
  284. if (CONFIG_SYS_DDR_SIZE != msize) {
  285. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  286. (ddr_size > 1);
  287. ddr_size = ddr_size >> 1, ddr_size_log2++)
  288. if (ddr_size & 1)
  289. return -1;
  290. out_be32(&im->sysconf.ddrlaw[0].ar,
  291. (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
  292. out_be32(&im->ddr.csbnds[0].csbnds,
  293. (((msize / 16) - 1) & 0xff));
  294. }
  295. return msize;
  296. }
  297. int dram_init(void)
  298. {
  299. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  300. u32 msize = 0;
  301. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  302. return -ENXIO;
  303. out_be32(&im->sysconf.ddrlaw[0].bar,
  304. CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
  305. msize = fixed_sdram();
  306. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  307. /*
  308. * Initialize DDR ECC byte
  309. */
  310. ddr_enable_ecc(msize * 1024 * 1024);
  311. #endif
  312. /* return total bus SDRAM size(bytes) -- DDR */
  313. gd->ram_size = msize * 1024 * 1024;
  314. return 0;
  315. }
  316. int checkboard(void)
  317. {
  318. puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
  319. if (piggy_present())
  320. puts(" with PIGGY.");
  321. puts("\n");
  322. return 0;
  323. }
  324. int ft_board_setup(void *blob, bd_t *bd)
  325. {
  326. ft_cpu_setup(blob, bd);
  327. return 0;
  328. }
  329. #if defined(CONFIG_HUSH_INIT_VAR)
  330. int hush_init_var(void)
  331. {
  332. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  333. return 0;
  334. }
  335. #endif
  336. #if defined(CONFIG_POST)
  337. int post_hotkeys_pressed(void)
  338. {
  339. int testpin = 0;
  340. struct km_bec_fpga *base =
  341. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  342. int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
  343. testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
  344. debug("post_hotkeys_pressed: %d\n", !testpin);
  345. return testpin;
  346. }
  347. ulong post_word_load(void)
  348. {
  349. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  350. debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
  351. return in_le32(addr);
  352. }
  353. void post_word_store(ulong value)
  354. {
  355. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  356. debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
  357. out_le32(addr, value);
  358. }
  359. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  360. {
  361. *vstart = CONFIG_SYS_MEMTEST_START;
  362. *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
  363. debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
  364. return 0;
  365. }
  366. #endif