fsl_lbc.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ASM_PPC_FSL_LBC_H
  6. #define __ASM_PPC_FSL_LBC_H
  7. #include <config.h>
  8. #include <common.h>
  9. #ifdef CONFIG_MPC85xx
  10. void lbc_sdram_init(void);
  11. #endif
  12. /* BR - Base Registers
  13. */
  14. #define BR0 0x5000 /* Register offset to immr */
  15. #define BR1 0x5008
  16. #define BR2 0x5010
  17. #define BR3 0x5018
  18. #define BR4 0x5020
  19. #define BR5 0x5028
  20. #define BR6 0x5030
  21. #define BR7 0x5038
  22. #define BR_BA 0xFFFF8000
  23. #define BR_BA_SHIFT 15
  24. #define BR_XBA 0x00006000
  25. #define BR_XBA_SHIFT 13
  26. #define BR_PS 0x00001800
  27. #define BR_PS_SHIFT 11
  28. #define BR_PS_8 0x00000800 /* Port Size 8 bit */
  29. #define BR_PS_16 0x00001000 /* Port Size 16 bit */
  30. #define BR_PS_32 0x00001800 /* Port Size 32 bit */
  31. #define BR_DECC 0x00000600
  32. #define BR_DECC_SHIFT 9
  33. #define BR_DECC_OFF 0x00000000
  34. #define BR_DECC_CHK 0x00000200
  35. #define BR_DECC_CHK_GEN 0x00000400
  36. #define BR_WP 0x00000100
  37. #define BR_WP_SHIFT 8
  38. #define BR_MSEL 0x000000E0
  39. #define BR_MSEL_SHIFT 5
  40. #define BR_MS_GPCM 0x00000000 /* GPCM */
  41. #if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
  42. #define BR_MS_FCM 0x00000020 /* FCM */
  43. #endif
  44. #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
  45. #define BR_MS_SDRAM 0x00000060 /* SDRAM */
  46. #elif defined(CONFIG_MPC85xx)
  47. #define BR_MS_SDRAM 0x00000000 /* SDRAM */
  48. #endif
  49. #define BR_MS_UPMA 0x00000080 /* UPMA */
  50. #define BR_MS_UPMB 0x000000A0 /* UPMB */
  51. #define BR_MS_UPMC 0x000000C0 /* UPMC */
  52. #if !defined(CONFIG_ARCH_MPC834X)
  53. #define BR_ATOM 0x0000000C
  54. #define BR_ATOM_SHIFT 2
  55. #endif
  56. #define BR_V 0x00000001
  57. #define BR_V_SHIFT 0
  58. #define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT)
  59. #define UPMA 0
  60. #define UPMB 1
  61. #define UPMC 2
  62. #if defined(CONFIG_ARCH_MPC834X)
  63. #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
  64. #else
  65. #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
  66. #endif
  67. /* Convert an address into the right format for the BR registers */
  68. #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
  69. #define BR_PHYS_ADDR(x) \
  70. ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
  71. #else
  72. #define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
  73. #endif
  74. /* OR - Option Registers
  75. */
  76. #define OR0 0x5004 /* Register offset to immr */
  77. #define OR1 0x500C
  78. #define OR2 0x5014
  79. #define OR3 0x501C
  80. #define OR4 0x5024
  81. #define OR5 0x502C
  82. #define OR6 0x5034
  83. #define OR7 0x503C
  84. #define OR_GPCM_AM 0xFFFF8000
  85. #define OR_GPCM_AM_SHIFT 15
  86. #define OR_GPCM_XAM 0x00006000
  87. #define OR_GPCM_XAM_SHIFT 13
  88. #define OR_GPCM_BCTLD 0x00001000
  89. #define OR_GPCM_BCTLD_SHIFT 12
  90. #define OR_GPCM_CSNT 0x00000800
  91. #define OR_GPCM_CSNT_SHIFT 11
  92. #define OR_GPCM_ACS 0x00000600
  93. #define OR_GPCM_ACS_SHIFT 9
  94. #define OR_GPCM_ACS_DIV2 0x00000600
  95. #define OR_GPCM_ACS_DIV4 0x00000400
  96. #define OR_GPCM_XACS 0x00000100
  97. #define OR_GPCM_XACS_SHIFT 8
  98. #define OR_GPCM_SCY 0x000000F0
  99. #define OR_GPCM_SCY_SHIFT 4
  100. #define OR_GPCM_SCY_1 0x00000010
  101. #define OR_GPCM_SCY_2 0x00000020
  102. #define OR_GPCM_SCY_3 0x00000030
  103. #define OR_GPCM_SCY_4 0x00000040
  104. #define OR_GPCM_SCY_5 0x00000050
  105. #define OR_GPCM_SCY_6 0x00000060
  106. #define OR_GPCM_SCY_7 0x00000070
  107. #define OR_GPCM_SCY_8 0x00000080
  108. #define OR_GPCM_SCY_9 0x00000090
  109. #define OR_GPCM_SCY_10 0x000000a0
  110. #define OR_GPCM_SCY_11 0x000000b0
  111. #define OR_GPCM_SCY_12 0x000000c0
  112. #define OR_GPCM_SCY_13 0x000000d0
  113. #define OR_GPCM_SCY_14 0x000000e0
  114. #define OR_GPCM_SCY_15 0x000000f0
  115. #define OR_GPCM_SETA 0x00000008
  116. #define OR_GPCM_SETA_SHIFT 3
  117. #define OR_GPCM_TRLX 0x00000004
  118. #define OR_GPCM_TRLX_SHIFT 2
  119. #define OR_GPCM_TRLX_CLEAR 0x00000000
  120. #define OR_GPCM_TRLX_SET 0x00000004
  121. #define OR_GPCM_EHTR 0x00000002
  122. #define OR_GPCM_EHTR_SHIFT 1
  123. #define OR_GPCM_EHTR_CLEAR 0x00000000
  124. #define OR_GPCM_EHTR_SET 0x00000002
  125. #if !defined(CONFIG_ARCH_MPC8308)
  126. #define OR_GPCM_EAD 0x00000001
  127. #define OR_GPCM_EAD_SHIFT 0
  128. #endif
  129. /* helpers to convert values into an OR address mask (GPCM mode) */
  130. #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
  131. #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
  132. #define OR_FCM_AM 0xFFFF8000
  133. #define OR_FCM_AM_SHIFT 15
  134. #define OR_FCM_XAM 0x00006000
  135. #define OR_FCM_XAM_SHIFT 13
  136. #define OR_FCM_BCTLD 0x00001000
  137. #define OR_FCM_BCTLD_SHIFT 12
  138. #define OR_FCM_PGS 0x00000400
  139. #define OR_FCM_PGS_SHIFT 10
  140. #define OR_FCM_CSCT 0x00000200
  141. #define OR_FCM_CSCT_SHIFT 9
  142. #define OR_FCM_CST 0x00000100
  143. #define OR_FCM_CST_SHIFT 8
  144. #define OR_FCM_CHT 0x00000080
  145. #define OR_FCM_CHT_SHIFT 7
  146. #define OR_FCM_SCY 0x00000070
  147. #define OR_FCM_SCY_SHIFT 4
  148. #define OR_FCM_SCY_1 0x00000010
  149. #define OR_FCM_SCY_2 0x00000020
  150. #define OR_FCM_SCY_3 0x00000030
  151. #define OR_FCM_SCY_4 0x00000040
  152. #define OR_FCM_SCY_5 0x00000050
  153. #define OR_FCM_SCY_6 0x00000060
  154. #define OR_FCM_SCY_7 0x00000070
  155. #define OR_FCM_RST 0x00000008
  156. #define OR_FCM_RST_SHIFT 3
  157. #define OR_FCM_TRLX 0x00000004
  158. #define OR_FCM_TRLX_SHIFT 2
  159. #define OR_FCM_EHTR 0x00000002
  160. #define OR_FCM_EHTR_SHIFT 1
  161. #define OR_UPM_AM 0xFFFF8000
  162. #define OR_UPM_AM_SHIFT 15
  163. #define OR_UPM_XAM 0x00006000
  164. #define OR_UPM_XAM_SHIFT 13
  165. #define OR_UPM_BCTLD 0x00001000
  166. #define OR_UPM_BCTLD_SHIFT 12
  167. #define OR_UPM_BI 0x00000100
  168. #define OR_UPM_BI_SHIFT 8
  169. #define OR_UPM_TRLX 0x00000004
  170. #define OR_UPM_TRLX_SHIFT 2
  171. #define OR_UPM_EHTR 0x00000002
  172. #define OR_UPM_EHTR_SHIFT 1
  173. #define OR_UPM_EAD 0x00000001
  174. #define OR_UPM_EAD_SHIFT 0
  175. #define OR_SDRAM_AM 0xFFFF8000
  176. #define OR_SDRAM_AM_SHIFT 15
  177. #define OR_SDRAM_XAM 0x00006000
  178. #define OR_SDRAM_XAM_SHIFT 13
  179. #define OR_SDRAM_COLS 0x00001C00
  180. #define OR_SDRAM_COLS_SHIFT 10
  181. #define OR_SDRAM_MIN_COLS 7
  182. #define OR_SDRAM_ROWS 0x000001C0
  183. #define OR_SDRAM_ROWS_SHIFT 6
  184. #define OR_SDRAM_MIN_ROWS 9
  185. #define OR_SDRAM_PMSEL 0x00000020
  186. #define OR_SDRAM_PMSEL_SHIFT 5
  187. #define OR_SDRAM_EAD 0x00000001
  188. #define OR_SDRAM_EAD_SHIFT 0
  189. #define OR_AM_32KB 0xFFFF8000
  190. #define OR_AM_64KB 0xFFFF0000
  191. #define OR_AM_128KB 0xFFFE0000
  192. #define OR_AM_256KB 0xFFFC0000
  193. #define OR_AM_512KB 0xFFF80000
  194. #define OR_AM_1MB 0xFFF00000
  195. #define OR_AM_2MB 0xFFE00000
  196. #define OR_AM_4MB 0xFFC00000
  197. #define OR_AM_8MB 0xFF800000
  198. #define OR_AM_16MB 0xFF000000
  199. #define OR_AM_32MB 0xFE000000
  200. #define OR_AM_64MB 0xFC000000
  201. #define OR_AM_128MB 0xF8000000
  202. #define OR_AM_256MB 0xF0000000
  203. #define OR_AM_512MB 0xE0000000
  204. #define OR_AM_1GB 0xC0000000
  205. #define OR_AM_2GB 0x80000000
  206. #define OR_AM_4GB 0x00000000
  207. /* MxMR - UPM Machine A/B/C Mode Registers
  208. */
  209. #define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
  210. #define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
  211. #define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
  212. #define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
  213. #define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
  214. #define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
  215. #define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
  216. #define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
  217. #define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
  218. #define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
  219. #define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
  220. #define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
  221. #define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
  222. #define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
  223. #define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
  224. #define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
  225. #define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
  226. #define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
  227. #define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
  228. #define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
  229. #define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
  230. #define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
  231. #define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
  232. #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
  233. #define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
  234. #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
  235. #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
  236. #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
  237. #define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */
  238. #define MxMR_OP_NORM 0x00000000 /* Normal Operation */
  239. #define MxMR_OP_WARR 0x10000000 /* Write to Array */
  240. #define MxMR_OP_RARR 0x20000000 /* Read from Array */
  241. #define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
  242. #define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
  243. #define MxMR_RFEN 0x40000000 /* Refresh Enable */
  244. #define MxMR_BSEL 0x80000000 /* Bus Select */
  245. #define LBLAWAR_EN 0x80000000
  246. #define LBLAWAR_4KB 0x0000000B
  247. #define LBLAWAR_8KB 0x0000000C
  248. #define LBLAWAR_16KB 0x0000000D
  249. #define LBLAWAR_32KB 0x0000000E
  250. #define LBLAWAR_64KB 0x0000000F
  251. #define LBLAWAR_128KB 0x00000010
  252. #define LBLAWAR_256KB 0x00000011
  253. #define LBLAWAR_512KB 0x00000012
  254. #define LBLAWAR_1MB 0x00000013
  255. #define LBLAWAR_2MB 0x00000014
  256. #define LBLAWAR_4MB 0x00000015
  257. #define LBLAWAR_8MB 0x00000016
  258. #define LBLAWAR_16MB 0x00000017
  259. #define LBLAWAR_32MB 0x00000018
  260. #define LBLAWAR_64MB 0x00000019
  261. #define LBLAWAR_128MB 0x0000001A
  262. #define LBLAWAR_256MB 0x0000001B
  263. #define LBLAWAR_512MB 0x0000001C
  264. #define LBLAWAR_1GB 0x0000001D
  265. #define LBLAWAR_2GB 0x0000001E
  266. /* LBCR - Local Bus Configuration Register
  267. */
  268. #define LBCR_LDIS 0x80000000
  269. #define LBCR_LDIS_SHIFT 31
  270. #define LBCR_BCTLC 0x00C00000
  271. #define LBCR_BCTLC_SHIFT 22
  272. #define LBCR_LPBSE 0x00020000
  273. #define LBCR_LPBSE_SHIFT 17
  274. #define LBCR_EPAR 0x00010000
  275. #define LBCR_EPAR_SHIFT 16
  276. #define LBCR_BMT 0x0000FF00
  277. #define LBCR_BMT_SHIFT 8
  278. #define LBCR_BMTPS 0x0000000F
  279. #define LBCR_BMTPS_SHIFT 0
  280. /* LCRR - Clock Ratio Register
  281. */
  282. #define LCRR_DBYP 0x80000000
  283. #define LCRR_DBYP_SHIFT 31
  284. #define LCRR_BUFCMDC 0x30000000
  285. #define LCRR_BUFCMDC_SHIFT 28
  286. #define LCRR_BUFCMDC_1 0x10000000
  287. #define LCRR_BUFCMDC_2 0x20000000
  288. #define LCRR_BUFCMDC_3 0x30000000
  289. #define LCRR_BUFCMDC_4 0x00000000
  290. #define LCRR_ECL 0x03000000
  291. #define LCRR_ECL_SHIFT 24
  292. #define LCRR_ECL_4 0x00000000
  293. #define LCRR_ECL_5 0x01000000
  294. #define LCRR_ECL_6 0x02000000
  295. #define LCRR_ECL_7 0x03000000
  296. #define LCRR_EADC 0x00030000
  297. #define LCRR_EADC_SHIFT 16
  298. #define LCRR_EADC_1 0x00010000
  299. #define LCRR_EADC_2 0x00020000
  300. #define LCRR_EADC_3 0x00030000
  301. #define LCRR_EADC_4 0x00000000
  302. /* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
  303. * should always be zero on older parts that have a four bit CLKDIV.
  304. */
  305. #define LCRR_CLKDIV 0x0000001F
  306. #define LCRR_CLKDIV_SHIFT 0
  307. #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
  308. defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
  309. defined(CONFIG_ARCH_MPC8560)
  310. #define LCRR_CLKDIV_2 0x00000002
  311. #define LCRR_CLKDIV_4 0x00000004
  312. #define LCRR_CLKDIV_8 0x00000008
  313. #elif defined(CONFIG_FSL_CORENET)
  314. #define LCRR_CLKDIV_8 0x00000002
  315. #define LCRR_CLKDIV_16 0x00000004
  316. #define LCRR_CLKDIV_32 0x00000008
  317. #else
  318. #define LCRR_CLKDIV_4 0x00000002
  319. #define LCRR_CLKDIV_8 0x00000004
  320. #define LCRR_CLKDIV_16 0x00000008
  321. #endif
  322. /* LTEDR - Transfer Error Check Disable Register
  323. */
  324. #define LTEDR_BMD 0x80000000 /* Bus monitor disable */
  325. #define LTEDR_PARD 0x20000000 /* Parity error checking disabled */
  326. #define LTEDR_WPD 0x04000000 /* Write protect error checking diable */
  327. #define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */
  328. #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
  329. #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
  330. /* FMR - Flash Mode Register
  331. */
  332. #define FMR_CWTO 0x0000F000
  333. #define FMR_CWTO_SHIFT 12
  334. #define FMR_BOOT 0x00000800
  335. #define FMR_ECCM 0x00000100
  336. #define FMR_AL 0x00000030
  337. #define FMR_AL_SHIFT 4
  338. #define FMR_OP 0x00000003
  339. #define FMR_OP_SHIFT 0
  340. /* FIR - Flash Instruction Register
  341. */
  342. #define FIR_OP0 0xF0000000
  343. #define FIR_OP0_SHIFT 28
  344. #define FIR_OP1 0x0F000000
  345. #define FIR_OP1_SHIFT 24
  346. #define FIR_OP2 0x00F00000
  347. #define FIR_OP2_SHIFT 20
  348. #define FIR_OP3 0x000F0000
  349. #define FIR_OP3_SHIFT 16
  350. #define FIR_OP4 0x0000F000
  351. #define FIR_OP4_SHIFT 12
  352. #define FIR_OP5 0x00000F00
  353. #define FIR_OP5_SHIFT 8
  354. #define FIR_OP6 0x000000F0
  355. #define FIR_OP6_SHIFT 4
  356. #define FIR_OP7 0x0000000F
  357. #define FIR_OP7_SHIFT 0
  358. #define FIR_OP_NOP 0x0 /* No operation and end of sequence */
  359. #define FIR_OP_CA 0x1 /* Issue current column address */
  360. #define FIR_OP_PA 0x2 /* Issue current block+page address */
  361. #define FIR_OP_UA 0x3 /* Issue user defined address */
  362. #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
  363. #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
  364. #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
  365. #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
  366. #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
  367. #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
  368. #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
  369. #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
  370. #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
  371. #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
  372. #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
  373. #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
  374. /* FCR - Flash Command Register
  375. */
  376. #define FCR_CMD0 0xFF000000
  377. #define FCR_CMD0_SHIFT 24
  378. #define FCR_CMD1 0x00FF0000
  379. #define FCR_CMD1_SHIFT 16
  380. #define FCR_CMD2 0x0000FF00
  381. #define FCR_CMD2_SHIFT 8
  382. #define FCR_CMD3 0x000000FF
  383. #define FCR_CMD3_SHIFT 0
  384. /* FBAR - Flash Block Address Register
  385. */
  386. #define FBAR_BLK 0x00FFFFFF
  387. /* FPAR - Flash Page Address Register
  388. */
  389. #define FPAR_SP_PI 0x00007C00
  390. #define FPAR_SP_PI_SHIFT 10
  391. #define FPAR_SP_MS 0x00000200
  392. #define FPAR_SP_CI 0x000001FF
  393. #define FPAR_SP_CI_SHIFT 0
  394. #define FPAR_LP_PI 0x0003F000
  395. #define FPAR_LP_PI_SHIFT 12
  396. #define FPAR_LP_MS 0x00000800
  397. #define FPAR_LP_CI 0x000007FF
  398. #define FPAR_LP_CI_SHIFT 0
  399. /* LSDMR - SDRAM Machine Mode Register
  400. */
  401. #define LSDMR_RFEN (1 << (31 - 1))
  402. #define LSDMR_BSMA1516 (3 << (31 - 10))
  403. #define LSDMR_BSMA1617 (4 << (31 - 10))
  404. #define LSDMR_RFCR5 (3 << (31 - 16))
  405. #define LSDMR_RFCR16 (7 << (31 - 16))
  406. #define LSDMR_PRETOACT3 (3 << (31 - 19))
  407. #define LSDMR_PRETOACT7 (7 << (31 - 19))
  408. #define LSDMR_ACTTORW3 (3 << (31 - 22))
  409. #define LSDMR_ACTTORW7 (7 << (31 - 22))
  410. #define LSDMR_ACTTORW6 (6 << (31 - 22))
  411. #define LSDMR_BL8 (1 << (31 - 23))
  412. #define LSDMR_WRC2 (2 << (31 - 27))
  413. #define LSDMR_WRC4 (0 << (31 - 27))
  414. #define LSDMR_BUFCMD (1 << (31 - 29))
  415. #define LSDMR_CL3 (3 << (31 - 31))
  416. #define LSDMR_OP_NORMAL (0 << (31 - 4))
  417. #define LSDMR_OP_ARFRSH (1 << (31 - 4))
  418. #define LSDMR_OP_SRFRSH (2 << (31 - 4))
  419. #define LSDMR_OP_MRW (3 << (31 - 4))
  420. #define LSDMR_OP_PRECH (4 << (31 - 4))
  421. #define LSDMR_OP_PCHALL (5 << (31 - 4))
  422. #define LSDMR_OP_ACTBNK (6 << (31 - 4))
  423. #define LSDMR_OP_RWINV (7 << (31 - 4))
  424. /* LTESR - Transfer Error Status Register
  425. */
  426. #define LTESR_BM 0x80000000
  427. #define LTESR_FCT 0x40000000
  428. #define LTESR_PAR 0x20000000
  429. #define LTESR_WP 0x04000000
  430. #define LTESR_ATMW 0x00800000
  431. #define LTESR_ATMR 0x00400000
  432. #define LTESR_CS 0x00080000
  433. #define LTESR_CC 0x00000001
  434. #ifndef __ASSEMBLY__
  435. #include <asm/io.h>
  436. extern void print_lbc_regs(void);
  437. extern void init_early_memctl_regs(void);
  438. extern void upmconfig(uint upm, uint *table, uint size);
  439. #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
  440. #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
  441. #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
  442. #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
  443. #define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
  444. #define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
  445. #define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
  446. typedef struct lbc_bank {
  447. u32 br;
  448. u32 or;
  449. } lbc_bank_t;
  450. /* Local Bus Controller Registers */
  451. typedef struct fsl_lbc {
  452. lbc_bank_t bank[8];
  453. u8 res1[40];
  454. u32 mar; /* LBC UPM Addr */
  455. u8 res2[4];
  456. u32 mamr; /* LBC UPMA Mode */
  457. u32 mbmr; /* LBC UPMB Mode */
  458. u32 mcmr; /* LBC UPMC Mode */
  459. u8 res3[8];
  460. u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
  461. u32 mdr; /* LBC UPM Data */
  462. #ifdef CONFIG_FSL_ELBC
  463. u8 res4[4];
  464. u32 lsor;
  465. u8 res5[12];
  466. u32 lurt; /* LBC UPM Refresh Timer */
  467. u8 res6[4];
  468. #else
  469. u8 res4[8];
  470. u32 lsdmr; /* LBC SDRAM Mode */
  471. u8 res5[8];
  472. u32 lurt; /* LBC UPM Refresh Timer */
  473. u32 lsrt; /* LBC SDRAM Refresh Timer */
  474. #endif
  475. u8 res7[8];
  476. u32 ltesr; /* LBC Transfer Error Status */
  477. u32 ltedr; /* LBC Transfer Error Disable */
  478. u32 lteir; /* LBC Transfer Error IRQ */
  479. u32 lteatr; /* LBC Transfer Error Attrs */
  480. u32 ltear; /* LBC Transfer Error Addr */
  481. u8 res8[12];
  482. u32 lbcr; /* LBC Configuration */
  483. u32 lcrr; /* LBC Clock Ratio */
  484. #ifdef CONFIG_NAND_FSL_ELBC
  485. u8 res9[0x8];
  486. u32 fmr; /* Flash Mode Register */
  487. u32 fir; /* Flash Instruction Register */
  488. u32 fcr; /* Flash Command Register */
  489. u32 fbar; /* Flash Block Addr Register */
  490. u32 fpar; /* Flash Page Addr Register */
  491. u32 fbcr; /* Flash Byte Count Register */
  492. u8 res10[0xF08];
  493. #else
  494. u8 res9[0xF28];
  495. #endif
  496. } fsl_lbc_t;
  497. #endif /* __ASSEMBLY__ */
  498. #endif /* __ASM_PPC_FSL_LBC_H */