speed.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  7. */
  8. #ifndef CONFIG_CLK_MPC83XX
  9. #include <common.h>
  10. #include <mpc83xx.h>
  11. #include <command.h>
  12. #include <asm/processor.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /* ----------------------------------------------------------------- */
  15. typedef enum {
  16. _unk,
  17. _off,
  18. _byp,
  19. _x8,
  20. _x4,
  21. _x2,
  22. _x1,
  23. _1x,
  24. _1_5x,
  25. _2x,
  26. _2_5x,
  27. _3x
  28. } mult_t;
  29. typedef struct {
  30. mult_t core_csb_ratio;
  31. mult_t vco_divider;
  32. } corecnf_t;
  33. static corecnf_t corecnf_tab[] = {
  34. {_byp, _byp}, /* 0x00 */
  35. {_byp, _byp}, /* 0x01 */
  36. {_byp, _byp}, /* 0x02 */
  37. {_byp, _byp}, /* 0x03 */
  38. {_byp, _byp}, /* 0x04 */
  39. {_byp, _byp}, /* 0x05 */
  40. {_byp, _byp}, /* 0x06 */
  41. {_byp, _byp}, /* 0x07 */
  42. {_1x, _x2}, /* 0x08 */
  43. {_1x, _x4}, /* 0x09 */
  44. {_1x, _x8}, /* 0x0A */
  45. {_1x, _x8}, /* 0x0B */
  46. {_1_5x, _x2}, /* 0x0C */
  47. {_1_5x, _x4}, /* 0x0D */
  48. {_1_5x, _x8}, /* 0x0E */
  49. {_1_5x, _x8}, /* 0x0F */
  50. {_2x, _x2}, /* 0x10 */
  51. {_2x, _x4}, /* 0x11 */
  52. {_2x, _x8}, /* 0x12 */
  53. {_2x, _x8}, /* 0x13 */
  54. {_2_5x, _x2}, /* 0x14 */
  55. {_2_5x, _x4}, /* 0x15 */
  56. {_2_5x, _x8}, /* 0x16 */
  57. {_2_5x, _x8}, /* 0x17 */
  58. {_3x, _x2}, /* 0x18 */
  59. {_3x, _x4}, /* 0x19 */
  60. {_3x, _x8}, /* 0x1A */
  61. {_3x, _x8}, /* 0x1B */
  62. };
  63. /* ----------------------------------------------------------------- */
  64. /*
  65. *
  66. */
  67. int get_clocks(void)
  68. {
  69. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  70. u32 pci_sync_in;
  71. u8 spmf;
  72. u8 clkin_div;
  73. u32 sccr;
  74. u32 corecnf_tab_index;
  75. u8 corepll;
  76. u32 lcrr;
  77. u32 csb_clk;
  78. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  79. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
  80. u32 tsec1_clk;
  81. u32 tsec2_clk;
  82. u32 usbdr_clk;
  83. #elif defined(CONFIG_ARCH_MPC8309)
  84. u32 usbdr_clk;
  85. #endif
  86. #ifdef CONFIG_ARCH_MPC834X
  87. u32 usbmph_clk;
  88. #endif
  89. u32 core_clk;
  90. u32 i2c1_clk;
  91. #if !defined(CONFIG_ARCH_MPC832X)
  92. u32 i2c2_clk;
  93. #endif
  94. #if defined(CONFIG_ARCH_MPC8315)
  95. u32 tdm_clk;
  96. #endif
  97. #if defined(CONFIG_FSL_ESDHC)
  98. u32 sdhc_clk;
  99. #endif
  100. #if !defined(CONFIG_ARCH_MPC8309)
  101. u32 enc_clk;
  102. #endif
  103. u32 lbiu_clk;
  104. u32 lclk_clk;
  105. u32 mem_clk;
  106. #if defined(CONFIG_ARCH_MPC8360)
  107. u32 mem_sec_clk;
  108. #endif
  109. #if defined(CONFIG_QE)
  110. u32 qepmf;
  111. u32 qepdf;
  112. u32 qe_clk;
  113. u32 brg_clk;
  114. #endif
  115. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  116. defined(CONFIG_MPC837x)
  117. u32 pciexp1_clk;
  118. u32 pciexp2_clk;
  119. #endif
  120. #if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
  121. u32 sata_clk;
  122. #endif
  123. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  124. return -1;
  125. clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
  126. if (im->reset.rcwh & HRCWH_PCI_HOST) {
  127. #if defined(CONFIG_83XX_CLKIN)
  128. pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
  129. #else
  130. pci_sync_in = 0xDEADBEEF;
  131. #endif
  132. } else {
  133. #if defined(CONFIG_83XX_PCICLK)
  134. pci_sync_in = CONFIG_83XX_PCICLK;
  135. #else
  136. pci_sync_in = 0xDEADBEEF;
  137. #endif
  138. }
  139. spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  140. csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
  141. sccr = im->clk.sccr;
  142. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  143. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
  144. switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
  145. case 0:
  146. tsec1_clk = 0;
  147. break;
  148. case 1:
  149. tsec1_clk = csb_clk;
  150. break;
  151. case 2:
  152. tsec1_clk = csb_clk / 2;
  153. break;
  154. case 3:
  155. tsec1_clk = csb_clk / 3;
  156. break;
  157. default:
  158. /* unknown SCCR_TSEC1CM value */
  159. return -2;
  160. }
  161. #endif
  162. #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
  163. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
  164. switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
  165. case 0:
  166. usbdr_clk = 0;
  167. break;
  168. case 1:
  169. usbdr_clk = csb_clk;
  170. break;
  171. case 2:
  172. usbdr_clk = csb_clk / 2;
  173. break;
  174. case 3:
  175. usbdr_clk = csb_clk / 3;
  176. break;
  177. default:
  178. /* unknown SCCR_USBDRCM value */
  179. return -3;
  180. }
  181. #endif
  182. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
  183. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
  184. switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
  185. case 0:
  186. tsec2_clk = 0;
  187. break;
  188. case 1:
  189. tsec2_clk = csb_clk;
  190. break;
  191. case 2:
  192. tsec2_clk = csb_clk / 2;
  193. break;
  194. case 3:
  195. tsec2_clk = csb_clk / 3;
  196. break;
  197. default:
  198. /* unknown SCCR_TSEC2CM value */
  199. return -4;
  200. }
  201. #elif defined(CONFIG_ARCH_MPC8313)
  202. tsec2_clk = tsec1_clk;
  203. if (!(sccr & SCCR_TSEC1ON))
  204. tsec1_clk = 0;
  205. if (!(sccr & SCCR_TSEC2ON))
  206. tsec2_clk = 0;
  207. #endif
  208. #if defined(CONFIG_ARCH_MPC834X)
  209. switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
  210. case 0:
  211. usbmph_clk = 0;
  212. break;
  213. case 1:
  214. usbmph_clk = csb_clk;
  215. break;
  216. case 2:
  217. usbmph_clk = csb_clk / 2;
  218. break;
  219. case 3:
  220. usbmph_clk = csb_clk / 3;
  221. break;
  222. default:
  223. /* unknown SCCR_USBMPHCM value */
  224. return -5;
  225. }
  226. if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
  227. /* if USB MPH clock is not disabled and
  228. * USB DR clock is not disabled then
  229. * USB MPH & USB DR must have the same rate
  230. */
  231. return -6;
  232. }
  233. #endif
  234. #if !defined(CONFIG_ARCH_MPC8309)
  235. switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
  236. case 0:
  237. enc_clk = 0;
  238. break;
  239. case 1:
  240. enc_clk = csb_clk;
  241. break;
  242. case 2:
  243. enc_clk = csb_clk / 2;
  244. break;
  245. case 3:
  246. enc_clk = csb_clk / 3;
  247. break;
  248. default:
  249. /* unknown SCCR_ENCCM value */
  250. return -7;
  251. }
  252. #endif
  253. #if defined(CONFIG_FSL_ESDHC)
  254. switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
  255. case 0:
  256. sdhc_clk = 0;
  257. break;
  258. case 1:
  259. sdhc_clk = csb_clk;
  260. break;
  261. case 2:
  262. sdhc_clk = csb_clk / 2;
  263. break;
  264. case 3:
  265. sdhc_clk = csb_clk / 3;
  266. break;
  267. default:
  268. /* unknown SCCR_SDHCCM value */
  269. return -8;
  270. }
  271. #endif
  272. #if defined(CONFIG_ARCH_MPC8315)
  273. switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
  274. case 0:
  275. tdm_clk = 0;
  276. break;
  277. case 1:
  278. tdm_clk = csb_clk;
  279. break;
  280. case 2:
  281. tdm_clk = csb_clk / 2;
  282. break;
  283. case 3:
  284. tdm_clk = csb_clk / 3;
  285. break;
  286. default:
  287. /* unknown SCCR_TDMCM value */
  288. return -8;
  289. }
  290. #endif
  291. #if defined(CONFIG_ARCH_MPC834X)
  292. i2c1_clk = tsec2_clk;
  293. #elif defined(CONFIG_ARCH_MPC8360)
  294. i2c1_clk = csb_clk;
  295. #elif defined(CONFIG_ARCH_MPC832X)
  296. i2c1_clk = enc_clk;
  297. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  298. i2c1_clk = enc_clk;
  299. #elif defined(CONFIG_FSL_ESDHC)
  300. i2c1_clk = sdhc_clk;
  301. #elif defined(CONFIG_MPC837x)
  302. i2c1_clk = enc_clk;
  303. #elif defined(CONFIG_ARCH_MPC8309)
  304. i2c1_clk = csb_clk;
  305. #endif
  306. #if !defined(CONFIG_ARCH_MPC832X)
  307. i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
  308. #endif
  309. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  310. defined(CONFIG_MPC837x)
  311. switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
  312. case 0:
  313. pciexp1_clk = 0;
  314. break;
  315. case 1:
  316. pciexp1_clk = csb_clk;
  317. break;
  318. case 2:
  319. pciexp1_clk = csb_clk / 2;
  320. break;
  321. case 3:
  322. pciexp1_clk = csb_clk / 3;
  323. break;
  324. default:
  325. /* unknown SCCR_PCIEXP1CM value */
  326. return -9;
  327. }
  328. switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
  329. case 0:
  330. pciexp2_clk = 0;
  331. break;
  332. case 1:
  333. pciexp2_clk = csb_clk;
  334. break;
  335. case 2:
  336. pciexp2_clk = csb_clk / 2;
  337. break;
  338. case 3:
  339. pciexp2_clk = csb_clk / 3;
  340. break;
  341. default:
  342. /* unknown SCCR_PCIEXP2CM value */
  343. return -10;
  344. }
  345. #endif
  346. #if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
  347. switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
  348. case 0:
  349. sata_clk = 0;
  350. break;
  351. case 1:
  352. sata_clk = csb_clk;
  353. break;
  354. case 2:
  355. sata_clk = csb_clk / 2;
  356. break;
  357. case 3:
  358. sata_clk = csb_clk / 3;
  359. break;
  360. default:
  361. /* unknown SCCR_SATA1CM value */
  362. return -11;
  363. }
  364. #endif
  365. lbiu_clk = csb_clk *
  366. (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
  367. lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
  368. switch (lcrr) {
  369. case 2:
  370. case 4:
  371. case 8:
  372. lclk_clk = lbiu_clk / lcrr;
  373. break;
  374. default:
  375. /* unknown lcrr */
  376. return -12;
  377. }
  378. mem_clk = csb_clk *
  379. (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
  380. corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
  381. #if defined(CONFIG_ARCH_MPC8360)
  382. mem_sec_clk = csb_clk * (1 +
  383. ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
  384. #endif
  385. corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
  386. if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
  387. /* corecnf_tab_index is too high, possibly wrong value */
  388. return -11;
  389. }
  390. switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
  391. case _byp:
  392. case _x1:
  393. case _1x:
  394. core_clk = csb_clk;
  395. break;
  396. case _1_5x:
  397. core_clk = (3 * csb_clk) / 2;
  398. break;
  399. case _2x:
  400. core_clk = 2 * csb_clk;
  401. break;
  402. case _2_5x:
  403. core_clk = (5 * csb_clk) / 2;
  404. break;
  405. case _3x:
  406. core_clk = 3 * csb_clk;
  407. break;
  408. default:
  409. /* unknown core to csb ratio */
  410. return -13;
  411. }
  412. #if defined(CONFIG_QE)
  413. qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
  414. qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
  415. qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
  416. brg_clk = qe_clk / 2;
  417. #endif
  418. gd->arch.csb_clk = csb_clk;
  419. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  420. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
  421. gd->arch.tsec1_clk = tsec1_clk;
  422. gd->arch.tsec2_clk = tsec2_clk;
  423. gd->arch.usbdr_clk = usbdr_clk;
  424. #elif defined(CONFIG_ARCH_MPC8309)
  425. gd->arch.usbdr_clk = usbdr_clk;
  426. #endif
  427. #if defined(CONFIG_ARCH_MPC834X)
  428. gd->arch.usbmph_clk = usbmph_clk;
  429. #endif
  430. #if defined(CONFIG_ARCH_MPC8315)
  431. gd->arch.tdm_clk = tdm_clk;
  432. #endif
  433. #if defined(CONFIG_FSL_ESDHC)
  434. gd->arch.sdhc_clk = sdhc_clk;
  435. #endif
  436. gd->arch.core_clk = core_clk;
  437. gd->arch.i2c1_clk = i2c1_clk;
  438. #if !defined(CONFIG_ARCH_MPC832X)
  439. gd->arch.i2c2_clk = i2c2_clk;
  440. #endif
  441. #if !defined(CONFIG_ARCH_MPC8309)
  442. gd->arch.enc_clk = enc_clk;
  443. #endif
  444. gd->arch.lbiu_clk = lbiu_clk;
  445. gd->arch.lclk_clk = lclk_clk;
  446. gd->mem_clk = mem_clk;
  447. #if defined(CONFIG_ARCH_MPC8360)
  448. gd->arch.mem_sec_clk = mem_sec_clk;
  449. #endif
  450. #if defined(CONFIG_QE)
  451. gd->arch.qe_clk = qe_clk;
  452. gd->arch.brg_clk = brg_clk;
  453. #endif
  454. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  455. defined(CONFIG_MPC837x)
  456. gd->arch.pciexp1_clk = pciexp1_clk;
  457. gd->arch.pciexp2_clk = pciexp2_clk;
  458. #endif
  459. #if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
  460. gd->arch.sata_clk = sata_clk;
  461. #endif
  462. gd->pci_clk = pci_sync_in;
  463. gd->cpu_clk = gd->arch.core_clk;
  464. gd->bus_clk = gd->arch.csb_clk;
  465. return 0;
  466. }
  467. /********************************************
  468. * get_bus_freq
  469. * return system bus freq in Hz
  470. *********************************************/
  471. ulong get_bus_freq(ulong dummy)
  472. {
  473. return gd->arch.csb_clk;
  474. }
  475. /********************************************
  476. * get_ddr_freq
  477. * return ddr bus freq in Hz
  478. *********************************************/
  479. ulong get_ddr_freq(ulong dummy)
  480. {
  481. return gd->mem_clk;
  482. }
  483. static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  484. {
  485. char buf[32];
  486. printf("Clock configuration:\n");
  487. printf(" Core: %-4s MHz\n",
  488. strmhz(buf, gd->arch.core_clk));
  489. printf(" Coherent System Bus: %-4s MHz\n",
  490. strmhz(buf, gd->arch.csb_clk));
  491. #if defined(CONFIG_QE)
  492. printf(" QE: %-4s MHz\n",
  493. strmhz(buf, gd->arch.qe_clk));
  494. printf(" BRG: %-4s MHz\n",
  495. strmhz(buf, gd->arch.brg_clk));
  496. #endif
  497. printf(" Local Bus Controller:%-4s MHz\n",
  498. strmhz(buf, gd->arch.lbiu_clk));
  499. printf(" Local Bus: %-4s MHz\n",
  500. strmhz(buf, gd->arch.lclk_clk));
  501. printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
  502. #if defined(CONFIG_ARCH_MPC8360)
  503. printf(" DDR Secondary: %-4s MHz\n",
  504. strmhz(buf, gd->arch.mem_sec_clk));
  505. #endif
  506. #if !defined(CONFIG_ARCH_MPC8309)
  507. printf(" SEC: %-4s MHz\n",
  508. strmhz(buf, gd->arch.enc_clk));
  509. #endif
  510. printf(" I2C1: %-4s MHz\n",
  511. strmhz(buf, gd->arch.i2c1_clk));
  512. #if !defined(CONFIG_ARCH_MPC832X)
  513. printf(" I2C2: %-4s MHz\n",
  514. strmhz(buf, gd->arch.i2c2_clk));
  515. #endif
  516. #if defined(CONFIG_ARCH_MPC8315)
  517. printf(" TDM: %-4s MHz\n",
  518. strmhz(buf, gd->arch.tdm_clk));
  519. #endif
  520. #if defined(CONFIG_FSL_ESDHC)
  521. printf(" SDHC: %-4s MHz\n",
  522. strmhz(buf, gd->arch.sdhc_clk));
  523. #endif
  524. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  525. defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
  526. printf(" TSEC1: %-4s MHz\n",
  527. strmhz(buf, gd->arch.tsec1_clk));
  528. printf(" TSEC2: %-4s MHz\n",
  529. strmhz(buf, gd->arch.tsec2_clk));
  530. printf(" USB DR: %-4s MHz\n",
  531. strmhz(buf, gd->arch.usbdr_clk));
  532. #elif defined(CONFIG_ARCH_MPC8309)
  533. printf(" USB DR: %-4s MHz\n",
  534. strmhz(buf, gd->arch.usbdr_clk));
  535. #endif
  536. #if defined(CONFIG_ARCH_MPC834X)
  537. printf(" USB MPH: %-4s MHz\n",
  538. strmhz(buf, gd->arch.usbmph_clk));
  539. #endif
  540. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  541. defined(CONFIG_MPC837x)
  542. printf(" PCIEXP1: %-4s MHz\n",
  543. strmhz(buf, gd->arch.pciexp1_clk));
  544. printf(" PCIEXP2: %-4s MHz\n",
  545. strmhz(buf, gd->arch.pciexp2_clk));
  546. #endif
  547. #if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
  548. printf(" SATA: %-4s MHz\n",
  549. strmhz(buf, gd->arch.sata_clk));
  550. #endif
  551. return 0;
  552. }
  553. U_BOOT_CMD(clocks, 1, 0, do_clocks,
  554. "print clock configuration",
  555. " clocks"
  556. );
  557. #endif