sunxi_dw_hdmi.c 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Allwinner DW HDMI bridge
  4. *
  5. * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  6. */
  7. #include <common.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <dw_hdmi.h>
  11. #include <edid.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/lcdc.h>
  15. struct sunxi_dw_hdmi_priv {
  16. struct dw_hdmi hdmi;
  17. int mux;
  18. };
  19. struct sunxi_hdmi_phy {
  20. u32 pol;
  21. u32 res1[3];
  22. u32 read_en;
  23. u32 unscramble;
  24. u32 res2[2];
  25. u32 ctrl;
  26. u32 unk1;
  27. u32 unk2;
  28. u32 pll;
  29. u32 clk;
  30. u32 unk3;
  31. u32 status;
  32. };
  33. #define HDMI_PHY_OFFS 0x10000
  34. static int sunxi_dw_hdmi_get_divider(uint clock)
  35. {
  36. /*
  37. * Due to missing documentaion of HDMI PHY, we know correct
  38. * settings only for following four PHY dividers. Select one
  39. * based on clock speed.
  40. */
  41. if (clock <= 27000000)
  42. return 11;
  43. else if (clock <= 74250000)
  44. return 4;
  45. else if (clock <= 148500000)
  46. return 2;
  47. else
  48. return 1;
  49. }
  50. static void sunxi_dw_hdmi_phy_init(void)
  51. {
  52. struct sunxi_hdmi_phy * const phy =
  53. (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  54. unsigned long tmo;
  55. u32 tmp;
  56. /*
  57. * HDMI PHY settings are taken as-is from Allwinner BSP code.
  58. * There is no documentation.
  59. */
  60. writel(0, &phy->ctrl);
  61. setbits_le32(&phy->ctrl, BIT(0));
  62. udelay(5);
  63. setbits_le32(&phy->ctrl, BIT(16));
  64. setbits_le32(&phy->ctrl, BIT(1));
  65. udelay(10);
  66. setbits_le32(&phy->ctrl, BIT(2));
  67. udelay(5);
  68. setbits_le32(&phy->ctrl, BIT(3));
  69. udelay(40);
  70. setbits_le32(&phy->ctrl, BIT(19));
  71. udelay(100);
  72. setbits_le32(&phy->ctrl, BIT(18));
  73. setbits_le32(&phy->ctrl, 7 << 4);
  74. /* Note that Allwinner code doesn't fail in case of timeout */
  75. tmo = timer_get_us() + 2000;
  76. while ((readl(&phy->status) & 0x80) == 0) {
  77. if (timer_get_us() > tmo) {
  78. printf("Warning: HDMI PHY init timeout!\n");
  79. break;
  80. }
  81. }
  82. setbits_le32(&phy->ctrl, 0xf << 8);
  83. setbits_le32(&phy->ctrl, BIT(7));
  84. writel(0x39dc5040, &phy->pll);
  85. writel(0x80084343, &phy->clk);
  86. udelay(10000);
  87. writel(1, &phy->unk3);
  88. setbits_le32(&phy->pll, BIT(25));
  89. udelay(100000);
  90. tmp = (readl(&phy->status) & 0x1f800) >> 11;
  91. setbits_le32(&phy->pll, BIT(31) | BIT(30));
  92. setbits_le32(&phy->pll, tmp);
  93. writel(0x01FF0F7F, &phy->ctrl);
  94. writel(0x80639000, &phy->unk1);
  95. writel(0x0F81C405, &phy->unk2);
  96. /* enable read access to HDMI controller */
  97. writel(0x54524545, &phy->read_en);
  98. /* descramble register offsets */
  99. writel(0x42494E47, &phy->unscramble);
  100. }
  101. static int sunxi_dw_hdmi_get_plug_in_status(void)
  102. {
  103. struct sunxi_hdmi_phy * const phy =
  104. (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  105. return !!(readl(&phy->status) & (1 << 19));
  106. }
  107. static int sunxi_dw_hdmi_wait_for_hpd(void)
  108. {
  109. ulong start;
  110. start = get_timer(0);
  111. do {
  112. if (sunxi_dw_hdmi_get_plug_in_status())
  113. return 0;
  114. udelay(100);
  115. } while (get_timer(start) < 300);
  116. return -1;
  117. }
  118. static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
  119. {
  120. struct sunxi_hdmi_phy * const phy =
  121. (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  122. int div = sunxi_dw_hdmi_get_divider(clock);
  123. u32 tmp;
  124. /*
  125. * Unfortunately, we don't know much about those magic
  126. * numbers. They are taken from Allwinner BSP driver.
  127. */
  128. switch (div) {
  129. case 1:
  130. writel(0x30dc5fc0, &phy->pll);
  131. writel(0x800863C0 | (phy_div - 1), &phy->clk);
  132. mdelay(10);
  133. writel(0x00000001, &phy->unk3);
  134. setbits_le32(&phy->pll, BIT(25));
  135. mdelay(200);
  136. tmp = (readl(&phy->status) & 0x1f800) >> 11;
  137. setbits_le32(&phy->pll, BIT(31) | BIT(30));
  138. if (tmp < 0x3d)
  139. setbits_le32(&phy->pll, tmp + 2);
  140. else
  141. setbits_le32(&phy->pll, 0x3f);
  142. mdelay(100);
  143. writel(0x01FFFF7F, &phy->ctrl);
  144. writel(0x8063b000, &phy->unk1);
  145. writel(0x0F8246B5, &phy->unk2);
  146. break;
  147. case 2:
  148. writel(0x39dc5040, &phy->pll);
  149. writel(0x80084380 | (phy_div - 1), &phy->clk);
  150. mdelay(10);
  151. writel(0x00000001, &phy->unk3);
  152. setbits_le32(&phy->pll, BIT(25));
  153. mdelay(100);
  154. tmp = (readl(&phy->status) & 0x1f800) >> 11;
  155. setbits_le32(&phy->pll, BIT(31) | BIT(30));
  156. setbits_le32(&phy->pll, tmp);
  157. writel(0x01FFFF7F, &phy->ctrl);
  158. writel(0x8063a800, &phy->unk1);
  159. writel(0x0F81C485, &phy->unk2);
  160. break;
  161. case 4:
  162. writel(0x39dc5040, &phy->pll);
  163. writel(0x80084340 | (phy_div - 1), &phy->clk);
  164. mdelay(10);
  165. writel(0x00000001, &phy->unk3);
  166. setbits_le32(&phy->pll, BIT(25));
  167. mdelay(100);
  168. tmp = (readl(&phy->status) & 0x1f800) >> 11;
  169. setbits_le32(&phy->pll, BIT(31) | BIT(30));
  170. setbits_le32(&phy->pll, tmp);
  171. writel(0x01FFFF7F, &phy->ctrl);
  172. writel(0x8063b000, &phy->unk1);
  173. writel(0x0F81C405, &phy->unk2);
  174. break;
  175. case 11:
  176. writel(0x39dc5040, &phy->pll);
  177. writel(0x80084300 | (phy_div - 1), &phy->clk);
  178. mdelay(10);
  179. writel(0x00000001, &phy->unk3);
  180. setbits_le32(&phy->pll, BIT(25));
  181. mdelay(100);
  182. tmp = (readl(&phy->status) & 0x1f800) >> 11;
  183. setbits_le32(&phy->pll, BIT(31) | BIT(30));
  184. setbits_le32(&phy->pll, tmp);
  185. writel(0x01FFFF7F, &phy->ctrl);
  186. writel(0x8063b000, &phy->unk1);
  187. writel(0x0F81C405, &phy->unk2);
  188. break;
  189. }
  190. }
  191. static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
  192. {
  193. int value, n, m, div, diff;
  194. int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
  195. /*
  196. * Find the lowest divider resulting in a matching clock. If there
  197. * is no match, pick the closest lower clock, as monitors tend to
  198. * not sync to higher frequencies.
  199. */
  200. for (div = 1; div <= 16; div++) {
  201. int target = clk_khz * div;
  202. if (target < 192000)
  203. continue;
  204. if (target > 912000)
  205. continue;
  206. for (m = 1; m <= 16; m++) {
  207. n = (m * target) / 24000;
  208. if (n >= 1 && n <= 128) {
  209. value = (24000 * n) / m / div;
  210. diff = clk_khz - value;
  211. if (diff < best_diff) {
  212. best_diff = diff;
  213. best_m = m;
  214. best_n = n;
  215. best_div = div;
  216. }
  217. }
  218. }
  219. }
  220. *phy_div = best_div;
  221. clock_set_pll3_factors(best_m, best_n);
  222. debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
  223. clk_khz, (clock_get_pll3() / 1000) / best_div,
  224. best_n, best_m, best_div);
  225. }
  226. static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
  227. int bpp)
  228. {
  229. struct sunxi_ccm_reg * const ccm =
  230. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  231. int div = clock_get_pll3() / edid->pixelclock.typ;
  232. struct sunxi_lcdc_reg *lcdc;
  233. if (mux == 0) {
  234. lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
  235. /* Reset off */
  236. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
  237. /* Clock on */
  238. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
  239. writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
  240. &ccm->lcd0_clk_cfg);
  241. } else {
  242. lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
  243. /* Reset off */
  244. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
  245. /* Clock on */
  246. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
  247. writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
  248. &ccm->lcd1_clk_cfg);
  249. }
  250. lcdc_init(lcdc);
  251. lcdc_tcon1_mode_set(lcdc, edid, false, false);
  252. lcdc_enable(lcdc, bpp);
  253. }
  254. static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
  255. {
  256. int phy_div;
  257. sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
  258. sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
  259. return 0;
  260. }
  261. static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  262. {
  263. struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
  264. return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  265. }
  266. static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
  267. const struct display_timing *edid)
  268. {
  269. struct sunxi_hdmi_phy * const phy =
  270. (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  271. struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
  272. int ret;
  273. ret = dw_hdmi_enable(&priv->hdmi, edid);
  274. if (ret)
  275. return ret;
  276. sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
  277. if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
  278. setbits_le32(&phy->pol, 0x200);
  279. if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
  280. setbits_le32(&phy->pol, 0x100);
  281. setbits_le32(&phy->ctrl, 0xf << 12);
  282. /*
  283. * This is last hdmi access before boot, so scramble addresses
  284. * again or othwerwise BSP driver won't work. Dummy read is
  285. * needed or otherwise last write doesn't get written correctly.
  286. */
  287. (void)readb(SUNXI_HDMI_BASE);
  288. writel(0, &phy->unscramble);
  289. return 0;
  290. }
  291. static int sunxi_dw_hdmi_probe(struct udevice *dev)
  292. {
  293. struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
  294. struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
  295. struct sunxi_ccm_reg * const ccm =
  296. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  297. int ret;
  298. /* Set pll3 to 297 MHz */
  299. clock_set_pll3(297000000);
  300. /* Set hdmi parent to pll3 */
  301. clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  302. CCM_HDMI_CTRL_PLL3);
  303. /* Set ahb gating to pass */
  304. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  305. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
  306. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  307. setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
  308. /* Clock on */
  309. setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  310. sunxi_dw_hdmi_phy_init();
  311. ret = sunxi_dw_hdmi_wait_for_hpd();
  312. if (ret < 0) {
  313. debug("hdmi can not get hpd signal\n");
  314. return -1;
  315. }
  316. priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
  317. priv->hdmi.i2c_clk_high = 0xd8;
  318. priv->hdmi.i2c_clk_low = 0xfe;
  319. priv->hdmi.reg_io_width = 1;
  320. priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
  321. priv->mux = uc_plat->source_id;
  322. uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
  323. &priv->hdmi.ddc_bus);
  324. dw_hdmi_init(&priv->hdmi);
  325. return 0;
  326. }
  327. static const struct dm_display_ops sunxi_dw_hdmi_ops = {
  328. .read_edid = sunxi_dw_hdmi_read_edid,
  329. .enable = sunxi_dw_hdmi_enable,
  330. };
  331. U_BOOT_DRIVER(sunxi_dw_hdmi) = {
  332. .name = "sunxi_dw_hdmi",
  333. .id = UCLASS_DISPLAY,
  334. .ops = &sunxi_dw_hdmi_ops,
  335. .probe = sunxi_dw_hdmi_probe,
  336. .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
  337. };
  338. U_BOOT_DEVICE(sunxi_dw_hdmi) = {
  339. .name = "sunxi_dw_hdmi"
  340. };