dw_hdmi.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. * Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  6. */
  7. #include <common.h>
  8. #include <fdtdec.h>
  9. #include <asm/io.h>
  10. #include <i2c.h>
  11. #include <media_bus_format.h>
  12. #include "dw_hdmi.h"
  13. struct tmds_n_cts {
  14. u32 tmds;
  15. u32 cts;
  16. u32 n;
  17. };
  18. static const struct tmds_n_cts n_cts_table[] = {
  19. {
  20. .tmds = 25175000, .n = 6144, .cts = 25175,
  21. }, {
  22. .tmds = 25200000, .n = 6144, .cts = 25200,
  23. }, {
  24. .tmds = 27000000, .n = 6144, .cts = 27000,
  25. }, {
  26. .tmds = 27027000, .n = 6144, .cts = 27027,
  27. }, {
  28. .tmds = 40000000, .n = 6144, .cts = 40000,
  29. }, {
  30. .tmds = 54000000, .n = 6144, .cts = 54000,
  31. }, {
  32. .tmds = 54054000, .n = 6144, .cts = 54054,
  33. }, {
  34. .tmds = 65000000, .n = 6144, .cts = 65000,
  35. }, {
  36. .tmds = 74176000, .n = 11648, .cts = 140625,
  37. }, {
  38. .tmds = 74250000, .n = 6144, .cts = 74250,
  39. }, {
  40. .tmds = 83500000, .n = 6144, .cts = 83500,
  41. }, {
  42. .tmds = 106500000, .n = 6144, .cts = 106500,
  43. }, {
  44. .tmds = 108000000, .n = 6144, .cts = 108000,
  45. }, {
  46. .tmds = 148352000, .n = 5824, .cts = 140625,
  47. }, {
  48. .tmds = 148500000, .n = 6144, .cts = 148500,
  49. }, {
  50. .tmds = 297000000, .n = 5120, .cts = 247500,
  51. }
  52. };
  53. static const u16 csc_coeff_default[3][4] = {
  54. { 0x2000, 0x0000, 0x0000, 0x0000 },
  55. { 0x0000, 0x2000, 0x0000, 0x0000 },
  56. { 0x0000, 0x0000, 0x2000, 0x0000 }
  57. };
  58. static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  59. { 0x2591, 0x1322, 0x074b, 0x0000 },
  60. { 0x6535, 0x2000, 0x7acc, 0x0200 },
  61. { 0x6acd, 0x7534, 0x2000, 0x0200 }
  62. };
  63. static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  64. { 0x2000, 0x6926, 0x74fd, 0x010e },
  65. { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  66. { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  67. };
  68. static void dw_hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
  69. {
  70. switch (hdmi->reg_io_width) {
  71. case 1:
  72. writeb(val, hdmi->ioaddr + offset);
  73. break;
  74. case 4:
  75. writel(val, hdmi->ioaddr + (offset << 2));
  76. break;
  77. default:
  78. debug("reg_io_width has unsupported width!\n");
  79. break;
  80. }
  81. }
  82. static u8 dw_hdmi_read(struct dw_hdmi *hdmi, int offset)
  83. {
  84. switch (hdmi->reg_io_width) {
  85. case 1:
  86. return readb(hdmi->ioaddr + offset);
  87. case 4:
  88. return readl(hdmi->ioaddr + (offset << 2));
  89. default:
  90. debug("reg_io_width has unsupported width!\n");
  91. break;
  92. }
  93. return 0;
  94. }
  95. static u8 (*hdmi_read)(struct dw_hdmi *hdmi, int offset) = dw_hdmi_read;
  96. static void (*hdmi_write)(struct dw_hdmi *hdmi, u8 val, int offset) =
  97. dw_hdmi_write;
  98. static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
  99. {
  100. u8 val = hdmi_read(hdmi, reg) & ~mask;
  101. val |= data & mask;
  102. hdmi_write(hdmi, val, reg);
  103. }
  104. static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts)
  105. {
  106. uint cts3;
  107. uint n3;
  108. /* first set ncts_atomic_write (if present) */
  109. n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
  110. hdmi_write(hdmi, n3, HDMI_AUD_N3);
  111. /* set cts_manual (if present) */
  112. cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
  113. cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
  114. cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
  115. /* write cts values; cts3 must be written first */
  116. hdmi_write(hdmi, cts3, HDMI_AUD_CTS3);
  117. hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
  118. hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1);
  119. /* write n values; n1 must be written last */
  120. n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
  121. hdmi_write(hdmi, n3, HDMI_AUD_N3);
  122. hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
  123. hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3);
  124. hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS);
  125. }
  126. static int hdmi_lookup_n_cts(u32 pixel_clk)
  127. {
  128. int i;
  129. for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
  130. if (pixel_clk <= n_cts_table[i].tmds)
  131. break;
  132. if (i >= ARRAY_SIZE(n_cts_table))
  133. return -1;
  134. return i;
  135. }
  136. static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk)
  137. {
  138. u32 clk_n, clk_cts;
  139. int index;
  140. index = hdmi_lookup_n_cts(pixel_clk);
  141. if (index == -1) {
  142. debug("audio not supported for pixel clk %d\n", pixel_clk);
  143. return;
  144. }
  145. clk_n = n_cts_table[index].n;
  146. clk_cts = n_cts_table[index].cts;
  147. hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts);
  148. }
  149. /*
  150. * this submodule is responsible for the video data synchronization.
  151. * for example, for rgb 4:4:4 input, the data map is defined as
  152. * pin{47~40} <==> r[7:0]
  153. * pin{31~24} <==> g[7:0]
  154. * pin{15~8} <==> b[7:0]
  155. */
  156. static void hdmi_video_sample(struct dw_hdmi *hdmi)
  157. {
  158. u32 color_format;
  159. uint val;
  160. switch (hdmi->hdmi_data.enc_in_bus_format) {
  161. case MEDIA_BUS_FMT_RGB888_1X24:
  162. color_format = 0x01;
  163. break;
  164. case MEDIA_BUS_FMT_RGB101010_1X30:
  165. color_format = 0x03;
  166. break;
  167. case MEDIA_BUS_FMT_RGB121212_1X36:
  168. color_format = 0x05;
  169. break;
  170. case MEDIA_BUS_FMT_RGB161616_1X48:
  171. color_format = 0x07;
  172. break;
  173. case MEDIA_BUS_FMT_YUV8_1X24:
  174. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  175. color_format = 0x09;
  176. break;
  177. case MEDIA_BUS_FMT_YUV10_1X30:
  178. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  179. color_format = 0x0B;
  180. break;
  181. case MEDIA_BUS_FMT_YUV12_1X36:
  182. case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
  183. color_format = 0x0D;
  184. break;
  185. case MEDIA_BUS_FMT_YUV16_1X48:
  186. case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
  187. color_format = 0x0F;
  188. break;
  189. case MEDIA_BUS_FMT_UYVY8_1X16:
  190. color_format = 0x16;
  191. break;
  192. case MEDIA_BUS_FMT_UYVY10_1X20:
  193. color_format = 0x14;
  194. break;
  195. case MEDIA_BUS_FMT_UYVY12_1X24:
  196. color_format = 0x12;
  197. break;
  198. default:
  199. color_format = 0x01;
  200. break;
  201. }
  202. val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
  203. ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
  204. HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
  205. hdmi_write(hdmi, val, HDMI_TX_INVID0);
  206. /* enable tx stuffing: when de is inactive, fix the output data to 0 */
  207. val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
  208. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
  209. HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
  210. hdmi_write(hdmi, val, HDMI_TX_INSTUFFING);
  211. hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0);
  212. hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1);
  213. hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0);
  214. hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1);
  215. hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0);
  216. hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1);
  217. }
  218. static void hdmi_video_packetize(struct dw_hdmi *hdmi)
  219. {
  220. u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
  221. u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
  222. u32 color_depth = 0;
  223. uint val, vp_conf;
  224. /* set the packetizer registers */
  225. val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
  226. HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
  227. ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
  228. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
  229. hdmi_write(hdmi, val, HDMI_VP_PR_CD);
  230. hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK,
  231. HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
  232. /* data from pixel repeater block */
  233. vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
  234. HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
  235. hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK |
  236. HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
  237. hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
  238. 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
  239. hdmi_write(hdmi, remap_size, HDMI_VP_REMAP);
  240. vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
  241. HDMI_VP_CONF_PP_EN_DISABLE |
  242. HDMI_VP_CONF_YCC422_EN_DISABLE;
  243. hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK |
  244. HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
  245. vp_conf);
  246. hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK |
  247. HDMI_VP_STUFF_YCC422_STUFFING_MASK,
  248. HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
  249. HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
  250. hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
  251. output_select);
  252. }
  253. static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit)
  254. {
  255. hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK,
  256. bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
  257. }
  258. static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec)
  259. {
  260. ulong start;
  261. u32 val;
  262. start = get_timer(0);
  263. do {
  264. val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0);
  265. if (val & 0x3) {
  266. hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
  267. return 0;
  268. }
  269. udelay(100);
  270. } while (get_timer(start) < msec);
  271. return 1;
  272. }
  273. static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr)
  274. {
  275. hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0);
  276. hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
  277. hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR);
  278. hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR);
  279. hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
  280. HDMI_PHY_I2CM_OPERATION_ADDR);
  281. hdmi_phy_wait_i2c_done(hdmi, 1000);
  282. }
  283. static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable)
  284. {
  285. hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK,
  286. enable << HDMI_PHY_CONF0_PDZ_OFFSET);
  287. }
  288. static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable)
  289. {
  290. hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK,
  291. enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
  292. }
  293. static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable)
  294. {
  295. hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK,
  296. enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
  297. }
  298. static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable)
  299. {
  300. hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
  301. enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
  302. }
  303. static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable)
  304. {
  305. hdmi_mod(hdmi, HDMI_PHY_CONF0,
  306. HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
  307. enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
  308. }
  309. static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable)
  310. {
  311. hdmi_mod(hdmi, HDMI_PHY_CONF0,
  312. HDMI_PHY_CONF0_SELDATAENPOL_MASK,
  313. enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
  314. }
  315. static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi,
  316. uint enable)
  317. {
  318. hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK,
  319. enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
  320. }
  321. static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
  322. {
  323. ulong start;
  324. uint i, val;
  325. if (!hdmi->mpll_cfg || !hdmi->phy_cfg)
  326. return -1;
  327. /* gen2 tx power off */
  328. hdmi_phy_gen2_txpwron(hdmi, 0);
  329. /* gen2 pddq */
  330. hdmi_phy_gen2_pddq(hdmi, 1);
  331. /* phy reset */
  332. hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
  333. hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
  334. hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
  335. hdmi_phy_test_clear(hdmi, 1);
  336. hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
  337. HDMI_PHY_I2CM_SLAVE_ADDR);
  338. hdmi_phy_test_clear(hdmi, 0);
  339. /* pll/mpll cfg - always match on final entry */
  340. for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++)
  341. if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock)
  342. break;
  343. hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
  344. hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
  345. hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
  346. hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
  347. hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
  348. for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++)
  349. if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock)
  350. break;
  351. /*
  352. * resistance term 133ohm cfg
  353. * preemp cgf 0.00
  354. * tx/ck lvl 10
  355. */
  356. hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM);
  357. hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL);
  358. hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL);
  359. /* remove clk term */
  360. hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL);
  361. hdmi_phy_enable_power(hdmi, 1);
  362. /* toggle tmds enable */
  363. hdmi_phy_enable_tmds(hdmi, 0);
  364. hdmi_phy_enable_tmds(hdmi, 1);
  365. /* gen2 tx power on */
  366. hdmi_phy_gen2_txpwron(hdmi, 1);
  367. hdmi_phy_gen2_pddq(hdmi, 0);
  368. hdmi_phy_enable_spare(hdmi, 1);
  369. /* wait for phy pll lock */
  370. start = get_timer(0);
  371. do {
  372. val = hdmi_read(hdmi, HDMI_PHY_STAT0);
  373. if (!(val & HDMI_PHY_TX_PHY_LOCK))
  374. return 0;
  375. udelay(100);
  376. } while (get_timer(start) < 5);
  377. return -1;
  378. }
  379. static void hdmi_av_composer(struct dw_hdmi *hdmi,
  380. const struct display_timing *edid)
  381. {
  382. bool mdataenablepolarity = true;
  383. uint inv_val;
  384. uint hbl;
  385. uint vbl;
  386. hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
  387. edid->hsync_len.typ;
  388. vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
  389. edid->vsync_len.typ;
  390. /* set up hdmi_fc_invidconf */
  391. inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
  392. inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
  393. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
  394. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
  395. inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
  396. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
  397. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
  398. inv_val |= (mdataenablepolarity ?
  399. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
  400. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
  401. inv_val |= (edid->hdmi_monitor ?
  402. HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
  403. HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
  404. inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
  405. inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
  406. hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF);
  407. /* set up horizontal active pixel width */
  408. hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1);
  409. hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0);
  410. /* set up vertical active lines */
  411. hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1);
  412. hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0);
  413. /* set up horizontal blanking pixel region width */
  414. hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1);
  415. hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0);
  416. /* set up vertical blanking pixel region width */
  417. hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK);
  418. /* set up hsync active edge delay width (in pixel clks) */
  419. hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1);
  420. hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0);
  421. /* set up vsync active edge delay (in lines) */
  422. hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY);
  423. /* set up hsync active pulse width (in pixel clks) */
  424. hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1);
  425. hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0);
  426. /* set up vsync active edge delay (in lines) */
  427. hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH);
  428. }
  429. static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
  430. {
  431. switch (bus_format) {
  432. case MEDIA_BUS_FMT_RGB888_1X24:
  433. case MEDIA_BUS_FMT_RGB101010_1X30:
  434. case MEDIA_BUS_FMT_RGB121212_1X36:
  435. case MEDIA_BUS_FMT_RGB161616_1X48:
  436. return true;
  437. default:
  438. return false;
  439. }
  440. }
  441. static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
  442. {
  443. switch (bus_format) {
  444. case MEDIA_BUS_FMT_YUV8_1X24:
  445. case MEDIA_BUS_FMT_YUV10_1X30:
  446. case MEDIA_BUS_FMT_YUV12_1X36:
  447. case MEDIA_BUS_FMT_YUV16_1X48:
  448. return true;
  449. default:
  450. return false;
  451. }
  452. }
  453. static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
  454. {
  455. switch (bus_format) {
  456. case MEDIA_BUS_FMT_UYVY8_1X16:
  457. case MEDIA_BUS_FMT_UYVY10_1X20:
  458. case MEDIA_BUS_FMT_UYVY12_1X24:
  459. return true;
  460. default:
  461. return false;
  462. }
  463. }
  464. static int is_color_space_interpolation(struct dw_hdmi *hdmi)
  465. {
  466. if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
  467. return 0;
  468. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
  469. hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
  470. return 1;
  471. return 0;
  472. }
  473. static int is_color_space_decimation(struct dw_hdmi *hdmi)
  474. {
  475. if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
  476. return 0;
  477. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
  478. hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
  479. return 1;
  480. return 0;
  481. }
  482. static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
  483. {
  484. switch (bus_format) {
  485. case MEDIA_BUS_FMT_RGB888_1X24:
  486. case MEDIA_BUS_FMT_YUV8_1X24:
  487. case MEDIA_BUS_FMT_UYVY8_1X16:
  488. case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
  489. return 8;
  490. case MEDIA_BUS_FMT_RGB101010_1X30:
  491. case MEDIA_BUS_FMT_YUV10_1X30:
  492. case MEDIA_BUS_FMT_UYVY10_1X20:
  493. case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
  494. return 10;
  495. case MEDIA_BUS_FMT_RGB121212_1X36:
  496. case MEDIA_BUS_FMT_YUV12_1X36:
  497. case MEDIA_BUS_FMT_UYVY12_1X24:
  498. case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
  499. return 12;
  500. case MEDIA_BUS_FMT_RGB161616_1X48:
  501. case MEDIA_BUS_FMT_YUV16_1X48:
  502. case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
  503. return 16;
  504. default:
  505. return 0;
  506. }
  507. }
  508. static int is_color_space_conversion(struct dw_hdmi *hdmi)
  509. {
  510. return hdmi->hdmi_data.enc_in_bus_format !=
  511. hdmi->hdmi_data.enc_out_bus_format;
  512. }
  513. static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
  514. {
  515. const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
  516. unsigned int i;
  517. u32 csc_scale = 1;
  518. if (is_color_space_conversion(hdmi)) {
  519. if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
  520. csc_coeff = &csc_coeff_rgb_out_eitu601;
  521. } else if (hdmi_bus_fmt_is_rgb(
  522. hdmi->hdmi_data.enc_in_bus_format)) {
  523. csc_coeff = &csc_coeff_rgb_in_eitu601;
  524. csc_scale = 0;
  525. }
  526. }
  527. /* The CSC registers are sequential, alternating MSB then LSB */
  528. for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
  529. u16 coeff_a = (*csc_coeff)[0][i];
  530. u16 coeff_b = (*csc_coeff)[1][i];
  531. u16 coeff_c = (*csc_coeff)[2][i];
  532. hdmi_write(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
  533. hdmi_write(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
  534. hdmi_write(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
  535. hdmi_write(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
  536. hdmi_write(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
  537. hdmi_write(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
  538. }
  539. hdmi_mod(hdmi, HDMI_CSC_SCALE, HDMI_CSC_SCALE_CSCSCALE_MASK, csc_scale);
  540. }
  541. static void hdmi_video_csc(struct dw_hdmi *hdmi)
  542. {
  543. int color_depth = 0;
  544. int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
  545. int decimation = 0;
  546. /* YCC422 interpolation to 444 mode */
  547. if (is_color_space_interpolation(hdmi))
  548. interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
  549. else if (is_color_space_decimation(hdmi))
  550. decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
  551. switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
  552. case 8:
  553. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
  554. break;
  555. case 10:
  556. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
  557. break;
  558. case 12:
  559. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
  560. break;
  561. case 16:
  562. color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
  563. break;
  564. default:
  565. return;
  566. }
  567. /* Configure the CSC registers */
  568. hdmi_write(hdmi, interpolation | decimation, HDMI_CSC_CFG);
  569. hdmi_mod(hdmi, HDMI_CSC_SCALE, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
  570. color_depth);
  571. dw_hdmi_update_csc_coeffs(hdmi);
  572. }
  573. /* hdmi initialization step b.4 */
  574. static void hdmi_enable_video_path(struct dw_hdmi *hdmi, bool audio)
  575. {
  576. uint clkdis;
  577. /* control period minimum duration */
  578. hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR);
  579. hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR);
  580. hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC);
  581. /* set to fill tmds data channels */
  582. hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM);
  583. hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM);
  584. hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM);
  585. hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
  586. HDMI_MC_FLOWCTRL);
  587. /* enable pixel clock and tmds data path */
  588. clkdis = 0x7f;
  589. clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
  590. hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
  591. clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
  592. hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
  593. /* Enable csc path */
  594. if (is_color_space_conversion(hdmi)) {
  595. clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
  596. hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
  597. }
  598. /* Enable color space conversion if needed */
  599. if (is_color_space_conversion(hdmi))
  600. hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
  601. HDMI_MC_FLOWCTRL);
  602. else
  603. hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
  604. HDMI_MC_FLOWCTRL);
  605. if (audio) {
  606. clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
  607. hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
  608. }
  609. }
  610. /* workaround to clear the overflow condition */
  611. static void hdmi_clear_overflow(struct dw_hdmi *hdmi)
  612. {
  613. uint val, count;
  614. /* tmds software reset */
  615. hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
  616. val = hdmi_read(hdmi, HDMI_FC_INVIDCONF);
  617. for (count = 0; count < 4; count++)
  618. hdmi_write(hdmi, val, HDMI_FC_INVIDCONF);
  619. }
  620. static void hdmi_audio_set_format(struct dw_hdmi *hdmi)
  621. {
  622. hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
  623. HDMI_AUD_CONF0);
  624. hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
  625. HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1);
  626. hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2);
  627. }
  628. static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi)
  629. {
  630. hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ);
  631. hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0);
  632. hdmi_write(hdmi, 0x00, HDMI_AUD_INT);
  633. hdmi_write(hdmi, 0x00, HDMI_AUD_INT1);
  634. }
  635. static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi)
  636. {
  637. uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD;
  638. return !!val;
  639. }
  640. static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
  641. {
  642. u32 val;
  643. ulong start;
  644. start = get_timer(0);
  645. do {
  646. val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0);
  647. if (val & 0x2) {
  648. hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0);
  649. return 0;
  650. }
  651. udelay(100);
  652. } while (get_timer(start) < msec);
  653. return 1;
  654. }
  655. static void hdmi_ddc_reset(struct dw_hdmi *hdmi)
  656. {
  657. hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0);
  658. }
  659. static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
  660. {
  661. int shift = (block % 2) * 0x80;
  662. int edid_read_err = 0;
  663. u32 trytime = 5;
  664. u32 n;
  665. if (CONFIG_IS_ENABLED(DM_I2C) && hdmi->ddc_bus) {
  666. struct udevice *chip;
  667. edid_read_err = i2c_get_chip(hdmi->ddc_bus,
  668. HDMI_I2CM_SLAVE_DDC_ADDR,
  669. 1, &chip);
  670. if (edid_read_err)
  671. return edid_read_err;
  672. return dm_i2c_read(chip, shift, buff, HDMI_EDID_BLOCK_SIZE);
  673. }
  674. /* set ddc i2c clk which devided from ddc_clk to 100khz */
  675. hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
  676. hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
  677. hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
  678. HDMI_I2CM_DIV_STD_MODE);
  679. hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE);
  680. hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR);
  681. hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR);
  682. while (trytime--) {
  683. edid_read_err = 0;
  684. for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
  685. hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS);
  686. if (block == 0)
  687. hdmi_write(hdmi, HDMI_I2CM_OP_RD8,
  688. HDMI_I2CM_OPERATION);
  689. else
  690. hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT,
  691. HDMI_I2CM_OPERATION);
  692. if (hdmi_ddc_wait_i2c_done(hdmi, 10)) {
  693. hdmi_ddc_reset(hdmi);
  694. edid_read_err = 1;
  695. break;
  696. }
  697. buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI);
  698. }
  699. if (!edid_read_err)
  700. break;
  701. }
  702. return edid_read_err;
  703. }
  704. static const u8 pre_buf[] = {
  705. 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
  706. 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
  707. 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
  708. 0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
  709. 0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
  710. 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
  711. 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
  712. 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
  713. 0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
  714. 0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
  715. 0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
  716. 0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
  717. 0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
  718. 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
  719. 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
  720. 0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
  721. 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
  722. 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
  723. 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
  724. 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
  725. 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
  726. 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
  727. 0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
  728. 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
  729. 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
  730. 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
  731. 0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
  732. 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
  733. 0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
  734. 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  735. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  736. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
  737. };
  738. int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
  739. {
  740. int i, ret;
  741. /* hdmi phy spec says to do the phy initialization sequence twice */
  742. for (i = 0; i < 2; i++) {
  743. hdmi_phy_sel_data_en_pol(hdmi, 1);
  744. hdmi_phy_sel_interface_control(hdmi, 0);
  745. hdmi_phy_enable_tmds(hdmi, 0);
  746. hdmi_phy_enable_power(hdmi, 0);
  747. ret = hdmi_phy_configure(hdmi, mpixelclock);
  748. if (ret) {
  749. debug("hdmi phy config failure %d\n", ret);
  750. return ret;
  751. }
  752. }
  753. return 0;
  754. }
  755. int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
  756. {
  757. ulong start;
  758. start = get_timer(0);
  759. do {
  760. if (hdmi_get_plug_in_status(hdmi))
  761. return 0;
  762. udelay(100);
  763. } while (get_timer(start) < 300);
  764. return -1;
  765. }
  766. void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
  767. {
  768. /* enable phy i2cm done irq */
  769. hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
  770. HDMI_PHY_I2CM_INT_ADDR);
  771. /* enable phy i2cm nack & arbitration error irq */
  772. hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
  773. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
  774. HDMI_PHY_I2CM_CTLINT_ADDR);
  775. /* enable cable hot plug irq */
  776. hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
  777. /* clear hotplug interrupts */
  778. hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
  779. }
  780. int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size)
  781. {
  782. u32 edid_size = HDMI_EDID_BLOCK_SIZE;
  783. int ret;
  784. if (0) {
  785. edid_size = sizeof(pre_buf);
  786. memcpy(buf, pre_buf, edid_size);
  787. } else {
  788. ret = hdmi_read_edid(hdmi, 0, buf);
  789. if (ret) {
  790. debug("failed to read edid.\n");
  791. return -1;
  792. }
  793. if (buf[0x7e] != 0) {
  794. hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE);
  795. edid_size += HDMI_EDID_BLOCK_SIZE;
  796. }
  797. }
  798. return edid_size;
  799. }
  800. int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
  801. {
  802. int ret;
  803. debug("%s, mode info : clock %d hdis %d vdis %d\n",
  804. edid->hdmi_monitor ? "hdmi" : "dvi",
  805. edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
  806. hdmi_av_composer(hdmi, edid);
  807. ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
  808. if (ret)
  809. return ret;
  810. hdmi_enable_video_path(hdmi, edid->hdmi_monitor);
  811. if (edid->hdmi_monitor) {
  812. hdmi_audio_fifo_reset(hdmi);
  813. hdmi_audio_set_format(hdmi);
  814. hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ);
  815. }
  816. hdmi_video_packetize(hdmi);
  817. hdmi_video_csc(hdmi);
  818. hdmi_video_sample(hdmi);
  819. hdmi_clear_overflow(hdmi);
  820. return 0;
  821. }
  822. void dw_hdmi_init(struct dw_hdmi *hdmi)
  823. {
  824. uint ih_mute;
  825. /*
  826. * boot up defaults are:
  827. * hdmi_ih_mute = 0x03 (disabled)
  828. * hdmi_ih_mute_* = 0x00 (enabled)
  829. *
  830. * disable top level interrupt bits in hdmi block
  831. */
  832. ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/
  833. HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
  834. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
  835. if (hdmi->write_reg)
  836. hdmi_write = hdmi->write_reg;
  837. if (hdmi->read_reg)
  838. hdmi_read = hdmi->read_reg;
  839. hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
  840. /* enable i2c master done irq */
  841. hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT);
  842. /* enable i2c client nack % arbitration error irq */
  843. hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
  844. }