mscc,luton.dtsi 4.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. / {
  7. #address-cells = <1>;
  8. #size-cells = <1>;
  9. compatible = "mscc,luton";
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu@0 {
  14. compatible = "mips,mips24KEc";
  15. device_type = "cpu";
  16. reg = <0>;
  17. };
  18. };
  19. aliases {
  20. serial0 = &uart0;
  21. };
  22. sys_clk: sys-clk {
  23. compatible = "fixed-clock";
  24. #clock-cells = <0>;
  25. clock-frequency = <250000000>;
  26. };
  27. ahb_clk: ahb-clk {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <208333333>;
  31. };
  32. ahb {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. ranges = <0 0x60000000 0x10200000>;
  37. uart0: serial@10100000 {
  38. pinctrl-0 = <&uart_pins>;
  39. pinctrl-names = "default";
  40. compatible = "ns16550a";
  41. reg = <0x10100000 0x20>;
  42. clocks = <&ahb_clk>;
  43. reg-io-width = <4>;
  44. reg-shift = <2>;
  45. status = "disabled";
  46. };
  47. gpio: pinctrl@70068 {
  48. compatible = "mscc,luton-pinctrl";
  49. reg = <0x70068 0x68>;
  50. gpio-controller;
  51. #gpio-cells = <2>;
  52. gpio-ranges = <&gpio 0 0 32>;
  53. sgpio_pins: sgpio-pins {
  54. pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
  55. function = "sio";
  56. };
  57. uart_pins: uart-pins {
  58. pins = "GPIO_30", "GPIO_31";
  59. function = "uart";
  60. };
  61. };
  62. sgpio: gpio@70130 {
  63. compatible = "mscc,luton-sgpio";
  64. status = "disabled";
  65. clocks = <&sys_clk>;
  66. pinctrl-0 = <&sgpio_pins>;
  67. pinctrl-names = "default";
  68. reg = <0x0070130 0x100>;
  69. gpio-controller;
  70. #gpio-cells = <2>;
  71. gpio-ranges = <&sgpio 0 0 64>;
  72. };
  73. spi0: spi-bitbang {
  74. compatible = "mscc,luton-bb-spi";
  75. status = "okay";
  76. reg = <0x10000064 0x4>;
  77. num-chipselects = <1>;
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. };
  81. switch: switch@1010000 {
  82. compatible = "mscc,vsc7527-switch";
  83. reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
  84. <0x1f0000 0x0100>, // VTSS_TO_DEV_1
  85. <0x200000 0x0100>, // VTSS_TO_DEV_2
  86. <0x210000 0x0100>, // VTSS_TO_DEV_3
  87. <0x220000 0x0100>, // VTSS_TO_DEV_4
  88. <0x230000 0x0100>, // VTSS_TO_DEV_5
  89. <0x240000 0x0100>, // VTSS_TO_DEV_6
  90. <0x250000 0x0100>, // VTSS_TO_DEV_7
  91. <0x260000 0x0100>, // VTSS_TO_DEV_8
  92. <0x270000 0x0100>, // VTSS_TO_DEV_9
  93. <0x280000 0x0100>, // VTSS_TO_DEV_10
  94. <0x290000 0x0100>, // VTSS_TO_DEV_11
  95. <0x2a0000 0x0100>, // VTSS_TO_DEV_12
  96. <0x2b0000 0x0100>, // VTSS_TO_DEV_13
  97. <0x2c0000 0x0100>, // VTSS_TO_DEV_14
  98. <0x2d0000 0x0100>, // VTSS_TO_DEV_15
  99. <0x2e0000 0x0100>, // VTSS_TO_DEV_16
  100. <0x2f0000 0x0100>, // VTSS_TO_DEV_17
  101. <0x300000 0x0100>, // VTSS_TO_DEV_18
  102. <0x310000 0x0100>, // VTSS_TO_DEV_19
  103. <0x320000 0x0100>, // VTSS_TO_DEV_20
  104. <0x330000 0x0100>, // VTSS_TO_DEV_21
  105. <0x340000 0x0100>, // VTSS_TO_DEV_22
  106. <0x350000 0x0100>, // VTSS_TO_DEV_23
  107. <0x010000 0x1000>, // VTSS_TO_SYS
  108. <0x020000 0x1000>, // VTSS_TO_ANA
  109. <0x030000 0x1000>, // VTSS_TO_REW
  110. <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
  111. <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
  112. <0x0a0000 0x10000>; // VTSS_TO_HSIO
  113. reg-names = "port0", "port1", "port2", "port3",
  114. "port4", "port5", "port6", "port7",
  115. "port8", "port9", "port10", "port11",
  116. "port12", "port13", "port14", "port15",
  117. "port16", "port17", "port18", "port19",
  118. "port20", "port21", "port22", "port23",
  119. "sys", "ana", "rew", "gcb", "qs", "hsio";
  120. status = "okay";
  121. ethernet-ports {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. };
  125. };
  126. mdio0: mdio@700a0 {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. compatible = "mscc,luton-miim";
  130. reg = <0x700a0 0x24>;
  131. status = "disabled";
  132. };
  133. mdio1: mdio@700c4 {
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. compatible = "mscc,luton-miim";
  137. reg = <0x700c4 0x24>;
  138. status = "disabled";
  139. };
  140. hsio: syscon@10d0000 {
  141. compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
  142. reg = <0xa0000 0x10000>;
  143. serdes_hsio: serdes_hsio {
  144. compatible = "mscc,vsc7527-serdes";
  145. #phy-cells = <3>;
  146. };
  147. };
  148. };
  149. };