luton_pcb091.dts 2.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. /dts-v1/;
  6. #include "mscc,luton.dtsi"
  7. / {
  8. model = "Luton10 PCB091 Reference Board";
  9. compatible = "mscc,luton-pcb091", "mscc,luton";
  10. aliases {
  11. serial0 = &uart0;
  12. spi0 = &spi0;
  13. };
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. gpio-leds {
  18. compatible = "gpio-leds";
  19. top_dimmer {
  20. label = "pcb091:top:dimmer";
  21. gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
  22. default-state = "on";
  23. };
  24. status_green {
  25. label = "pcb091:green:status";
  26. gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
  27. default-state = "on";
  28. };
  29. status_red {
  30. label = "pcb091:red:status";
  31. gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
  32. default-state = "off";
  33. };
  34. };
  35. };
  36. &sgpio {
  37. status = "okay";
  38. mscc,sgpio-ports = <0xFFF000FF>;
  39. };
  40. &uart0 {
  41. status = "okay";
  42. };
  43. &spi0 {
  44. status = "okay";
  45. spi-flash@0 {
  46. compatible = "jedec,spi-nor";
  47. spi-max-frequency = <18000000>; /* input clock */
  48. reg = <0>; /* CS0 */
  49. spi-cs-high;
  50. };
  51. };
  52. &mdio0 {
  53. status = "okay";
  54. phy0: ethernet-phy@0 {
  55. reg = <0>;
  56. };
  57. phy1: ethernet-phy@1 {
  58. reg = <1>;
  59. };
  60. phy2: ethernet-phy@2 {
  61. reg = <2>;
  62. };
  63. phy3: ethernet-phy@3 {
  64. reg = <3>;
  65. };
  66. phy4: ethernet-phy@4 {
  67. reg = <4>;
  68. };
  69. phy5: ethernet-phy@5 {
  70. reg = <5>;
  71. };
  72. phy6: ethernet-phy@6 {
  73. reg = <6>;
  74. };
  75. phy7: ethernet-phy@7 {
  76. reg = <7>;
  77. };
  78. phy8: ethernet-phy@8 {
  79. reg = <8>;
  80. };
  81. phy9: ethernet-phy@9 {
  82. reg = <9>;
  83. };
  84. phy10: ethernet-phy@10 {
  85. reg = <10>;
  86. };
  87. phy11: ethernet-phy@11 {
  88. reg = <11>;
  89. };
  90. };
  91. &switch {
  92. ethernet-ports {
  93. port0: port@0 {
  94. reg = <0>;
  95. phy-handle = <&phy0>;
  96. };
  97. port1: port@1 {
  98. reg = <1>;
  99. phy-handle = <&phy1>;
  100. };
  101. port2: port@2 {
  102. reg = <2>;
  103. phy-handle = <&phy2>;
  104. };
  105. port3: port@3 {
  106. reg = <3>;
  107. phy-handle = <&phy3>;
  108. };
  109. port4: port@4 {
  110. reg = <4>;
  111. phy-handle = <&phy4>;
  112. };
  113. port5: port@5 {
  114. reg = <5>;
  115. phy-handle = <&phy5>;
  116. };
  117. port6: port@6 {
  118. reg = <6>;
  119. phy-handle = <&phy6>;
  120. };
  121. port7: port@7 {
  122. reg = <7>;
  123. phy-handle = <&phy7>;
  124. };
  125. port8: port@8 {
  126. reg = <8>;
  127. phy-handle = <&phy8>;
  128. };
  129. port9: port@9 {
  130. reg = <9>;
  131. phy-handle = <&phy9>;
  132. };
  133. port10: port@10 {
  134. reg = <10>;
  135. phy-handle = <&phy10>;
  136. };
  137. port11: port@11 {
  138. reg = <11>;
  139. phy-handle = <&phy11>;
  140. };
  141. };
  142. };